coreboot January 2011

coreboot@coreboot.org

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299 discussions

superiotool Makefile patch
by Christian Ruppert 09 Jan '11

09 Jan '11

As requested in IRC, a small patch for superiotool's Makefile has been attached, for more details please take a look at the patch itself. -- Regards, Christian Ruppert Role: Gentoo Linux developer, Bugzilla administrator and Infrastructure member Fingerprint: EEB1 C341 7C84 B274 6C59 F243 5EAB 0C62 B427 ABC8

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Tyan 1832DL (440BX)
by Roger 09 Jan '11

09 Jan '11

Here's several logs detailing differences between warm & cold boot raminit. (With 4 slot SDRAM banks enabled within .config. using Tyan S1846 mainboard layout.) -- Roger http://rogerx.freeshell.org/

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-Wa, --divide command not found
by Roger 09 Jan '11

09 Jan '11

I get the following after typing "make" within coreboot source folder using SeaBIOS, "/bin/sh: -Wa,--divide: command not found" ---snip--- Checking out SeaBIOS 0.6.1-stable Already up-to-date. M src/config.h Already on '0.6.1-stable' /bin/sh: -Wa,--divide: command not found Compiling whole program out/ccode.16.s ---snip--- $ fgrep coreboot/ -r -e "--divide" ./payloads/libpayload/util/xcompile/xcompile:testcc "$CC" "$CFLAGS-Wa,--divide " && CFLAGS="$CFLAGS-Wa,--divide " ./util/abuild/abuild: # i386-elf target needs --divide, for i386-linux, that's the default ./util/abuild/abuild: CC="$CC -Wa,--divide" ./util/xcompile/xcompile:testcc "$CC" "$CFLAGS-Wa,--divide " && CFLAGS="$CFLAGS-Wa,--divide " (removed .svn folders from above listing) Ah, looks like there's a missing space char between "$CFLAGS" and "-Wa" within xcompile:testcc within the above grep! (First line within the above grep listing.) Executing a little further, I'm getting another error with the flags syntax used within the code. Looks like somebody substituted commas for spaces on some of the flags used. Seems I've corrected some within both xcompile and abuild, but am still getting "/bin/sh: -fno-stack-protector: command not found" some place. Attaching an svn diff of what I have so far. -- Roger http://rogerx.freeshell.org/

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New SeaBIOS feature - boot order configuration
by Kevin O'Connor 08 Jan '11

08 Jan '11

The latest SeaBIOS git now has a feature which permits one to configure the default boot order via a CBFS file. This feature was added for QEMU, but it was done in such a way that Coreboot users can benefit as well. To use the feature, see the documentation at: http://www.coreboot.org/SeaBIOS#Configuring_boot_order For other information on obtaining and using SeaBIOS, see: http://www.coreboot.org/SeaBIOS -Kevin

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.cb files
by ali hagigat 08 Jan '11

08 Jan '11

How .cb files are created? and what they are used for?

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Support for Asus M2N-SLI Deluxe
by Michael Cassaniti 08 Jan '11

08 Jan '11

Hi, Answering the following questions from the FAQ, I have the following: Board Vendor: Asus Board Product Name: M2N-SLI Deluxe CPU Model: AMD Athlon 64FX, Socket AM2 Northbridge: Nvidia nForce 570 SLI Southbridge: Nvidia MCP55 Link to specifications: http://www.asus.com.au/product.aspx?P_ID=szSFtrap7crpBaQE Attached are the outputs of lspci, superiotool and flashrom. I noticed that a similar board (Asus M2N-E) is supported. I was hoping that porting to this board would not require major rework. Regards, Michael Cassaniti

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[commit] r6247 - trunk/src/mainboard/nokia/ip530
by repository service 07 Jan '11

07 Jan '11

Author: uwe Date: Fri Jan 7 00:03:46 2011 New Revision: 6247 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6247 Log: Various Nokia IP530 fixes. - Correct default ROM image size for this board (512KB is correct). - devicetree.cb: Add AUX I/O config (mainly GPIO settings). This allows you to control the LEDs in the front panel and JP900/JP901 can be read. - irq_tables.c: Rework PIRQ table to make more onboard devices work. Also, avoid IRQ9. - mainboard.c: Drop unneeded functions, everything is done in devicetree.cb. Signed-off-by: Marc Bertens <mbertens(a)xs4all.nl> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/nokia/ip530/Kconfig trunk/src/mainboard/nokia/ip530/devicetree.cb trunk/src/mainboard/nokia/ip530/irq_tables.c trunk/src/mainboard/nokia/ip530/mainboard.c Modified: trunk/src/mainboard/nokia/ip530/Kconfig ============================================================================== --- trunk/src/mainboard/nokia/ip530/Kconfig Thu Jan 6 03:18:12 2011 (r6246) +++ trunk/src/mainboard/nokia/ip530/Kconfig Fri Jan 7 00:03:46 2011 (r6247) @@ -27,7 +27,7 @@ select SUPERIO_SMSC_SMSCSUPERIO select SOUTHBRIDGE_TI_PCI1X2X select DRIVERS_DEC_21143 - select BOARD_ROMSIZE_KB_256 + select BOARD_ROMSIZE_KB_512 select PIRQ_ROUTE select HAVE_PIRQ_TABLE select UDELAY_TSC Modified: trunk/src/mainboard/nokia/ip530/devicetree.cb ============================================================================== --- trunk/src/mainboard/nokia/ip530/devicetree.cb Thu Jan 6 03:18:12 2011 (r6246) +++ trunk/src/mainboard/nokia/ip530/devicetree.cb Fri Jan 7 00:03:46 2011 (r6247) @@ -40,10 +40,55 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.6 on end # RTC - device pnp 3f0.7 off end # PS/2 keyboard / mouse (No connector) - device pnp 3f0.8 on end # AUX I/O - device pnp 3f0.a off end # ACPI (No support yet) + device pnp 3f0.6 on # RTC + irq 0x63 = 0x72 + end + device pnp 3f0.7 off # PS/2 keyboard / mouse (No connector) + end + device pnp 3f0.8 on # AUX I/O + irq 0x24 = 0x84 # OSC + + irq 0xB2 = 0x0C # Soft power status 1 + irq 0xB3 = 0x05 # Soft power status 2 + irq 0xC0 = 0x03 # IRQ MUX control + + irq 0xC8 = 0x10 # GP50 = (I/O) output = Flashrom enable + irq 0xCA = 0x09 # GP52 = IRQ8 (output) + irq 0xCB = 0x01 # GP53 = nROMCS (output) + irq 0xCC = 0x11 # GP54 = (I/O) input + irq 0xF9 = 0x00 # read/write GP5x lines (0x1C) + + irq 0xD0 = 0x08 # GP60 = IRQ1 + irq 0xD1 = 0x08 # GP61 = IRQ3 + irq 0xD2 = 0x08 # GP62 = IRQ4 + irq 0xD3 = 0x11 # GP63 = (I/O) input = JP901 on board + irq 0xD4 = 0x11 # GP64 = (I/O) input + irq 0xD5 = 0x11 # GP65 = (I/O) input + irq 0xD6 = 0x08 # GP66 = IRQ8 + irq 0xD7 = 0x11 # GP67 = (I/O) input + irq 0xFA = 0x00 # read/write GP6x lines (0x88) + + irq 0xE0 = 0x00 # GP10 (I/O) = output + irq 0xE1 = 0x01 # GP11 (I/O) = input + irq 0xE2 = 0x08 # GP12 = P17 + irq 0xE3 = 0x00 # GP13 (I/O) = output = LED fault on front, active low + irq 0xE4 = 0x00 # GP14 (I/O) = output + irq 0xE5 = 0x00 # GP15 (I/O) = output + irq 0xE6 = 0x01 # GP16 (I/O) = input = JP900 on board, low on short, high on open + irq 0xE7 = 0x00 # GP17 (I/O) = output = LED alert on front, active low + irq 0xF6 = 0xFF # read/write GP1x lines (0xCA) + + irq 0xEF = 0x00 # GP_INT2 disable + irq 0xF0 = 0x00 # GP_INT1 disable + irq 0xF1 = 0x00 # WDT_UNITS + irq 0xF2 = 0x00 # WDT_VAL + irq 0xF3 = 0x00 # WDT_CFG + irq 0xF4 = 0x20 # WDT_CTRL (stop-cnt) + end + device pnp 3f0.a off # ACPI (No support yet) + # irq 0x60 = 0x0C + # irq 0x61 = 0x80 + end end end device pci 7.1 on end # IDE Modified: trunk/src/mainboard/nokia/ip530/irq_tables.c ============================================================================== --- trunk/src/mainboard/nokia/ip530/irq_tables.c Thu Jan 6 03:18:12 2011 (r6246) +++ trunk/src/mainboard/nokia/ip530/irq_tables.c Fri Jan 7 00:03:46 2011 (r6247) @@ -20,6 +20,8 @@ #include <arch/pirq_routing.h> +#define PIRQ_IRQ_MASK 0x0c60 + const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ @@ -31,46 +33,51 @@ 0x122e, /* Device */ 0, /* Miniport */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x44, /* Checksum */ + 0xD7, /* Checksum */ { /** - * Rebuild of the PIRQ table, to fix the non-working on-board NIC and PCMCIA controller. + * Rebuild of the PIRQ table, to fix the non-working on-board NIC and PCMCIA controller. + * FEDCBA9876543210 + * 0x1E20 = 0001111000100000 + * 0x0C60 = 0000110001100000 */ - // Southbridge 82371 - { 0x00, (0x07 << 3) | 0x0, {{0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 }, + // Southbridge 82371EB, INTD = 0x63 + { 0x00, (0x07 << 3) | 0x0, {{0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 }, // On-board PCI-to-PCI bridge - { 0x01, (0x00 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 }, - // ETH1 on front panel - { 0x00, (0x0d << 3) | 0x0, {{0x62, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 }, - // ETH2 on front panel - { 0x00, (0x0e << 3) | 0x0, {{0x63, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 }, - // ETH3 on front panel - { 0x02, (0x04 << 3) | 0x0, {{0x60, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 }, - // ETH4 on front panel - { 0x02, (0x05 << 3) | 0x0, {{0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 }, - // PCMCIA/Cardbus controller - { 0x00, (0x0f << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 }, + { 0x01, (0x00 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0x0, 0x0 }, + // ETH1 on front panel, INTA = 0x62 = ok + { 0x00, (0x0d << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 }, + + // ETH2 on front panel, 0x63 + { 0x00, (0x0e << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 }, + // ETH3 on front panel = 0x60 + { 0x02, (0x04 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 }, + + // ETH4 on front panel, INTA = 0x61 = ok + { 0x02, (0x05 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 }, + // PCMCIA/Cardbus controller, INTA = 0x60 = ok, INTB = 0x61 = ok + { 0x00, (0x0f << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 }, // Bridge for slot 1 (top) - { 0x02, (0x07 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x64, 0x1E20}}, 0x0, 0x0 }, + { 0x02, (0x07 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x64, PIRQ_IRQ_MASK}}, 0x0, 0x0 }, // PCI compact slots 1 (top) - { 0x03, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x1, 0x0 }, - { 0x03, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x2, 0x0 }, - { 0x03, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x3, 0x0 }, - { 0x03, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x4, 0x0 }, + { 0x03, (0x04 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x1, 0x0 }, + { 0x03, (0x05 << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}}, 0x2, 0x0 }, + { 0x03, (0x06 << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}}, 0x3, 0x0 }, + { 0x03, (0x07 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0x4, 0x0 }, // Bridge for slot 2 (middle) - { 0x02, (0x06 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 }, + { 0x02, (0x06 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x0, 0x0 }, // PCI compact slots 2 (middle) - { 0x04, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x5, 0x0 }, - { 0x04, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x6, 0x0 }, - { 0x04, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x7, 0x0 }, - { 0x04, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x8, 0x0 }, + { 0x04, (0x04 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x5, 0x0 }, + { 0x04, (0x05 << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}}, 0x6, 0x0 }, + { 0x04, (0x06 << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}}, 0x7, 0x0 }, + { 0x04, (0x07 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0x8, 0x0 }, // Bridge for slot 3 (bottom) - { 0x00, (0x10 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 }, + { 0x00, (0x10 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x0, 0x0 }, // PCI compact slots 3 (bottom) - { 0x05, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x9, 0x0 }, - { 0x05, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0xA, 0x0 }, - { 0x05, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0xB, 0x0 }, - { 0x05, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0xC, 0x0 }, + { 0x05, (0x04 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x9, 0x0 }, + { 0x05, (0x05 << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}}, 0xA, 0x0 }, + { 0x05, (0x06 << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}}, 0xB, 0x0 }, + { 0x05, (0x07 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0xC, 0x0 }, } }; @@ -81,10 +88,9 @@ /** * TODO: This stub function is here until the point is solved in the - * main code of coreboot. see also arch/x86/boot/pirq_tables.c + * main code of coreboot. See also arch/x86/boot/pirq_tables.c. */ void pirq_assign_irqs(const unsigned char pIntAtoD[4]) { return; } - Modified: trunk/src/mainboard/nokia/ip530/mainboard.c ============================================================================== --- trunk/src/mainboard/nokia/ip530/mainboard.c Thu Jan 6 03:18:12 2011 (r6246) +++ trunk/src/mainboard/nokia/ip530/mainboard.c Fri Jan 7 00:03:46 2011 (r6247) @@ -20,44 +20,7 @@ #include <device/device.h> #include "chip.h" -#include <device/pci_def.h> -#include <device/pci.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <console/console.h> -#define OUTB outb -#define INB inb - -/* -* Taken from flashrom project -* Generic Super I/O helper functions -*/ -static uint8_t sio_read(uint16_t port, uint8_t reg) -{ - OUTB( reg, port ); - return ( INB( port + 1 ) ); -} - -static void sio_write(uint16_t port, uint8_t reg, uint8_t data) -{ - OUTB( reg, port ); - OUTB( data, port + 1 ); - return; -} - -static void nokia_ip530_board_enable( device_t dev ) -{ - print_debug( "Setting up IP530-Super I/O devices\n"); - sio_write( 0x20, 0x03, 0x80 ); - printk( BIOS_DEBUG, "--Register 0x03 = %X := 0x80\n", sio_read( 0x20, 0x03 ) ); - sio_write( 0x20, 0x22, 0x30 ); - printk( BIOS_DEBUG, "--Register 0x22 = %X := 0x30\n", sio_read( 0x20, 0x22 ) ); - sio_write( 0x20, 0x24, 0x84 ); - printk( BIOS_DEBUG, "--Register 0x24 = %X := 0x84\n", sio_read( 0x20, 0x24 ) ); - return; -} struct chip_operations mainboard_ops = { CHIP_NAME("Nokia IP530 Mainboard") - .enable_dev = nokia_ip530_board_enable, };

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Re: [coreboot] 440BX - DFI P2XBL - Which Target?
by Roger 07 Jan '11

07 Jan '11

>On Fri, Jan 07, 2011 at 12:06:28AM -0500, Keith Hui wrote: >Rows 50, 60 and C0 are the ones that for now really matters. If you >think sending through the whole dump (actually -xxx will do) will be >easier, I am fine with that too. For my testing, the RAM need not be >256MB, they just needs to be double-sided. And yes, only the dump from >0:0.0 will be needed. For this board, the DFI P2XBL (sorry, I keep calling it a p2bx instead!), I already have the original Manuf BIOS posted to my web page, md5sumed and has been sitting on their for years. Both, compressed & uncompressed. (If you're concerned about getting an altered BIOS, can quickly toss in the file name into Google and likely find the original Chinese(?) manufacturer website?) http://rogerx.freeshell.org/files/linuxbios/440BX.P2XBL/ (FYI: Going up one level will display the other Tyan 1832DL 440BX motherboard original manufactured BIOS as well.) I also have the log file from a lspci -xxx dump using 3 rows of double sided 256MB RAM. Beware, it's PC133 and not PC100 or PC66. But from what I understand, the bus just throttles to what the RAM is able to do on the bus, in this case, PC100 is the max bus speed. Correct me if I'm wrong though. I will likely have PC100 256MB ram on order, whether it's double sided is likely not known. >The Tyan S1832, however, has 4 slots (so if you're porting to it as >well, you must select SDRAMPWR_4DIMM), and I already have that >programming done. You'll just want to make sure the board (and RAM) >can run properly under coreboot, but I don't need to see any dumps >from it for now. I'll check into this sometime soon. -- Roger http://rogerx.freeshell.org/ 00:00.0 Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (rev 03) 00: 86 80 90 71 06 00 10 22 03 00 00 06 00 20 00 00 10: 08 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 0c 8a 00 ff 00 00 00 09 03 10 11 11 13 00 00 00 60: 10 20 30 40 50 60 60 60 00 3f e8 ff 0f ea 00 00 70: 20 1f 0a 78 aa 0a 07 01 27 ff 10 38 00 00 00 00 80: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 98 aa 00 00 04 61 00 00 00 05 00 00 00 00 00 00 a0: 02 00 10 00 03 02 00 1f 02 03 00 00 00 00 00 00 b0: 80 20 00 00 30 00 00 00 00 00 70 2f 20 10 00 00 c0: 00 00 00 00 00 00 00 00 18 0c ff ff 7f 00 00 00 d0: 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00 e0: 4c ad ff bb 8a 3e 00 80 2c d3 f7 cf 9d 3e 00 00 f0: 40 01 00 00 00 f8 00 60 20 0f 00 00 00 00 00 00 00:01.0 PCI bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX AGP bridge (rev 03) 00: 86 80 91 71 07 01 20 02 03 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 20 f0 00 a0 22 20: 00 e4 f0 e5 00 d0 f0 df 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 88 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.0 ISA bridge: Intel Corporation 82371AB/EB/MB PIIX4 ISA (rev 02) 00: 86 80 10 71 0f 00 80 02 02 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 4d 00 20 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 0b 05 07 0c 10 00 00 00 00 f2 80 00 00 00 00 00 70: 00 00 00 00 00 00 0c 0c 00 00 00 00 00 00 00 00 80: 00 00 07 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 05 00 80 60 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 21 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 30 0f 00 00 00 00 00 00 00:07.1 IDE interface: Intel Corporation 82371AB/EB/MB PIIX4 IDE (rev 01) 00: 86 80 11 71 05 00 80 02 01 80 01 01 00 20 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 07 e3 33 e3 b0 00 00 00 0d 00 02 22 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 30 0f 00 00 00 00 00 00 00:07.2 USB Controller: Intel Corporation 82371AB/EB/MB PIIX4 USB (rev 01) 00: 86 80 12 71 05 00 80 02 01 00 03 0c 00 20 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 0c 04 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 30 0f 00 00 00 00 00 00 00:07.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 02) 00: 86 80 13 71 03 00 80 02 02 00 80 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 58 1f 00 00 00 00 00 07 00 00 02 00 00 00 00 60: 00 00 00 00 94 02 83 10 00 00 00 00 00 00 00 00 70: 40 40 11 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 01 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 09 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 30 0f 00 00 00 00 00 00 00:0b.0 Multimedia audio controller: Creative Labs SB Live! EMU10k1 (rev 08) 00: 02 11 02 00 05 00 90 02 08 00 01 04 00 20 80 00 10: 01 c4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 02 11 27 80 30: 00 00 00 00 dc 00 00 00 00 00 00 00 05 01 02 14 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 01 06 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0b.1 Input device controller: Creative Labs SB Live! Game Port (rev 08) 00: 02 11 02 70 05 00 90 02 08 00 80 09 00 20 80 00 10: 01 c8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 02 11 20 00 30: 00 00 00 00 dc 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 01 06 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0d.0 Ethernet controller: Intel Corporation 82557/8/9/0/1 Ethernet Pro 100 (rev 08) 00: 86 80 29 12 07 00 90 02 08 00 00 02 08 20 00 00 10: 00 00 12 e7 01 cc 00 00 00 00 00 e7 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 0c 00 30: 00 00 00 00 dc 00 00 00 00 00 00 00 07 01 08 38 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 22 fe e0: 00 40 00 3a 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.0 Mass storage controller: Promise Technology, Inc. PDC20267 (FastTrak100/Ultra100) (rev 02) 00: 5a 10 30 4d 07 00 10 02 02 00 80 01 00 20 00 00 10: 01 d0 00 00 01 d4 00 00 01 d8 00 00 01 dc 00 00 20: 01 e0 00 00 00 00 10 e7 00 00 00 00 5a 10 33 4d 30: 00 00 00 00 58 00 00 00 00 00 00 00 0c 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: ce 32 00 00 00 00 00 00 01 00 01 00 00 00 00 00 60: f1 24 41 00 c9 f3 4f 00 09 f3 4f 00 09 f3 4f 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.0 VGA compatible controller: nVidia Corporation NV25 [GeForce4 Ti 4200] (rev a3) 00: de 10 53 02 07 00 b0 02 a3 00 00 03 00 20 00 00 10: 00 00 00 e4 08 00 00 d0 08 00 00 d8 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 00 87 30: 00 00 00 00 60 00 00 00 00 00 00 00 0b 01 05 01 40: 62 14 00 87 02 00 20 00 17 02 00 1f 02 03 00 1f 50: 01 00 00 00 01 00 00 00 ce d6 23 00 0f 00 00 00 60: 01 44 02 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

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Re: [coreboot] 440BX - DFI P2XBL - Which Target?
by Roger 07 Jan '11

07 Jan '11

On Fri, Jan 07, 2011 at 12:06:28AM -0500, Keith Hui wrote: >Rows 50, 60 and C0 are the ones that for now really matters. If you >think sending through the whole dump (actually -xxx will do) will be >easier, I am fine with that too. For my testing, the RAM need not be >256MB, they just needs to be double-sided. And yes, only the dump from >0:0.0 will be needed. For this board, the DFI P2XBL (sorry, I keep calling it a p2bx instead!), I already have the original Manuf BIOS posted to my web page, md5sumed and has been sitting on their for years. Both, compressed & uncompressed. (If you're concerned about getting an altered BIOS, can quickly toss in the file name into Google and likely find the original Chinese(?) manufacturer website?) http://rogerx.freeshell.org/files/linuxbios/440BX.P2XBL/ (FYI: Going up one level will display the other Tyan 1832DL 440BX motherboard original manufactured BIOS as well.) I also have the log file from a lspci -xxx dump using 3 rows of double sided 256MB RAM. Beware, it's PC133 and not PC100 or PC66. But from what I understand, the bus just throttles to what the RAM is able to do on the bus, in this case, PC100 is the max bus speed. Correct me if I'm wrong though. I will likely have PC100 256MB ram on order, whether it's double sided is likely not known. >The Tyan S1832, however, has 4 slots (so if you're porting to it as >well, you must select SDRAMPWR_4DIMM), and I already have that >programming done. You'll just want to make sure the board (and RAM) >can run properly under coreboot, but I don't need to see any dumps >from it for now. I'll check into this sometime soon. -- Roger http://rogerx.freeshell.org/

1 0

Patches for Nokia IP530
by Marc Bertens 07 Jan '11

07 Jan '11

Signed-off: Marc Bertens <mbertens(a)xs4all.nl> Tested: Marc Bertens <mbertens(a)xs4all.nl> I added superio registers for mainly the AUX device, to get it as the orginal bios. With its the LEDs in the front panel can be controlled and the JP900 and JP901 can be read. I changed the flash ROM size 512Kb this was from the beginning a typo. I removed the board_enable code due that all is in the devicetree.cb file now. Changed the irq_tables.c to avoid IRQ9. At the moment eth0 and eth3 work properly. The Cardbus interface the inserting en eject works correct and is seen by the OS (Linux 2.6.35 (ubuntu distro) Hard disk and CDROM work correct on IDE0. TODO: - eth1 and eth2 those still work no completely (they are buggy) - IDE1 needs to be tested - USB connections need to be found on the board and enabled - the HACK in the /arch/x86/boot/pirq_tables.c still needs to be fixed. Marc

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coreboot January 2011