coreboot January 2011

coreboot@coreboot.org

65 participants
299 discussions

[commit] r6249 - in trunk/src: cpu/amd/model_10xxx cpu/intel/model_f0x cpu/intel/model_f1x southbridge/amd/cs5536
by repository service 12 Jan '11

12 Jan '11

Author: stepan Date: Wed Jan 12 22:09:25 2011 New Revision: 6249 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6249 Log: drop unused files Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Deleted: trunk/src/cpu/amd/model_10xxx/mc_patch_01000020.h trunk/src/cpu/amd/model_10xxx/mc_patch_01000083.h trunk/src/cpu/amd/model_10xxx/mc_patch_01000084.h trunk/src/cpu/intel/model_f0x/multiplier.h trunk/src/cpu/intel/model_f1x/multiplier.h trunk/src/southbridge/amd/cs5536/smbus2.h

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Porting to ASUS K8V-X SE, found possible infinite loop in pnp_get_ioresource() (pnp_device.c)
by Alex G. 11 Jan '11

11 Jan '11

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello all, First, I want to thank everybody involved in coreboot for making it possible. I started porting coreboot code to the ASUS K8V-X SE Motherboard. It uses a Socket 754, with the VIA K8T800 / VT8237R southbridge combination, and Winbond W83627EHF SuperIO. I took the K8T890 code, adapted the PCI ID's, and removed the PCIe code for the southbridge. The VT8237R is already supported (Yay!), and looking at the datasheet, The SuperIO is almost identical (I couldn't find any difference)to the already supported W83627EHG. I took the mainboard code for the ASUS A8V-E SE as the starting point. It mostly works, except for an issue with initializing the PNP: 002e.207 device, which is (should be) the MIDI port, according to the datasheet and superiotool. The initialization code reaches pnp_get_ioresource() in src/devices/pnp_device.c, to the following point: /* Find the first bit that moves. */ while ((moving & step) == 0) { gran--; step >>= 1; } I put some printk's before the block, and the entering values are: moving = 0, and step = 32768; this leads to an infinite loop. Is there an underlying assumption that moving will never be zero, or is it safe to change the following to: /* Find the first bit that moves. */ while ((moving & step) == 0) { gran--; step >>= 1; if(step == 0) break; } If I do something like this, I can get SeaBIOS to load (but not boot yet). It might be that I'm doing something terribly wrong earlier on; therefore, if you need to look at the K8T800 or motherboard code, I can create a patch against the last svn commit (I'm curently developing over r6247). Alex G. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Fedora - http://enigmail.mozdev.org/ iQIcBAEBAgAGBQJNLIbPAAoJEL0kPHNPXJJK2BMQAI5exEh3Ege/+HcszdNHgTur cIzpZbWPcQGmI/tf9NB8cmkdRtBn5CkkwcGPc7JQYP60+kUaUePHT/9K0XLS1f/D hVDTKvzHSL1yia4yWMLzGy52Q2/2PBIDjsRMgJY2qMtGASjRp5PvAueq3WnwpxtI XQAWD7khVhnmPEF7Gx/VKRF2aYkWoosDHulzdMyiChXZnE1dkLVZ2dNyYO28a6CU 6E+5xKQySEdt+M7eWRf/CPL5MarjpbEOa6ezYnPrWZM9rJ8zFelPoBMtokDB9NDl XOZvkDJR7iriOVwVLBSOzZOlDaiSwlCCBarqLBugmHUX8N0eiVN/OBgHMryg2Hnt HovASJ0iIiLKFg4vNJk+nz9m8TFwV8GD+UpZz7N3zMiWpLb+/0XN7Clp22scECqg km7ZQlzmpy6nNjdtgI/nYgqMh0hRCm+nZF3rI1X3LPbgbT6T4TkimCs0w3/bbS3h 1RIjmaxsYTIviukoqnRX14yQNIy8Tw4+lKxhi+7ev/AP4HluAZZLBw6WcnYbefH+ 7JqckhTRItSjddslV9VJCxSPjEjUlE4FZ2rNvpeKxWdXWDu9vvMH1yYGuAv9528g EbiYF8p80TnHc2snRuPe7qTtCjvi/UvHteqLAIslJ6A1C7N50Fosp01boyc10bMV W+fciLTL4sFi3AQDJzIe =08zU -----END PGP SIGNATURE-----

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[commit] r6248 - in trunk/src: southbridge/amd/cimx_wrapper/sb800 vendorcode/amd/cimx/sb800
by repository service 11 Jan '11

11 Jan '11

Author: kerry Date: Tue Jan 11 03:15:57 2011 New Revision: 6248 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6248 Log: change a readable way to fix SB800 CIMX "multi-character constant warning". by using 'Int32FromChar' macro, instead of the ASCII code. Signed-off-by: Kerry She <kerry.she(a)amd.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.c trunk/src/vendorcode/amd/cimx/sb800/DISPATCHER.c trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h Fri Jan 7 00:03:46 2011 (r6247) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h Tue Jan 11 03:15:57 2011 (r6248) @@ -49,7 +49,15 @@ #define IOCFC 0xCFC #define IN #define OUT -#define IMAGE_SIGNATURE 'DMA$' + +#ifndef Int16FromChar +#define Int16FromChar(a,b) ((a) << 0 | (b) << 8) +#endif +#ifndef Int32FromChar +#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) +#endif + +#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') typedef UINTN AGESA_STATUS; Modified: trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.c ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.c Fri Jan 7 00:03:46 2011 (r6247) +++ trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.c Tue Jan 11 03:15:57 2011 (r6248) @@ -52,9 +52,7 @@ RsdPtr = (UINT32*) (UINTN)0xe0000; Rsdt = NULL; do { - //if ( *RsdPtr == ' DSR' && *(RsdPtr + 1) == ' RTP' ) { //gcc multi-character character constant warning - if ( *RsdPtr == 0x20445352 && *(RsdPtr + 1) == 0x20525450) { - + if ( *RsdPtr == Int32FromChar('R', 'S', 'D', ' ') && *(RsdPtr + 1) == Int32FromChar('P', 'T', 'R', ' ')) { Rsdt = (UINT32*) (UINTN) ((RSDP*)RsdPtr)->RsdtAddress; break; } Modified: trunk/src/vendorcode/amd/cimx/sb800/DISPATCHER.c ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/DISPATCHER.c Fri Jan 7 00:03:46 2011 (r6247) +++ trunk/src/vendorcode/amd/cimx/sb800/DISPATCHER.c Tue Jan 11 03:15:57 2011 (r6248) @@ -204,8 +204,7 @@ UINT16 Sum; UINT32 i; Sum = 0; - //if ( (*((UINT32*)ImagePtr) == 'DMA$' && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) { //gcc multi-character character constant warning - if ( (*((UINT32*)ImagePtr) == 0x444d4124 && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) {//'DMA$' + if ( (*((UINT32*)ImagePtr) == Int32FromChar('$', 'A', 'M', 'D') && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) { //GetImage Image size TempImagePtr = (UINT16*)ImagePtr; for ( i = 0; i < (((CIMFILEHEADER*)ImagePtr)->ImageSize); i += 2 ) { Modified: trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c Fri Jan 7 00:03:46 2011 (r6247) +++ trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c Tue Jan 11 03:15:57 2011 (r6248) @@ -769,12 +769,10 @@ } else { if ( ! (pConfig->S3Resume) ) { - //pHpetTable = (DESCRIPTION_HEADER*) ACPI_LocateTable ('TEPH'); //gcc multi-character character constant warning - pHpetTable = (DESCRIPTION_HEADER*) ACPI_LocateTable (0x54455048);//'TEPH' + pHpetTable = (DESCRIPTION_HEADER*) ACPI_LocateTable (Int32FromChar('H', 'P', 'E', 'T')); } if ( pHpetTable != NULL ) { - //pHpetTable->Signature = 'HPET'; - pHpetTable->Signature = 0x48504554; //'HPET' + pHpetTable->Signature = Int32FromChar('T', 'E', 'P', 'H'); } } }

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dmesg of a board which hangs at somewhere
by Bao, Zheng 10 Jan '11

10 Jan '11

I boot my board (Fam10/RS780/SB700) with coreboot. Sometimes it hangs at a place where it seems to a multi-core initialization. Before I debug this, could anyone give me a hint? Dmesg is below. Zheng coreboot-4.0-r964:968M Mon Jan 10 17:17:17 CST 2011 starting... BSP Family_Model: 00100f81 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1081, current patch id = 0x00000000 microcode: patch id to apply = 0x010000c4 microcode: updated to patch id = 0x010000c4 success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 02 event: 2005 data: 05 00 00 00 01 AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 00 ff Exit amd_ht_init() cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c8810f27 F3xD8: 03000c16 F3xDC: 0000543a core0 started: start_other_cores() init node: 00 cores: 05 Start other core - nodeid: 00 cores: 05 started ap apicid: c ccococoroorrrereexeex:xx:x: :: -- ----------- --{ {{{ {AA AAAPPPIIPPCIIICCCIICDDIII DD D == === 002100053 4NN NNOONDDOOODDDEEEIIEEDIIIDDD D== === 00 0000000 0CC CCCOORROOORRREEEIIEEDIIIDDD D== === 00 1000245}}3 }}} ------ ------- eequuPiimmmcc iiirr0cccroo1rrooccsocccootoooddardddee:teee: e:::eed eqq dd quuii*uiivv iaAvvvallPaaalee llenn0eenntt2nttt s rrtarrreereeevv tvvv iie idddiid rrenne ==* === A 00Pxx000 xx11x00101108803088118s11,,1ta,, , r ccctccuurueuurrrrdrreer 00xx0 ennttn*tt t A pp pPppaaa aatttcct0tcchhc4hh hsi t iddiaii drdd == t == =e 00 d 0t xx00x0*000000 00000A000000P000000 0000000000005s00 a immmicdi rcrro ciiccr oroooccscrccoodo5ooded6dde::e5ee: :0: pp _ppaapeaaattatrttcchclcch hyhh ii _ iddisid d pppllp tuttootpoo o ( aapa)aappp ppyylllg yyye == t ===_c00 pxx000xxxu001000_100111r00000ev000000 00000Ecc00ccA44c444 = :::iimmmciii1crccc0roorrr0fccooo8oocccooo1ddeddd.e::eee uu CuuppuPddpUppdaad dattaRatetteedeveed d dd tt isttooto oo n ppapoppatataatttcct 11000chehh c iidioiid dgdd == ni== =z 00 0e00xx0xdxx010.001001 ssss 0000000NB00000 0cc00cRc44c44e4 v ss issuussiuccuucoccccccnceesee essssiss A 1 2 pppuuSpccc uuuSeeSSSfeeattetttmAAAAA1MMDMMM0DMDDD_MMoSSMMRSSSpR RRRt imiz a dtd oiodddnonooonen ennee ) ii nniiiinnnistiriit__t5tt_ff_6_fiif5fiiddi0_ddvvdpvviivioiidddrdd___aa___a appainpp((pi((ss(stss ttaga e5 aagggeegee11e111)) ))) aa aappapppiicciiiiciccsdbidiid:7d:d: 0: : 00 01002_0 ar F APAA:FIFFIDyIDIIDV_DVDVIsVIVIIDeID DD tDo ou onoonpn nn () A AP 304 P:PP: : :s 0 b 0010702 0 _devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-18-0 sb700_pmio_por_init() Begin FIDVID MSR 0xc0010071 0x38ae00e4 0x38047440 FIDVID on BSP, APIC_id: 00 BSP fid = 0 Wait for AP stage 1: ap_apicid = 1 readback = 1000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2 readback = 2000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 3 readback = 3000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 4 readback = 4000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 5 readback = 5000001 common_fid(packed) = 0 common_fid = 0 End FIDVIDMSR 0xc0010071 0x38ae00e4 0x38047440 sr5650_htinit cpu_ht_freq=0. sr5650_htinit: HT1 mode ...WARM RESET... coreboot-4.0-r964:968M Mon Jan 10 17:17:17 CST 2011 starting... BSP Family_Model: 00100f81 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1081, current patch id = 0x00000000 microcode: patch id to apply = 0x010000c4 microcode: updated to patch id = 0x010000c4 success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 02 event: 2005 data: 05 00 00 00 01 AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 00 ff Exit amd_ht_init() cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c8810f27 F3xD8: 03000c16 F3xDC: 0000543a core0 started: start_other_cores() init node: 00 cores: 05 Start other core - nodeid: 00 cores: 05 started ap apicid: c cocccooororrrreexeeexx:xx:::: - ------------- -{ { {{{ A AAAAPPIPPPIIICICCCCIIDIIIDD DD === == 0100004 523 N ONNNNODOOODDDEDIEEEEIDIIIDDD D= === =0 00000000 0C OCCCCOOROORRRREEIEEEIIIDI DDDD = ==== 0 00010}2534} }}} ------ ------- eeeiAcPmmmm iiiircccco0rrrc1rooosoocdtccceaoooordddd:eeee t:::ee: qd eu qqqq*uuuuviiiia vvvlAvaaePaaln lllt0eeee2nnnn ttttrs et rrvarre reeeitvvvve diiii dddd d = nrrrrteeee ====0 xA 1P0000xxx 0x110811031000s,8888 1111tc,,,,a ruccctrcuueruurderrr nnnn* ttt pt Aa pPtppp caaaa0htttt cccc4hhhhsi td iia iidr=dddt 0====e dx0 00xx 000s0xx0*0000 0000000000A0000P0000 0000000005 t 0000 iiccrctremmmmodcii rrdrccor ooeoocc:ccsro ooo5dpdddeaeee6t:::5: 0 cpp_phpaea aaatitttcdcccr hhhlh y tii_ioidsd dde p=ppttptttopooou p laaa(aypp)p pp 000 l llly0yyyg ex =t0===_1 0000c0xxxp0x00u0001_0111rc000040000e0000v = 0cccEcm44A4i4 r ::d:: a iici1ccoccrrdrr0oeoo0o:ccfccoo8oo d1ddud.eepee utuuuCppeppPdUdddd aa aatttttReoeeee ddvdd ptittatsootoo c pphppn aaoaaitttttc 00c0dhrhh he = ii iicd0ddodx g ==n==0 i 1 z00000xx0xxe0000d0011.1100 ccee004000 00N0B00 0 ccscc44u44R c e c v ssisseusuusuciccscocc ss seens c ssiss p S uuuucc.tccApppp i MSSSDSfeaeeeMmtttStAAARA1MM M0MDD_DDMoMMM SSSSdpRRRotR ni em izaitn i ddoiddontooo(_nnnnfeeee) d vsiiiinnnirniid5iit_6ttt_s5___t0ffff_iiiiaddddgpvvveovii2riid _dddai____nsssspittttiaaaactggg geed iiicee2:222 0aaaap1pppi ccc

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[PATCH] fix SB800 CIMX "multi-character constant warning"
by She, Kerry 10 Jan '11

10 Jan '11

Hello, compile the original AMD SB800 CIMX code, GCC would complain “multi-character constant warning”. This patch using 'Int32FromChar' macro replace the multi-character constant to fix it. Signed-off-by Kerry She <kerry.she(a)amd.com>

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Trac reminder: list of new ticket(s)
by coreboot tracker 10 Jan '11

10 Jan '11

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Re: [coreboot] dmesg of a board which hangs at somewhere
by Xavi Drudis Ferran 10 Jan '11

10 Jan '11

On Mon 10/01/11 06:59 , "Bao, Zheng" <Zheng.Bao(a)amd.com> wrote: > I boot my board (Fam10/RS780/SB700) with coreboot. Sometimes it hangs at > a place where it seems to a multi-core initialization. Before I debug > this, could anyone give me a hint? > What CPU revision is this ? HY-D1 ? I think there's not even a constant in amddefs.h for it ? The last message seems to be from fidvid.c stage 2 . I'm very slowly looking at this code and it seems to be revision C3 and possibly others may be only half supported. In BIOS and Kernel Developer Guide 2.4.2.6 (IIRC) There are a dozen requirements and I'm looking at the code little by little to see if coreboot does it all. I've found or added code to fulfil the first 5-6 but I suspect the other half may not be performed or not completely, and it may depend on the CPU revision (some steps are noops for some revisions). What I have is sychronized with svn from some weeks ago and it may not even compile, and it's also ugly and full of silly notes in comments, and not tested. But I have little time for it so it'll take me a long while to finish if I ever do.

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Boot slows down on Tyan 1832DL (440BX)
by Roger 10 Jan '11

10 Jan '11

After booting and after SeaBIOS picks-up things, the boot process slows when executing the kernel. Although this box has an add-in PCI SATA card with two SATA drives, I believe I'm seeing the slow down by no matter what boot method I use. Attaching full log. This one details booting from a SATA hard drive printing specific error codes to stdout. -- Roger http://rogerx.freeshell.org/

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Patch to superiotool - add basic indexing of devices detected at IO ports
by Frantisek Rysanek 10 Jan '11

10 Jan '11

This patch adds a simple table of SuperIO chips already detected in the system. This allows superiotool to properly avoid scanning the same IO port again by another vendor-specific probe, after some device has already been found on that particular port. The table of chips detected contains entries that, apart from the IO port known to be "inhabited", also relate the port to a particular "chip entry" (struct superio_registers*). There's no immediate use for this, but in the future it could facilitate further functionality enhancements, such as - separation of the "dump" function from the "detect" function - write support (with validity checking of the desired LDN/CR) As suggested by Mr. Hendricks, the vendor-specific probe functions now return a result code, indicating that a particular chip was found and which one that was, or that none was detected. The simple "framework" is headquartered in superiotool.c, with some necessary mods to superiotool.h. All the existing "vendor-specific" C files have been adapted to make use of this "framework". Apart from this addition, the patch scraps some previous attempts at the same functionality, and moves some table definitions from superiotool.h to superiotool.c, where they seem to belong. Signed-off-by: Frank Rysanek <Frantisek.Rysanek(a)post.cz> --- Tested on my AEC-6811 with two Winbond SuperIO chips. Note that the Winbond probe comes last in the "sequence of vendors", so my test is not entirely significant :-) I've tried the recommended method of deriving the patch via "svn diff". The resulting patch however fails to apply cleanly (hunk failed...). But if I try the bare "diff -Naur", the resulting patch *does* apply just fine. Go figure... Attached you'll find the manual diff that works for me. The following section of this message contains a file attachment prepared for transmission using the Internet MIME message format. If you are using Pegasus Mail, or any other MIME-compliant system, you should be able to save it or view it from within your mailer. If you cannot, please ask your system administrator for assistance. ---- File information ----------- File: device_counting.diff Date: 9 Jan 2011, 22:25 Size: 20401 bytes. Type: Unknown

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Re: [coreboot] Tyan 1832DL (440BX)
by Keith Hui 10 Jan '11

10 Jan '11

Looking at your northbridge dump, looks like you plugged in all the RAM you have for 1GB. I believe that only works on 440BX with ECC RAM and we still don't have code to support them. Could that be causing the failure? Three sticks for 768MB should work. Try that.

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coreboot January 2011