coreboot January 2011

coreboot@coreboot.org

65 participants
299 discussions

superiotool sometimes skips further SuperIO chips in the system - suggested remedy included
by Frantisek Rysanek 03 Jan '11

03 Jan '11

Dear maintainers of the superiotool, I have the following "feature request" (maybe not a bug report): I have this idea that superiotool should be able to detect more than one SuperIO chip in the system. Such detection of multiple chips may work in some cases, but may fail in others. The primary cause seems to be that winbond.c :: probe_idregs_winbond() and ite.c :: probe_idregs_ite() call if (chip_found) return; // this is a global variable! after every "init sequence" tried. Therefore, after the first chip detected (of any kind), only the first init sequence is ever tried, in any subsequent calls to the aforementioned probe_* functions. My immediate hack was to comment out all occurrences of if (chip_found) return; in those probe functions. Makes me wonder if this has some adverse effects, such as repeatedly scanning some EFER bases / init sequences by probes belonging to different chip families. And my conclusion for the moment is that this repeated probing should be harmless, and that the current behavior (stop after the first init sequence tried) is flawed anyway :-) My motivation is simple: right now I'm working with an embedded PC that has two SuperIO chips on the inside: W83627 + W83977. But I've seen other models in the past as well. Your SuperIOtool is quite useful for a quick overview of the SuperIO chips in the system, including a thorough dump of their registers. In the past I myself have written and reused some simple snippet of code / a tiny library (in DOS) to help me debug/tweak SuperIO stuff, but I never got as far as making it truly universal and extensible. As for SuperIOtool, I could fancy a writing capability, and maybe an external configuration file, potentially allowing for extensions without coding in C, maybe human-readable interpretations / annotations of the register dump etc - but I admit that's too much work to be worth the bother, certainly for me at the moment :-) Keep up the excellent work that you're doing... Frank Rysanek

4 6

Support for Google CR-48/Atom N455
by Brandon White 03 Jan '11

03 Jan '11

Hello all. Someone was accidentally sent a CR-48 that had Windows 7 pre-installed and an actual BIOS instead of Google's EFI. Anways, he uploaded the BIOS, I was able to flash it and after that I installed Ubuntu as a dual boot with Chrome OS. I was wondering if Coreboot was possible on this machine? I have attached everything asked for in the wiki. Thanks, Brandon

2 2

Trac reminder: list of new ticket(s)
by coreboot tracker 03 Jan '11

03 Jan '11

1 0

raminit.c example
by Roger 03 Jan '11

03 Jan '11

I've read over the src/northbridge/intel/i440bx/raminit.c, but am still a little mystified on setting the settings. I can see where settings are set to zero (or default), but when I look at other settings, the values don't seem to match up to what is well documented within the comments. A good easy example would be setting DRAMC: DRAMC, 0x00, 0x08, Is the "0x00" designated by "000" as documented? Hex? What does "0x08" mean? -- Roger http://rogerx.freeshell.org/

2 2

help with core boot and compaq deskpro ep c500
by William juice 03 Jan '11

03 Jan '11

i have just seen and read about core boot and i was woundering about, if a Compaq Deskpro EP C500 <(old computer) could have core boot instaled with payload as seabios for a bios replacment due to slow booting(linux) and limited settings in bios ect. i have posted the hp link to the compaq bios ect below http://h20000.www2.hp.com/bizsupport/TechSupport/DriverDownload.jsp?prodNam… thx ~SIN~

2 1

Re: [coreboot] help with core boot and compaq deskpro ep c500
by anders＠jenbo.dk 03 Jan '11

03 Jan '11

Give us The output from lspci -tvnn Mvh Anders ----- Reply message ----- Fra: "William juice" <snes9xd(a)gmail.com> Dato: man., jan. 3, 2011 08:58 Emne: [coreboot] help with core boot and compaq deskpro ep c500 Til: <coreboot(a)coreboot.org> i have just seen and read about core boot and i was woundering about, if a Compaq Deskpro EP C500 <(old computer) could have core boot instaled with payload as seabios for a bios replacment due to slow booting(linux) and limited settings in bios ect. i have posted the hp link to the compaq bios ect below http://h20000.www2.hp.com/bizsupport/TechSupport/DriverDownload.jsp?prodNam… thx ~SIN~

1 0

Need pointers
by Keith Hui 02 Jan '11

02 Jan '11

While I try to help Roger with his raminit problems and/or port coreboot to SIS630, I also want to get the SCSI part of my P2B-LS fully working. This also means implementing an option table for this board. I am looking for pointers on what to read to know the relationships between option tables, cmos.layout, and where to implement a new option, especially one that isn't directly related to the southbridge, or is board specific. --- For the last few times I have tried leaving the SCSI part enabled on the board, I am getting lots of noise from the linux aic78xx driver, and the SCSI BIOS, extracted from OEM BIOS image and added to the coreboot image, wouldn't even run properly. I know the factory BIOS provides a setting to control the onboard termination of 2 of the 3 SCSI ports on the board (the third is always terminated), and I'm suspecting this is what making SCSI fail. So I have to implement it. This is where the option table comes in to play. Meanwhile I am mapping out where all the factory BIOS settings are in the nvram, so I can get the eventual cmos.layout as close to OEM as possible. I got some of it mapped out, by painstakingly toggling every option in its setup screen that won't immediately brick my test machine and taking a before and after nvram dump, looking for differences. --- Thanks Keith

2 1

incomplete documentation
by ali hagigat 02 Jan '11

02 Jan '11

Coreboot declares a complete documentation of some chips by: http://www.coreboot.org/Datasheets and particularly 82815E by: http://www.coreboot.org/Datasheets#Intel_82801BA.2FBAM_.28ICH2.29 Where is the documentation for integrated graphics controller of this chip? Only the explanation of some configuration registers are available. Why Coreboot site maintainers do not clearly express that the necessary documentation for BIOS developing is not available? Even the open documents you have added in Data-sheet section are not complete.

4 3

[commit] r6237 - in trunk/src/southbridge/amd/cimx_wrapper: . sb800
by repository service 02 Jan '11

02 Jan '11

Author: uwe Date: Sun Jan 2 00:36:03 2011 New Revision: 6237 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6237 Log: src/southbridge/amd/cimx_wrapper: Run dos2unix on the files. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/southbridge/amd/cimx_wrapper/Kconfig trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h Modified: trunk/src/southbridge/amd/cimx_wrapper/Kconfig ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/Kconfig Sun Jan 2 00:30:37 2011 (r6236) +++ trunk/src/southbridge/amd/cimx_wrapper/Kconfig Sun Jan 2 00:36:03 2011 (r6237) @@ -16,14 +16,15 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -# + config SOUTHBRIDGE_AMD_CIMX_WRAPPER - bool - default n + bool + default n config SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 - bool - select IOAPIC - select SOUTHBRIDGE_AMD_CIMX_WRAPPER + bool + select IOAPIC + select SOUTHBRIDGE_AMD_CIMX_WRAPPER source src/southbridge/amd/cimx_wrapper/sb800/Kconfig + Modified: trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc Sun Jan 2 00:30:37 2011 (r6236) +++ trunk/src/southbridge/amd/cimx_wrapper/Makefile.inc Sun Jan 2 00:36:03 2011 (r6237) @@ -16,4 +16,6 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # + subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800) += sb800 + Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h Sun Jan 2 00:30:37 2011 (r6236) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h Sun Jan 2 00:36:03 2011 (r6237) @@ -1,375 +1,375 @@ -/***************************************************************************** - * AMD Generic Encapsulated Software Architecture */ -/** - * @file - * - * Agesa structures and definitions - * - * Contains AMD AGESA/CIMx core interface - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - * @e \$Revision:$ @e \$Date:$ - */ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#ifndef _AMD_H_ -#define _AMD_H_ - -// AGESA Types and Definitions - -#ifndef NULL - #define NULL 0 -#endif - -#define LAST_ENTRY 0xFFFFFFFF -#define IOCF8 0xCF8 -#define IOCFC 0xCFC -#define IN -#define OUT -#define IMAGE_SIGNATURE 'DMA$' - -typedef UINTN AGESA_STATUS; - -#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) -#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) -#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) -#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) -#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) -#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) -#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) - -typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); -typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr); -typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr); - -///This allocation type is used by the AmdCreateStruct entry point -typedef enum { - PreMemHeap = 0, ///< Create heap in cache. - PostMemDram, ///< Create heap in memory. - ByHost ///< Create heap by Host. -} ALLOCATION_METHOD; - -/// These width descriptors are used by the library function, and others, to specify the data size -typedef enum ACCESS_WIDTH { - AccessWidth8 = 1, ///< Access width is 8 bits. - AccessWidth16, ///< Access width is 16 bits. - AccessWidth32, ///< Access width is 32 bits. - AccessWidth64, ///< Access width is 64 bits. - - AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. - AccessS3SaveWidth16, ///< Save 16 bits data. - AccessS3SaveWidth32, ///< Save 32 bits data. - AccessS3SaveWidth64, ///< Save 64 bits data. -} ACCESS_WIDTH; - -// AGESA Structures - -/// The standard header for all AGESA services. -typedef struct _AMD_CONFIG_PARAMS { - IN UINT32 ImageBasePtr; ///< The AGESA Image base address. - IN UINT32 Func; ///< The service desired, @sa dispatch.h. - IN UINT32 AltImageBasePtr; ///< Alternate Image location - IN UINT32 PcieBasePtr; ///< PCIe MMIO Base address, if configured. - union { ///< Callback pointer - IN UINT64 PlaceHolder; ///< Place holder - IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA - } CALLBACK; - IN OUT UINT32 Reserved[2]; ///< This space is reserved for future use. -} AMD_CONFIG_PARAMS; - - -/// AGESA Binary module header structure -typedef struct _AMD_IMAGE_HEADER { - IN UINT32 Signature; ///< Binary Signature - IN CHAR8 CreatorID[8]; ///< 8 characters ID - IN CHAR8 Version[12]; ///< 12 characters version - IN UINT32 ModuleInfoOffset; ///< Offset of module - IN UINT32 EntryPointAddress; ///< Entry address - IN UINT32 ImageBase; ///< Image base - IN UINT32 RelocTableOffset; ///< Relocate Table offset - IN UINT32 ImageSize; ///< Size - IN UINT16 Checksum; ///< Checksum - IN UINT8 ImageType; ///< Type - IN UINT8 V_Reserved; ///< Reserved -} AMD_IMAGE_HEADER; - -/// AGESA Binary module header structure -typedef struct _AMD_MODULE_HEADER { - IN UINT32 ModuleHeaderSignature; ///< Module signature - IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID - IN CHAR8 ModuleVersion[12]; ///< 12 characters version - IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher - IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link -} AMD_MODULE_HEADER; - -#define FUNC_0 0 // bit-placed for PCI address creation -#define FUNC_1 1 -#define FUNC_2 2 -#define FUNC_3 3 -#define FUNC_4 4 -#define FUNC_5 5 -#define FUNC_6 6 -#define FUNC_7 7 - -// SBDFO - Segment Bus Device Function Offset -// 31:28 Segment (4-bits) -// 27:20 Bus (8-bits) -// 19:15 Device (5-bits) -// 14:12 Function (3-bits) -// 11:00 Offset (12-bits) - -#if 0 -#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \ - (((UINT32) (Dev)) << 15) | (((UINT32) (Fun)) << 12) | ((UINT32) (Off))) -#endif -#define ILLEGAL_SBDFO 0xFFFFFFFF - -/// CPUID data received registers format -typedef struct _SB_CPUID_DATA { - IN OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX - IN OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX - IN OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX - IN OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX -} SB_CPUID_DATA; - -#define WARM_RESET 1 -#define COLD_RESET 2 // Cold reset -#define RESET_CPU 4 // Triggers a CPU reset - -/// HT frequency for external callbacks -typedef enum { - HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks - HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks - HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks - HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks - HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks - HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks - HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks - HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks - HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks - HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks - HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks - HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks - HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks - HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks - HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks - HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks -} HT_FREQUENCIES; - -#ifndef BIT0 - #define BIT0 0x0000000000000001ull -#endif -#ifndef BIT1 - #define BIT1 0x0000000000000002ull -#endif -#ifndef BIT2 - #define BIT2 0x0000000000000004ull -#endif -#ifndef BIT3 - #define BIT3 0x0000000000000008ull -#endif -#ifndef BIT4 - #define BIT4 0x0000000000000010ull -#endif -#ifndef BIT5 - #define BIT5 0x0000000000000020ull -#endif -#ifndef BIT6 - #define BIT6 0x0000000000000040ull -#endif -#ifndef BIT7 - #define BIT7 0x0000000000000080ull -#endif -#ifndef BIT8 - #define BIT8 0x0000000000000100ull -#endif -#ifndef BIT9 - #define BIT9 0x0000000000000200ull -#endif -#ifndef BIT10 - #define BIT10 0x0000000000000400ull -#endif -#ifndef BIT11 - #define BIT11 0x0000000000000800ull -#endif -#ifndef BIT12 - #define BIT12 0x0000000000001000ull -#endif -#ifndef BIT13 - #define BIT13 0x0000000000002000ull -#endif -#ifndef BIT14 - #define BIT14 0x0000000000004000ull -#endif -#ifndef BIT15 - #define BIT15 0x0000000000008000ull -#endif -#ifndef BIT16 - #define BIT16 0x0000000000010000ull -#endif -#ifndef BIT17 - #define BIT17 0x0000000000020000ull -#endif -#ifndef BIT18 - #define BIT18 0x0000000000040000ull -#endif -#ifndef BIT19 - #define BIT19 0x0000000000080000ull -#endif -#ifndef BIT20 - #define BIT20 0x0000000000100000ull -#endif -#ifndef BIT21 - #define BIT21 0x0000000000200000ull -#endif -#ifndef BIT22 - #define BIT22 0x0000000000400000ull -#endif -#ifndef BIT23 - #define BIT23 0x0000000000800000ull -#endif -#ifndef BIT24 - #define BIT24 0x0000000001000000ull -#endif -#ifndef BIT25 - #define BIT25 0x0000000002000000ull -#endif -#ifndef BIT26 - #define BIT26 0x0000000004000000ull -#endif -#ifndef BIT27 - #define BIT27 0x0000000008000000ull -#endif -#ifndef BIT28 - #define BIT28 0x0000000010000000ull -#endif -#ifndef BIT29 - #define BIT29 0x0000000020000000ull -#endif -#ifndef BIT30 - #define BIT30 0x0000000040000000ull -#endif -#ifndef BIT31 - #define BIT31 0x0000000080000000ull -#endif -#ifndef BIT32 - #define BIT32 0x0000000100000000ull -#endif -#ifndef BIT33 - #define BIT33 0x0000000200000000ull -#endif -#ifndef BIT34 - #define BIT34 0x0000000400000000ull -#endif -#ifndef BIT35 - #define BIT35 0x0000000800000000ull -#endif -#ifndef BIT36 - #define BIT36 0x0000001000000000ull -#endif -#ifndef BIT37 - #define BIT37 0x0000002000000000ull -#endif -#ifndef BIT38 - #define BIT38 0x0000004000000000ull -#endif -#ifndef BIT39 - #define BIT39 0x0000008000000000ull -#endif -#ifndef BIT40 - #define BIT40 0x0000010000000000ull -#endif -#ifndef BIT41 - #define BIT41 0x0000020000000000ull -#endif -#ifndef BIT42 - #define BIT42 0x0000040000000000ull -#endif -#ifndef BIT43 - #define BIT43 0x0000080000000000ull -#endif -#ifndef BIT44 - #define BIT44 0x0000100000000000ull -#endif -#ifndef BIT45 - #define BIT45 0x0000200000000000ull -#endif -#ifndef BIT46 - #define BIT46 0x0000400000000000ull -#endif -#ifndef BIT47 - #define BIT47 0x0000800000000000ull -#endif -#ifndef BIT48 - #define BIT48 0x0001000000000000ull -#endif -#ifndef BIT49 - #define BIT49 0x0002000000000000ull -#endif -#ifndef BIT50 - #define BIT50 0x0004000000000000ull -#endif -#ifndef BIT51 - #define BIT51 0x0008000000000000ull -#endif -#ifndef BIT52 - #define BIT52 0x0010000000000000ull -#endif -#ifndef BIT53 - #define BIT53 0x0020000000000000ull -#endif -#ifndef BIT54 - #define BIT54 0x0040000000000000ull -#endif -#ifndef BIT55 - #define BIT55 0x0080000000000000ull -#endif -#ifndef BIT56 - #define BIT56 0x0100000000000000ull -#endif -#ifndef BIT57 - #define BIT57 0x0200000000000000ull -#endif -#ifndef BIT58 - #define BIT58 0x0400000000000000ull -#endif -#ifndef BIT59 - #define BIT59 0x0800000000000000ull -#endif -#ifndef BIT60 - #define BIT60 0x1000000000000000ull -#endif -#ifndef BIT61 - #define BIT61 0x2000000000000000ull -#endif -#ifndef BIT62 - #define BIT62 0x4000000000000000ull -#endif -#ifndef BIT63 - #define BIT63 0x8000000000000000ull -#endif - -#endif +/***************************************************************************** + * AMD Generic Encapsulated Software Architecture */ +/** + * @file + * + * Agesa structures and definitions + * + * Contains AMD AGESA/CIMx core interface + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Include + * @e \$Revision:$ @e \$Date:$ + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#ifndef _AMD_H_ +#define _AMD_H_ + +// AGESA Types and Definitions + +#ifndef NULL + #define NULL 0 +#endif + +#define LAST_ENTRY 0xFFFFFFFF +#define IOCF8 0xCF8 +#define IOCFC 0xCFC +#define IN +#define OUT +#define IMAGE_SIGNATURE 'DMA$' + +typedef UINTN AGESA_STATUS; + +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) + +typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + +// AGESA Structures + +/// The standard header for all AGESA services. +typedef struct _AMD_CONFIG_PARAMS { + IN UINT32 ImageBasePtr; ///< The AGESA Image base address. + IN UINT32 Func; ///< The service desired, @sa dispatch.h. + IN UINT32 AltImageBasePtr; ///< Alternate Image location + IN UINT32 PcieBasePtr; ///< PCIe MMIO Base address, if configured. + union { ///< Callback pointer + IN UINT64 PlaceHolder; ///< Place holder + IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA + } CALLBACK; + IN OUT UINT32 Reserved[2]; ///< This space is reserved for future use. +} AMD_CONFIG_PARAMS; + + +/// AGESA Binary module header structure +typedef struct _AMD_IMAGE_HEADER { + IN UINT32 Signature; ///< Binary Signature + IN CHAR8 CreatorID[8]; ///< 8 characters ID + IN CHAR8 Version[12]; ///< 12 characters version + IN UINT32 ModuleInfoOffset; ///< Offset of module + IN UINT32 EntryPointAddress; ///< Entry address + IN UINT32 ImageBase; ///< Image base + IN UINT32 RelocTableOffset; ///< Relocate Table offset + IN UINT32 ImageSize; ///< Size + IN UINT16 Checksum; ///< Checksum + IN UINT8 ImageType; ///< Type + IN UINT8 V_Reserved; ///< Reserved +} AMD_IMAGE_HEADER; + +/// AGESA Binary module header structure +typedef struct _AMD_MODULE_HEADER { + IN UINT32 ModuleHeaderSignature; ///< Module signature + IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID + IN CHAR8 ModuleVersion[12]; ///< 12 characters version + IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher + IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link +} AMD_MODULE_HEADER; + +#define FUNC_0 0 // bit-placed for PCI address creation +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7 + +// SBDFO - Segment Bus Device Function Offset +// 31:28 Segment (4-bits) +// 27:20 Bus (8-bits) +// 19:15 Device (5-bits) +// 14:12 Function (3-bits) +// 11:00 Offset (12-bits) + +#if 0 +#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \ + (((UINT32) (Dev)) << 15) | (((UINT32) (Fun)) << 12) | ((UINT32) (Off))) +#endif +#define ILLEGAL_SBDFO 0xFFFFFFFF + +/// CPUID data received registers format +typedef struct _SB_CPUID_DATA { + IN OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX + IN OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX + IN OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX + IN OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX +} SB_CPUID_DATA; + +#define WARM_RESET 1 +#define COLD_RESET 2 // Cold reset +#define RESET_CPU 4 // Triggers a CPU reset + +/// HT frequency for external callbacks +typedef enum { + HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks + HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks + HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks + HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks + HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks + HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks + HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks + HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks + HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks + HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks + HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks + HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks + HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks + HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks + HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks + HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks +} HT_FREQUENCIES; + +#ifndef BIT0 + #define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 + #define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 + #define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 + #define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 + #define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 + #define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 + #define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 + #define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 + #define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 + #define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 + #define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 + #define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 + #define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 + #define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 + #define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 + #define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 + #define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 + #define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 + #define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 + #define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 + #define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 + #define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 + #define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 + #define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 + #define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 + #define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 + #define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 + #define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 + #define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 + #define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 + #define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 + #define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 + #define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 + #define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 + #define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 + #define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 + #define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 + #define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 + #define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 + #define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 + #define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 + #define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 + #define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 + #define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 + #define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 + #define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 + #define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 + #define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 + #define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 + #define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 + #define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 + #define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 + #define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 + #define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 + #define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 + #define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 + #define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 + #define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 + #define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 + #define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 + #define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 + #define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 + #define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 + #define BIT63 0x8000000000000000ull +#endif + +#endif Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h Sun Jan 2 00:30:37 2011 (r6236) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h Sun Jan 2 00:36:03 2011 (r6237) @@ -1,174 +1,174 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#ifndef _AMD_SB_LIB_H_ -#define _AMD_SB_LIB_H_ - -typedef CHAR8 *va_list; -#ifndef _INTSIZEOF - #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) ) -#endif - -// Also support coding convention rules for var arg macros -#ifndef va_start - #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) ) -#endif -#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) -#define va_end(ap) ( ap = (va_list)0 ) - -#pragma pack (push, 1) - -#define IMAGE_ALIGN 32*1024 -#define NUM_IMAGE_LOCATION 32 - -//Entry Point Call -typedef void (*CIM_IMAGE_ENTRY) (void* pConfig); - -//Hook Call - -typedef struct _CIMFILEHEADER -{ - UINT32 AMDLogo; - UINT64 CreatorID; - UINT32 Version1; - UINT32 Version2; - UINT32 Version3; - UINT32 ModuleInfoOffset; - UINT32 EntryPoint; - UINT32 ImageBase; - UINT32 RelocTableOffset; - UINT32 ImageSize; - UINT16 CheckSum; - UINT8 ImageType; - UINT8 Reserved2; -} CIMFILEHEADER; - -#ifndef BIT0 - #define BIT0 (1 << 0) -#endif -#ifndef BIT1 - #define BIT1 (1 << 1) -#endif -#ifndef BIT2 - #define BIT2 (1 << 2) -#endif -#ifndef BIT3 - #define BIT3 (1 << 3) -#endif -#ifndef BIT4 - #define BIT4 (1 << 4) -#endif -#ifndef BIT5 - #define BIT5 (1 << 5) -#endif -#ifndef BIT6 - #define BIT6 (1 << 6) -#endif -#ifndef BIT7 - #define BIT7 (1 << 7) -#endif -#ifndef BIT8 - #define BIT8 (1 << 8) -#endif -#ifndef BIT9 - #define BIT9 (1 << 9) -#endif -#ifndef BIT10 - #define BIT10 (1 << 10) -#endif -#ifndef BIT11 - #define BIT11 (1 << 11) -#endif -#ifndef BIT12 - #define BIT12 (1 << 12) -#endif -#ifndef BIT13 - #define BIT13 (1 << 13) -#endif -#ifndef BIT14 - #define BIT14 (1 << 14) -#endif -#ifndef BIT15 - #define BIT15 (1 << 15) -#endif -#ifndef BIT16 - #define BIT16 (1 << 16) -#endif -#ifndef BIT17 - #define BIT17 (1 << 17) -#endif -#ifndef BIT18 - #define BIT18 (1 << 18) -#endif -#ifndef BIT19 - #define BIT19 (1 << 19) -#endif -#ifndef BIT20 - #define BIT20 (1 << 20) -#endif -#ifndef BIT21 - #define BIT21 (1 << 21) -#endif -#ifndef BIT22 - #define BIT22 (1 << 22) -#endif -#ifndef BIT23 - #define BIT23 (1 << 23) -#endif -#ifndef BIT24 - #define BIT24 (1 << 24) -#endif -#ifndef BIT25 - #define BIT25 (1 << 25) -#endif -#ifndef BIT26 - #define BIT26 (1 << 26) -#endif -#ifndef BIT27 - #define BIT27 (1 << 27) -#endif -#ifndef BIT28 - #define BIT28 (1 << 28) -#endif -#ifndef BIT29 - #define BIT29 (1 << 29) -#endif -#ifndef BIT30 - #define BIT30 (1 << 30) -#endif -#ifndef BIT31 - #define BIT31 (1 << 31) -#endif - -#pragma pack (pop) - -typedef enum -{ - AccWidthUint8 = 0, - AccWidthUint16, - AccWidthUint32, -} ACC_WIDTH; - -#define S3_SAVE 0x80 - -#endif +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#ifndef _AMD_SB_LIB_H_ +#define _AMD_SB_LIB_H_ + +typedef CHAR8 *va_list; +#ifndef _INTSIZEOF + #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) ) +#endif + +// Also support coding convention rules for var arg macros +#ifndef va_start + #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) ) +#endif +#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) +#define va_end(ap) ( ap = (va_list)0 ) + +#pragma pack (push, 1) + +#define IMAGE_ALIGN 32*1024 +#define NUM_IMAGE_LOCATION 32 + +//Entry Point Call +typedef void (*CIM_IMAGE_ENTRY) (void* pConfig); + +//Hook Call + +typedef struct _CIMFILEHEADER +{ + UINT32 AMDLogo; + UINT64 CreatorID; + UINT32 Version1; + UINT32 Version2; + UINT32 Version3; + UINT32 ModuleInfoOffset; + UINT32 EntryPoint; + UINT32 ImageBase; + UINT32 RelocTableOffset; + UINT32 ImageSize; + UINT16 CheckSum; + UINT8 ImageType; + UINT8 Reserved2; +} CIMFILEHEADER; + +#ifndef BIT0 + #define BIT0 (1 << 0) +#endif +#ifndef BIT1 + #define BIT1 (1 << 1) +#endif +#ifndef BIT2 + #define BIT2 (1 << 2) +#endif +#ifndef BIT3 + #define BIT3 (1 << 3) +#endif +#ifndef BIT4 + #define BIT4 (1 << 4) +#endif +#ifndef BIT5 + #define BIT5 (1 << 5) +#endif +#ifndef BIT6 + #define BIT6 (1 << 6) +#endif +#ifndef BIT7 + #define BIT7 (1 << 7) +#endif +#ifndef BIT8 + #define BIT8 (1 << 8) +#endif +#ifndef BIT9 + #define BIT9 (1 << 9) +#endif +#ifndef BIT10 + #define BIT10 (1 << 10) +#endif +#ifndef BIT11 + #define BIT11 (1 << 11) +#endif +#ifndef BIT12 + #define BIT12 (1 << 12) +#endif +#ifndef BIT13 + #define BIT13 (1 << 13) +#endif +#ifndef BIT14 + #define BIT14 (1 << 14) +#endif +#ifndef BIT15 + #define BIT15 (1 << 15) +#endif +#ifndef BIT16 + #define BIT16 (1 << 16) +#endif +#ifndef BIT17 + #define BIT17 (1 << 17) +#endif +#ifndef BIT18 + #define BIT18 (1 << 18) +#endif +#ifndef BIT19 + #define BIT19 (1 << 19) +#endif +#ifndef BIT20 + #define BIT20 (1 << 20) +#endif +#ifndef BIT21 + #define BIT21 (1 << 21) +#endif +#ifndef BIT22 + #define BIT22 (1 << 22) +#endif +#ifndef BIT23 + #define BIT23 (1 << 23) +#endif +#ifndef BIT24 + #define BIT24 (1 << 24) +#endif +#ifndef BIT25 + #define BIT25 (1 << 25) +#endif +#ifndef BIT26 + #define BIT26 (1 << 26) +#endif +#ifndef BIT27 + #define BIT27 (1 << 27) +#endif +#ifndef BIT28 + #define BIT28 (1 << 28) +#endif +#ifndef BIT29 + #define BIT29 (1 << 29) +#endif +#ifndef BIT30 + #define BIT30 (1 << 30) +#endif +#ifndef BIT31 + #define BIT31 (1 << 31) +#endif + +#pragma pack (pop) + +typedef enum +{ + AccWidthUint8 = 0, + AccWidthUint16, + AccWidthUint32, +} ACC_WIDTH; + +#define S3_SAVE 0x80 + +#endif Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h Sun Jan 2 00:30:37 2011 (r6236) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h Sun Jan 2 00:36:03 2011 (r6237) @@ -1,153 +1,153 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#ifndef _AMD_SBPLATFORM_H_ -#define _AMD_SBPLATFORM_H_ - -#include <southbridge/amd/cimx_wrapper/sb800/cbtypes.h> -typedef UINT64 PLACEHOLDER; -#include <southbridge/amd/cimx_wrapper/sb800/Amdlib.h> -#include <southbridge/amd/cimx_wrapper/sb800/Amd.h> -#include <vendorcode/amd/cimx/lib/amdlib32.h> //TODO merge with agesa wrapper -#include <vendorcode/amd/cimx/sb800/SB800.h> -#include <vendorcode/amd/cimx/sb800/SBTYPE.h> -#include <vendorcode/amd/cimx/sb800/ACPILIB.h> -#include <vendorcode/amd/cimx/sb800/SBDEF.h> -#include <vendorcode/amd/cimx/sb800/AMDSBLIB.h> -#include <vendorcode/amd/cimx/sb800/SBSUBFUN.h> -#include <vendorcode/amd/cimx/sb800/OEM.h> - -#ifdef NULL - #undef NULL -#endif -#define NULL 0 - -#ifndef SBOEM_ACPI_RESTORE_SWSMI - #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3 - #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4 -#endif - -#ifndef _AMD_NB_CIM_X_PROTOCOL_H_ - -/// Extended PCI Address -typedef struct _EXT_PCI_ADDR { - UINT32 Reg :16; ///< / PCI Register - UINT32 Func:3; ///< / PCI Function - UINT32 Dev :5; ///< / PCI Device - UINT32 Bus :8; ///< / PCI Address -} EXT_PCI_ADDR; - -/// PCI Address -typedef union _PCI_ADDR { - UINT32 ADDR; ///< / 32 bit Address - EXT_PCI_ADDR Addr; ///< / Extended PCI Address -} PCI_ADDR; -#endif - -#define FIXUP_PTR(ptr) ptr - -//------------------------------------------------------------------------------------------------------------------------// -/** - * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over - * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable - * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal - * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable - * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00) - * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable - * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL) - * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable - * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable - * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable - * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable - * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable - * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable - * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable - * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable - * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable - * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable - * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11) - * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00) - * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz - * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable - * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable - * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable - * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable - * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable - * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable - * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable - * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable - * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable - * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable - * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable - * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable - * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable - */ -#define SB_CIMx_PARAMETER 0x02 - -// Generic -#define cimSpreadSpectrumDefault TRUE -#define cimSpreadSpectrumTypeDefault 0x00 // Normal -#define cimHpetTimerDefault TRUE -#define cimHpetMsiDisDefault FALSE // Enable -#define cimIrConfigDefault 0x00 // Disable -#define cimSpiFastReadEnableDefault 0x00 // Disable -#define cimSpiFastReadSpeedDefault 0x00 // NULL -// GPP/AB Controller -#define cimNbSbGen2Default TRUE -#define cimAlinkPhyPllPowerDownDefault TRUE -#define cimResetCpuOnSyncFloodDefault TRUE -#define cimGppGen2Default FALSE -#define cimGppMemWrImproveDefault TRUE -#define cimGppPortAspmDefault FALSE -#define cimGppLaneReversalDefault FALSE -#define cimGppPhyPllPowerDownDefault TRUE -// USB Controller -#define cimUsbPhyPowerDownDefault FALSE -// GEC Controller -#define cimSBGecDebugBusDefault FALSE -#define cimSBGecPwrDefault 0x03 -// Sata Controller -#define cimSataSetMaxGen2Default 0x00 -#define cimSATARefClkSelDefault 0x10 -#define cimSATARefDivSelDefault 0x80 -#define cimSataAggrLinkPmCapDefault TRUE -#define cimSataPortMultCapDefault TRUE -#define cimSataPscCapDefault 0x00 // Enable -#define cimSataSscCapDefault 0x00 // Enable -#define cimSataFisBasedSwitchingDefault FALSE -#define cimSataCccSupportDefault FALSE -#define cimSataClkAutoOffDefault FALSE -#define cimNativepciesupportDefault FALSE -// Fusion Related -#define cimAcDcMsgDefault FALSE -#define cimTimerTickTrackDefault FALSE -#define cimClockInterruptTagDefault FALSE -#define cimOhciTrafficHandingDefault FALSE -#define cimEhciTrafficHandingDefault FALSE -#define cimFusionMsgCMultiCoreDefault FALSE -#define cimFusionMsgCStageDefault FALSE - -#endif // _AMD_SBPLATFORM_H_ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#ifndef _AMD_SBPLATFORM_H_ +#define _AMD_SBPLATFORM_H_ + +#include <southbridge/amd/cimx_wrapper/sb800/cbtypes.h> +typedef UINT64 PLACEHOLDER; +#include <southbridge/amd/cimx_wrapper/sb800/Amdlib.h> +#include <southbridge/amd/cimx_wrapper/sb800/Amd.h> +#include <vendorcode/amd/cimx/lib/amdlib32.h> //TODO merge with agesa wrapper +#include <vendorcode/amd/cimx/sb800/SB800.h> +#include <vendorcode/amd/cimx/sb800/SBTYPE.h> +#include <vendorcode/amd/cimx/sb800/ACPILIB.h> +#include <vendorcode/amd/cimx/sb800/SBDEF.h> +#include <vendorcode/amd/cimx/sb800/AMDSBLIB.h> +#include <vendorcode/amd/cimx/sb800/SBSUBFUN.h> +#include <vendorcode/amd/cimx/sb800/OEM.h> + +#ifdef NULL + #undef NULL +#endif +#define NULL 0 + +#ifndef SBOEM_ACPI_RESTORE_SWSMI + #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3 + #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4 +#endif + +#ifndef _AMD_NB_CIM_X_PROTOCOL_H_ + +/// Extended PCI Address +typedef struct _EXT_PCI_ADDR { + UINT32 Reg :16; ///< / PCI Register + UINT32 Func:3; ///< / PCI Function + UINT32 Dev :5; ///< / PCI Device + UINT32 Bus :8; ///< / PCI Address +} EXT_PCI_ADDR; + +/// PCI Address +typedef union _PCI_ADDR { + UINT32 ADDR; ///< / 32 bit Address + EXT_PCI_ADDR Addr; ///< / Extended PCI Address +} PCI_ADDR; +#endif + +#define FIXUP_PTR(ptr) ptr + +//------------------------------------------------------------------------------------------------------------------------// +/** + * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over + * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable + * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal + * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable + * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) + * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00) + * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable + * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL) + * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable + * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable + * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable + * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable + * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable + * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable + * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable + * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable + * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable + * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable + * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11) + * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00) + * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz + * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable + * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable + * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) + * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) + * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable + * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable + * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable + * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable + * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable + * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable + * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable + * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable + * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable + * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable + * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable + */ +#define SB_CIMx_PARAMETER 0x02 + +// Generic +#define cimSpreadSpectrumDefault TRUE +#define cimSpreadSpectrumTypeDefault 0x00 // Normal +#define cimHpetTimerDefault TRUE +#define cimHpetMsiDisDefault FALSE // Enable +#define cimIrConfigDefault 0x00 // Disable +#define cimSpiFastReadEnableDefault 0x00 // Disable +#define cimSpiFastReadSpeedDefault 0x00 // NULL +// GPP/AB Controller +#define cimNbSbGen2Default TRUE +#define cimAlinkPhyPllPowerDownDefault TRUE +#define cimResetCpuOnSyncFloodDefault TRUE +#define cimGppGen2Default FALSE +#define cimGppMemWrImproveDefault TRUE +#define cimGppPortAspmDefault FALSE +#define cimGppLaneReversalDefault FALSE +#define cimGppPhyPllPowerDownDefault TRUE +// USB Controller +#define cimUsbPhyPowerDownDefault FALSE +// GEC Controller +#define cimSBGecDebugBusDefault FALSE +#define cimSBGecPwrDefault 0x03 +// Sata Controller +#define cimSataSetMaxGen2Default 0x00 +#define cimSATARefClkSelDefault 0x10 +#define cimSATARefDivSelDefault 0x80 +#define cimSataAggrLinkPmCapDefault TRUE +#define cimSataPortMultCapDefault TRUE +#define cimSataPscCapDefault 0x00 // Enable +#define cimSataSscCapDefault 0x00 // Enable +#define cimSataFisBasedSwitchingDefault FALSE +#define cimSataCccSupportDefault FALSE +#define cimSataClkAutoOffDefault FALSE +#define cimNativepciesupportDefault FALSE +// Fusion Related +#define cimAcDcMsgDefault FALSE +#define cimTimerTickTrackDefault FALSE +#define cimClockInterruptTagDefault FALSE +#define cimOhciTrafficHandingDefault FALSE +#define cimEhciTrafficHandingDefault FALSE +#define cimFusionMsgCMultiCoreDefault FALSE +#define cimFusionMsgCStageDefault FALSE + +#endif // _AMD_SBPLATFORM_H_

1 0

[commit] r6236 - in trunk/src: mainboard/amd/bimini_fam10 southbridge/amd/cimx_wrapper/sb800
by repository service 02 Jan '11

02 Jan '11

Author: uwe Date: Sun Jan 2 00:30:37 2011 New Revision: 6236 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6236 Log: AMD SB800: Drop component prefix from filenames. We did the same with other chipsets in r6150. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c - copied, changed from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.c trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h - copied, changed from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.h trunk/src/southbridge/amd/cimx_wrapper/sb800/early.c - copied, changed from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_early.c trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c - copied, changed from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_late.c trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.c - copied, changed from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.c trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.h - copied, changed from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.h trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.c - copied, changed from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.c trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.h - copied unchanged from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.h Deleted: trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.c trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.h trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_early.c trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_late.c trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.c trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.h trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.c trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.h Modified: trunk/src/mainboard/amd/bimini_fam10/romstage.c trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h trunk/src/southbridge/amd/cimx_wrapper/sb800/Kconfig trunk/src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h trunk/src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c trunk/src/southbridge/amd/cimx_wrapper/sb800/chip_name.c Modified: trunk/src/mainboard/amd/bimini_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/romstage.c Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/mainboard/amd/bimini_fam10/romstage.c Sun Jan 2 00:30:37 2011 (r6236) @@ -47,7 +47,7 @@ #include "southbridge/amd/rs780/early_setup.c" #include <SbEarly.h> #include <SBPLATFORM.h> /* SB OEM constants */ -#include <sb800_smbus.h> +#include <southbridge/amd/cimx_wrapper/sb800/smbus.h> #include "northbridge/amd/amdfam10/debug.c" static void activate_spd_rom(const struct mem_controller *ctrl) @@ -193,7 +193,7 @@ /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); - #endif +#endif rs780_htinit(); Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h Sun Jan 2 00:30:37 2011 (r6236) @@ -35,20 +35,15 @@ * */ - #ifndef _AMD_H_ #define _AMD_H_ -// -// // AGESA Types and Definitions -// -// + #ifndef NULL #define NULL 0 #endif - #define LAST_ENTRY 0xFFFFFFFF #define IOCF8 0xCF8 #define IOCFC 0xCFC @@ -58,7 +53,6 @@ typedef UINTN AGESA_STATUS; - #define AGESA_SUCCESS ((AGESA_STATUS) 0x0) #define AGESA_ALERT ((AGESA_STATUS) 0x40000000) #define AGESA_WARNING ((AGESA_STATUS) 0x40000001) @@ -131,7 +125,6 @@ IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link } AMD_MODULE_HEADER; - #define FUNC_0 0 // bit-placed for PCI address creation #define FUNC_1 1 #define FUNC_2 2 @@ -378,4 +371,5 @@ #ifndef BIT63 #define BIT63 0x8000000000000000ull #endif + #endif Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amdlib.h Sun Jan 2 00:30:37 2011 (r6236) @@ -36,7 +36,6 @@ #define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) #define va_end(ap) ( ap = (va_list)0 ) - #pragma pack (push, 1) #define IMAGE_ALIGN 32*1024 Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Kconfig ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/Kconfig Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Kconfig Sun Jan 2 00:30:37 2011 (r6236) @@ -17,10 +17,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## - if SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 + config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx_wrapper/sb800/bootblock.c" -endif #SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 + string + default "southbridge/amd/cimx_wrapper/sb800/bootblock.c" + +endif Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc Sun Jan 2 00:30:37 2011 (r6236) @@ -23,13 +23,13 @@ # SB800 Platform Files -romstage-y += sb800_cfg.c -romstage-y += sb800_early.c -romstage-y += sb800_smbus.c +romstage-y += cfg.c +romstage-y += early.c +romstage-y += smbus.c -ramstage-y += sb800_cfg.c -ramstage-y += sb800_late.c +ramstage-y += cfg.c +ramstage-y += late.c -driver-y += sb800_smbus.c -driver-y += sb800_lpc.c +driver-y += smbus.c +driver-y += lpc.c Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h Sun Jan 2 00:30:37 2011 (r6236) @@ -24,18 +24,18 @@ #ifndef _AMD_SBPLATFORM_H_ #define _AMD_SBPLATFORM_H_ -#include "cbtypes.h" +#include <southbridge/amd/cimx_wrapper/sb800/cbtypes.h> typedef UINT64 PLACEHOLDER; -#include "Amdlib.h" -#include "Amd.h" -#include "amdlib32.h"//TODO merge with agesa wrapper -#include "SB800.h" -#include "SBTYPE.h" -#include "ACPILIB.h" -#include "SBDEF.h" -#include "AMDSBLIB.h" -#include "SBSUBFUN.h" -#include "OEM.h" +#include <southbridge/amd/cimx_wrapper/sb800/Amdlib.h> +#include <southbridge/amd/cimx_wrapper/sb800/Amd.h> +#include <vendorcode/amd/cimx/lib/amdlib32.h> //TODO merge with agesa wrapper +#include <vendorcode/amd/cimx/sb800/SB800.h> +#include <vendorcode/amd/cimx/sb800/SBTYPE.h> +#include <vendorcode/amd/cimx/sb800/ACPILIB.h> +#include <vendorcode/amd/cimx/sb800/SBDEF.h> +#include <vendorcode/amd/cimx/sb800/AMDSBLIB.h> +#include <vendorcode/amd/cimx/sb800/SBSUBFUN.h> +#include <vendorcode/amd/cimx/sb800/OEM.h> #ifdef NULL #undef NULL @@ -66,9 +66,6 @@ #define FIXUP_PTR(ptr) ptr - - - //------------------------------------------------------------------------------------------------------------------------// /** * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h Sun Jan 2 00:30:37 2011 (r6236) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #ifndef _CIMX_SB_EARLY_H_ #define _CIMX_SB_EARLY_H_ Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c Sun Jan 2 00:30:37 2011 (r6236) @@ -17,11 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include <arch/io.h> #include <arch/romcc_io.h> - #if CONFIG_SERIAL_POST == 1 /* Data */ @@ -53,7 +51,6 @@ #endif // CONFIG_SERIAL_POST == 1 - static void sb800_enable_rom(void) { u32 word; @@ -90,7 +87,6 @@ pci_io_write_config16(dev, 0x6c, word); } - static void uart_init(void) { #if CONFIG_SERIAL_POST == 1 @@ -106,7 +102,6 @@ #endif // CONFIG_SERIAL_POST == 1 } - static void bootblock_southbridge_init(void) { /* Setup the rom access for 2M */ Copied and modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c (from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.c) ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.c Sat Jan 1 18:52:34 2011 (r6230, copy source) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c Sun Jan 2 00:30:37 2011 (r6236) @@ -17,10 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#include "SBPLATFORM.h" -#include "sb800_cfg.h" - +#include <southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h> +#include <southbridge/amd/cimx_wrapper/sb800/cfg.h> /** * @brief South Bridge CIMx configuration @@ -124,4 +122,3 @@ //sb_config-> #endif //!__PRE_RAM__ } - Copied and modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h (from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.h) ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_cfg.h Sat Jan 1 18:52:34 2011 (r6230, copy source) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h Sun Jan 2 00:30:37 2011 (r6236) @@ -17,13 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #ifndef _SB800_CFG_H_ #define _SB800_CFG_H_ #include <stdint.h> - /** * @def BIOS_SIZE_1M * @def BIOS_SIZE_2M @@ -150,7 +148,6 @@ */ #define SATA_PORT_MULT_CAP_RESERVED 1 - /** * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. @@ -218,10 +215,8 @@ #define GPP_CFGMODE GPP_CFGMODE_X1111 #endif - /** * @brief South Bridge CIMx configuration - * */ void sb800_cimx_config(AMDSBCFG *sb_cfg); @@ -233,7 +228,6 @@ * @param[in] func Southbridge CIMx Function ID. * @param[in] data Southbridge Input Data. * @param[in] sb_cfg Southbridge configuration structure pointer. - * */ u32 sb800_callout_entry(u32 func, u32 data, void* sb_cfg); Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/chip_name.c ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/chip_name.c Sat Jan 1 23:05:57 2011 (r6235) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/chip_name.c Sun Jan 2 00:30:37 2011 (r6236) @@ -21,5 +21,5 @@ #include "chip.h" struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = { - CHIP_NAME("AMD South Bridge SB800") + CHIP_NAME("AMD SB800 Southbridge") }; Copied and modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/early.c (from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_early.c) ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_early.c Sat Jan 1 18:52:34 2011 (r6230, copy source) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/early.c Sun Jan 2 00:30:37 2011 (r6236) @@ -17,16 +17,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - //#include <config.h> #include <stdint.h> #include <device/pci_ids.h> -#include <arch/io.h> /* inl, outl */ -#include <arch/romcc_io.h> /* device_t */ -#include "SBPLATFORM.h" -#include "SbEarly.h" -#include "sb800_cfg.h" /*sb800_cimx_config*/ - +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h> +#include <southbridge/amd/cimx_wrapper/sb800/SbEarly.h> +#include <southbridge/amd/cimx_wrapper/sb800/cfg.h> /** * @brief Get SouthBridge device number @@ -45,7 +43,6 @@ return (dev >> 15) & 0x1f; } - /** * @brief South Bridge CIMx romstage entry, * wrapper of sbPowerOnInit entry point. Copied and modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c (from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_late.c) ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_late.c Sat Jan 1 18:52:34 2011 (r6230, copy source) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c Sun Jan 2 00:30:37 2011 (r6236) @@ -17,17 +17,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#include <device/device.h> /* device_t */ -#include <device/pci.h> /* device_operations */ +#include <device/device.h> +#include <device/pci.h> #include <device/pci_ids.h> -#include <device/smbus.h> /* smbus_bus_operations */ -#include <console/console.h> /* printk */ -#include "sb800_lpc.h" /* lpc_read_resources */ -#include "SBPLATFORM.h" /* Platfrom Specific Definitions */ -#include "sb800_cfg.h" /* sb800 Cimx configuration */ -#include "chip.h" /* struct southbridge_amd_cimx_wrapper_sb800_config */ - +#include <device/smbus.h> +#include <console/console.h> +#include <southbridge/amd/cimx_wrapper/sb800/lpc.h> +#include <southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h> +#include <southbridge/amd/cimx_wrapper/sb800/cfg.h> +#include "chip.h" /*implement in mainboard.c*/ //void set_pcie_assert(void); @@ -35,14 +33,13 @@ void set_pcie_reset(void); void set_pcie_dereset(void); - #ifndef _RAMSTAGE_ #define _RAMSTAGE_ #endif + static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config static AMDSBCFG *sb_config = &sb_late_cfg; - /** * @brief Entry point of Southbridge CIMx callout * @@ -78,14 +75,12 @@ return ret; } - static struct pci_operations lops_pci = { .set_subsystem = 0, }; static void lpc_enable_resources(device_t dev) { - pci_dev_enable_resources(dev); //lpc_enable_childrens_resources(dev); } @@ -111,7 +106,6 @@ .device = PCI_DEVICE_ID_ATI_SB800_LPC, }; - static void sata_enable_resources(struct device *dev) { sataInitAfterPciEnum(sb_config); @@ -141,7 +135,6 @@ .device = PCI_DEVICE_ID_ATI_SB800_SATA, //SATA IDE Mode 4390 }; - #if CONFIG_USBDEBUG static void usb_set_resources(struct device *dev) { @@ -225,7 +218,6 @@ .device = PCI_DEVICE_ID_ATI_SB800_HDA, }; - static void gec_init(struct device *dev) { gecInitAfterPciEnum(sb_config); @@ -248,7 +240,6 @@ .device = PCI_DEVICE_ID_ATI_SB800_GEC, }; - static void pcie_init(device_t dev) { sbPcieGppLateInit(sb_config); @@ -270,7 +261,6 @@ .device = PCI_DEVICE_ID_ATI_SB800_PCI, }; - struct device_operations bridge_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -310,7 +300,6 @@ .device = PCI_DEVICE_ID_ATI_SB800_PCIED, }; - /** * @brief SB Cimx entry point sbBeforePciInit wrapper */ Copied and modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.c (from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.c) ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.c Sat Jan 1 18:52:34 2011 (r6230, copy source) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.c Sun Jan 2 00:30:37 2011 (r6236) @@ -18,8 +18,7 @@ */ #include <device/pci.h> -#include "sb800_lpc.h" - +#include <southbridge/amd/cimx_wrapper/sb800/lpc.h> void lpc_read_resources(device_t dev) { @@ -60,7 +59,6 @@ /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ res = find_resource(dev, SPIROM_BASE_ADDRESS); pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1); - } /** Copied and modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.h (from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.h) ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_lpc.h Sat Jan 1 18:52:34 2011 (r6230, copy source) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/lpc.h Sun Jan 2 00:30:37 2011 (r6236) @@ -20,7 +20,6 @@ #ifndef _SB800_LPC_H_ #define _SB800_LPC_H_ - #define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ void lpc_read_resources(device_t dev); Copied and modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.c (from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.c) ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.c Sat Jan 1 18:52:34 2011 (r6230, copy source) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.c Sun Jan 2 00:30:37 2011 (r6236) @@ -17,9 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include <arch/io.h> -#include "sb800_smbus.h" +#include <southbridge/amd/cimx_wrapper/sb800/smbus.h> static inline void smbus_delay(void) { @@ -248,4 +247,3 @@ outl(tmp, AB_DATA); outl(0, AB_INDX); } - Copied: trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.h (from r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.h) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/smbus.h Sun Jan 2 00:30:37 2011 (r6236, copy of r6230, trunk/src/southbridge/amd/cimx_wrapper/sb800/sb800_smbus.h) @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SB800_SMBUS_H_ +#define _SB800_SMBUS_H_ + +//#include <stdint.h> + +#define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS + +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTRL 0x2 +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 + +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc + +/*//SB00.H +#define AX_INDXC 0 +#define AX_INDXP 2 +#define AXCFG 4 +#define ABCFG 6 +#define RC_INDXC 1 +#define RC_INDXP 3 +*/ + +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4) + +/* Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100*1000*10) + +#define abcfg_reg(reg, mask, val) \ + alink_ab_indx((ABCFG), (reg), (mask), (val)) +#define axcfg_reg(reg, mask, val) \ + alink_ab_indx((AXCFG), (reg), (mask), (val)) +#define axindxc_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXC), (reg), (mask), (val)) +#define axindxp_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXP), (reg), (mask), (val)) +#define rcindxc_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) +#define rcindxp_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) + +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); +void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); + +#endif

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coreboot January 2011