[patch] AMD MCT DDR3 for register DIMMs

[Bao, Zheng]

The code is tested on my board with register DIMMs. More tests need to
be
done. Please send the testing report.

Note: The pDCTstat->PresetmaxFreq in mctGet_MaxLoadFreq() should be set
to a higher limit, otherwise the frequnce will be set as 400MHz.

Signed-off-by: Zheng Bao

Index: src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
===================================================================
--- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c	(revision 6244)
+++ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c	(working copy)
@@ -86,7 +86,7 @@
    procConifg(pMCTData,pDCTData, dimm, pass);
    /* 5. Begin write levelization training:
     *  Program F2x[1, 0]9C_x08[WrtLevelTrEn]=1. */
-	if (pDCTData->LogicalCPUID & AMD_DR_Cx)
+	if (pDCTData->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx))
    	set_DCT_ADDR_Bits(pDCTData, pDCTData->DctTrain,
pDCTData->NodeId, FUN_DCT,
    			DRAM_ADD_DCT_PHY_CONTROL_REG, WrtLvTrEn,
WrtLvTrEn, 1);
    else
@@ -656,9 +656,9 @@
    programODT(pMCTData, pDCTData, dimm);

/* Program F2x[1,0]9C_x08[WrLvOdtEn]=1 */
-	if (pDCTData->LogicalCPUID & AMD_DR_Cx)
+	if (pDCTData->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx))
    	set_DCT_ADDR_Bits(pDCTData, pDCTData->DctTrain,
pDCTData->NodeId, FUN_DCT,
-				DRAM_ADD_DCT_PHY_CONTROL_REG, WrLvOdtEn,
WrLvOdtEn,(u32) 1);
+				DRAM_ADD_DCT_PHY_CONTROL_REG, WrLvOdtEn,
WrLvOdtEn, (u32)1);
    else
    {
    	/* Program WrLvOdtEn=1 through set bit 12 of D3CSODT reg
offset 0 for Rev.B*/
@@ -722,7 +722,36 @@

pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;
    		ByteLane++;
    	}
+	} else if (pDCTData->Status[DCT_STATUS_REGISTERED]) {
/* For Pass 2 */
+		/* From BKDG, Write Leveling Seed Value. */
+		/* TODO: The unbuffered DIMMs are unstable on the code
below. So temporarily it is
+		 * only for registered DIMMs. */
+		u32 RegisterDelay, SeedTotal;
+		u8 MemClkFreq;
+		u16 freq_tab[] = {400, 533, 667, 800};
+		while(ByteLane < MAX_BYTE_LANES)
+		{
+			MemClkFreq = get_Bits(pDCTData,
pDCTData->CurrDct, pDCTData->NodeId,
+					      FUN_DCT, DRAM_CONFIG_HIGH,
0, 2);
+			if (pDCTData->Status[DCT_STATUS_REGISTERED])
+				RegisterDelay = 0x20; /* TODO: ((RCW2 &
BIT0) == 0) ? 0x20 : 0x30; */
+			else
+				RegisterDelay = 0;
+			SeedTotal =
(pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1F) |
+
pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] << 5;
+			/* SeedTotalPreScaling = (the total delay value
in F2x[1, 0]9C_x[4A:30] from pass 1 of write levelization
+			   training) - RegisterDelay. */
+			/* MemClkFreq: 3: 400Mhz; 4: 533Mhz; 5: 667Mhz;
6: 800Mhz */
+			SeedTotal = (u16) (RegisterDelay + ((((u32)
SeedTotal - RegisterDelay) *
+
freq_tab[MemClkFreq-3]) / 400));
+			Seed_Gross = (SeedTotal & 0x20) != 0 ? 1 : 2;
+			Seed_Fine = SeedTotal & 0x1F;
+
pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross;
+
pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;
+			ByteLane ++;
+		}
    }
+
    setWLByteDelay(pDCTData, ByteLane, dimm, 0);
 }

Index: src/northbridge/amd/amdmct/mct_ddr3/mctwl.c
===================================================================
--- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c	(revision 6246)
+++ src/northbridge/amd/amdmct/mct_ddr3/mctwl.c	(working copy)
@@ -342,7 +342,21 @@
    mct_Wait(250);

if (pDCTstat->Status & (1 << SB_Registered)) {
-		/* TODO: Assuming the dct==0. The agesa here is
confusing. */
+		u8 DCT0Present, DCT1Present;
+
+		DCT0Present = pDCTstat->DIMMValidDCT[0];
+		if (pDCTstat->GangedMode)
+			DCT1Present = 0;
+		else
+			DCT1Present = pDCTstat->DIMMValidDCT[1];
+
+		if (!DCT1Present)
+			pDCTstat->CSPresent =
pDCTstat->CSPresent_DCT[0];
+		else if (pDCTstat->GangedMode) {
+			pDCTstat->CSPresent = 0;
+		} else
+			pDCTstat->CSPresent =
pDCTstat->CSPresent_DCT[1];
+
    	FreqChgCtrlWrd(pMCTstat, pDCTstat);
    }
 }

[Zheng Bao]

ping.
Any comment before it is drowned?

Zheng

Date: Mon, 10 Jan 2011 13:29:49 +0800
From: [e-mail]
To: [e-mail]
Subject: [coreboot] [patch] AMD MCT DDR3 for register DIMMs

The code is tested on my board with register DIMMs. More tests need to
be
done. Please send the testing report.

Note: The pDCTstat->PresetmaxFreq in mctGet_MaxLoadFreq() should be set
to a higher limit, otherwise the frequnce will be set as 400MHz.

Signed-off-by: Zheng Bao

Index: src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
===================================================================
--- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c	(revision 6244)
+++ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c	(working copy)
@@ -86,7 +86,7 @@
    procConifg(pMCTData,pDCTData, dimm, pass);
    /* 5. Begin write levelization training:
     *  Program F2x[1, 0]9C_x08[WrtLevelTrEn]=1. */
-	if (pDCTData->LogicalCPUID & AMD_DR_Cx)
+	if (pDCTData->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx))
    	set_DCT_ADDR_Bits(pDCTData, pDCTData->DctTrain,
pDCTData->NodeId, FUN_DCT,
    			DRAM_ADD_DCT_PHY_CONTROL_REG, WrtLvTrEn,
WrtLvTrEn, 1);
    else
@@ -656,9 +656,9 @@
    programODT(pMCTData, pDCTData, dimm);

/* Program F2x[1,0]9C_x08[WrLvOdtEn]=1 */
-	if (pDCTData->LogicalCPUID & AMD_DR_Cx)
+	if (pDCTData->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx))
    	set_DCT_ADDR_Bits(pDCTData, pDCTData->DctTrain,
pDCTData->NodeId, FUN_DCT,
-				DRAM_ADD_DCT_PHY_CONTROL_REG, WrLvOdtEn,
WrLvOdtEn,(u32) 1);
+				DRAM_ADD_DCT_PHY_CONTROL_REG, WrLvOdtEn,
WrLvOdtEn, (u32)1);
    else
    {
    	/* Program WrLvOdtEn=1 through set bit 12 of D3CSODT reg
offset 0 for Rev.B*/
@@ -722,7 +722,36 @@

pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;
    		ByteLane++;
    	}
+	} else if (pDCTData->Status[DCT_STATUS_REGISTERED]) {
/* For Pass 2 */
+		/* From BKDG, Write Leveling Seed Value. */
+		/* TODO: The unbuffered DIMMs are unstable on the code
below. So temporarily it is
+		 * only for registered DIMMs. */
+		u32 RegisterDelay, SeedTotal;
+		u8 MemClkFreq;
+		u16 freq_tab[] = {400, 533, 667, 800};
+		while(ByteLane < MAX_BYTE_LANES)
+		{
+			MemClkFreq = get_Bits(pDCTData,
pDCTData->CurrDct, pDCTData->NodeId,
+					      FUN_DCT, DRAM_CONFIG_HIGH,
0, 2);
+			if (pDCTData->Status[DCT_STATUS_REGISTERED])
+				RegisterDelay = 0x20; /* TODO: ((RCW2 &
BIT0) == 0) ? 0x20 : 0x30; */
+			else
+				RegisterDelay = 0;
+			SeedTotal =
(pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1F) |
+
pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] << 5;
+			/* SeedTotalPreScaling = (the total delay value
in F2x[1, 0]9C_x[4A:30] from pass 1 of write levelization
+			   training) - RegisterDelay. */
+			/* MemClkFreq: 3: 400Mhz; 4: 533Mhz; 5: 667Mhz;
6: 800Mhz */
+			SeedTotal = (u16) (RegisterDelay + ((((u32)
SeedTotal - RegisterDelay) *
+
freq_tab[MemClkFreq-3]) / 400));
+			Seed_Gross = (SeedTotal & 0x20) != 0 ? 1 : 2;
+			Seed_Fine = SeedTotal & 0x1F;
+
pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross;
+
pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;
+			ByteLane ++;
+		}
    }
+
    setWLByteDelay(pDCTData, ByteLane, dimm, 0);
 }

Index: src/northbridge/amd/amdmct/mct_ddr3/mctwl.c
===================================================================
--- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c	(revision 6246)
+++ src/northbridge/amd/amdmct/mct_ddr3/mctwl.c	(working copy)
@@ -342,7 +342,21 @@
    mct_Wait(250);

if (pDCTstat->Status & (1 << SB_Registered)) {
-		/* TODO: Assuming the dct==0. The agesa here is
confusing. */
+		u8 DCT0Present, DCT1Present;
+
+		DCT0Present = pDCTstat->DIMMValidDCT[0];
+		if (pDCTstat->GangedMode)
+			DCT1Present = 0;
+		else
+			DCT1Present = pDCTstat->DIMMValidDCT[1];
+
+		if (!DCT1Present)
+			pDCTstat->CSPresent =
pDCTstat->CSPresent_DCT[0];
+		else if (pDCTstat->GangedMode) {
+			pDCTstat->CSPresent = 0;
+		} else
+			pDCTstat->CSPresent =
pDCTstat->CSPresent_DCT[1];
+
    	FreqChgCtrlWrd(pMCTstat, pDCTstat);
    }
 }

-- coreboot mailing list: [e-mail] http://www.coreboot.org/mailman/listinfo/coreboot

[Scott Duplichan]

_____

From: coreboot-bounces+scott=[e-mail] [mailto:coreboot-bounces+scott=[e-mail]] On Behalf Of Zheng Bao
Sent: Friday, January 14, 2011 07:51 AM
To: [e-mail]
Subject: Re: [coreboot] [patch] AMD MCT DDR3 for register DIMMs

]ping.
]Any comment before it is drowned?

]Zheng

Hello Bao Zheng,

I do not have a setup for testing with registered DIMMs.  But I will ack the patch based on that fact that you have the latest agesa
code and a way to test.

Acked-by: Scott Duplichan

Thanks,
Scott

Date: Mon, 10 Jan 2011 13:29:49 +0800
From: [e-mail]
To: [e-mail]
Subject: [coreboot] [patch] AMD MCT DDR3 for register DIMMs

The code is tested on my board with register DIMMs. More tests need to

be

done. Please send the testing report.

Note: The pDCTstat->PresetmaxFreq in mctGet_MaxLoadFreq() should be set

to a higher limit, otherwise the frequnce will be set as 400MHz.

Signed-off-by: Zheng Bao

Index: src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c

===================================================================

--- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c  (revision 6244)

+++ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c  (working copy)

@@ -86,7 +86,7 @@

procConifg(pMCTData,pDCTData, dimm, pass);

/* 5. Begin write levelization training:

*  Program F2x[1, 0]9C_x08[WrtLevelTrEn]=1. */

-      if (pDCTData->LogicalCPUID & AMD_DR_Cx)

+      if (pDCTData->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx))

set_DCT_ADDR_Bits(pDCTData, pDCTData->DctTrain,

pDCTData->NodeId, FUN_DCT,

DRAM_ADD_DCT_PHY_CONTROL_REG, WrtLvTrEn,

WrtLvTrEn, 1);

else

@@ -656,9 +656,9 @@

programODT(pMCTData, pDCTData, dimm);

/* Program F2x[1,0]9C_x08[WrLvOdtEn]=1 */

-      if (pDCTData->LogicalCPUID & AMD_DR_Cx)

+      if (pDCTData->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx))

set_DCT_ADDR_Bits(pDCTData, pDCTData->DctTrain,

pDCTData->NodeId, FUN_DCT,

-                            DRAM_ADD_DCT_PHY_CONTROL_REG, WrLvOdtEn,

WrLvOdtEn,(u32) 1);

+                            DRAM_ADD_DCT_PHY_CONTROL_REG, WrLvOdtEn,

WrLvOdtEn, (u32)1);

else

{

/* Program WrLvOdtEn=1 through set bit 12 of D3CSODT reg

offset 0 for Rev.B*/

@@ -722,7 +722,36 @@

pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;

ByteLane++;

}

+      } else if (pDCTData->Status[DCT_STATUS_REGISTERED]) {

/* For Pass 2 */

+              /* From BKDG, Write Leveling Seed Value. */

+              /* TODO: The unbuffered DIMMs are unstable on the code

below. So temporarily it is

+               * only for registered DIMMs. */

+              u32 RegisterDelay, SeedTotal;

+              u8 MemClkFreq;

+              u16 freq_tab[] = {400, 533, 667, 800};

+              while(ByteLane < MAX_BYTE_LANES)

+              {

+                     MemClkFreq = get_Bits(pDCTData,

pDCTData->CurrDct, pDCTData->NodeId,

+                                          FUN_DCT, DRAM_CONFIG_HIGH,

0, 2);

+                     if (pDCTData->Status[DCT_STATUS_REGISTERED])

+                            RegisterDelay = 0x20; /* TODO: ((RCW2 &

BIT0) == 0) ? 0x20 : 0x30; */

+                     else

+                            RegisterDelay = 0;

+                     SeedTotal =

(pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1F) |

+

pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] << 5;

+                     /* SeedTotalPreScaling = (the total delay value

in F2x[1, 0]9C_x[4A:30] from pass 1 of write levelization

+                        training) - RegisterDelay. */

+                     /* MemClkFreq: 3: 400Mhz; 4: 533Mhz; 5: 667Mhz;

6: 800Mhz */

+                     SeedTotal = (u16) (RegisterDelay + ((((u32)

SeedTotal - RegisterDelay) *

+

freq_tab[MemClkFreq-3]) / 400));

+                     Seed_Gross = (SeedTotal & 0x20) != 0 ? 1 : 2;

+                     Seed_Fine = SeedTotal & 0x1F;

+

pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross;

+

pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;

+                     ByteLane ++;

+              }

}

+

setWLByteDelay(pDCTData, ByteLane, dimm, 0);

}

Index: src/northbridge/amd/amdmct/mct_ddr3/mctwl.c

===================================================================

--- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c    (revision 6246)

+++ src/northbridge/amd/amdmct/mct_ddr3/mctwl.c    (working copy)

@@ -342,7 +342,21 @@

mct_Wait(250);

if (pDCTstat->Status & (1 << SB_Registered)) {

-              /* TODO: Assuming the dct==0. The agesa here is

confusing. */

+              u8 DCT0Present, DCT1Present;

+

+              DCT0Present = pDCTstat->DIMMValidDCT[0];

+              if (pDCTstat->GangedMode)

+                     DCT1Present = 0;

+              else

+                     DCT1Present = pDCTstat->DIMMValidDCT[1];

+

+              if (!DCT1Present)

+                     pDCTstat->CSPresent =

pDCTstat->CSPresent_DCT[0];

+              else if (pDCTstat->GangedMode) {

+                     pDCTstat->CSPresent = 0;

+              } else

+                     pDCTstat->CSPresent =

pDCTstat->CSPresent_DCT[1];

+

FreqChgCtrlWrd(pMCTstat, pDCTstat);

}

}

-- coreboot mailing list: [e-mail] http://www.coreboot.org/mailman/listinfo/coreboot

[Marc Jones]

On Fri, Jan 14, 2011 at 7:23 AM, Scott Duplichan  wrote:
> From: coreboot-bounces+scott=[e-mail]
> [mailto:coreboot-bounces+scott=[e-mail]] On Behalf Of Zheng
> Bao
> Sent: Friday, January 14, 2011 07:51 AM
> To: [e-mail]
> Subject: Re: [coreboot] [patch] AMD MCT DDR3 for register DIMMs
>
> ]ping.
>
> ]Any comment before it is drowned?
>
> ]Zheng
>
> Hello Bao Zheng,
>
> I do not have a setup for testing with registered DIMMs.  But I will ack the
> patch based on that fact that you have the latest agesa code and a way to
> test.
>
> Acked-by: Scott Duplichan

I don't have a registered DIMM setup to test with either. The patch looks fine.

Marc