coreboot May 2010

coreboot@coreboot.org

59 participants
300 discussions

Re: [coreboot] Warnings
by Nils 09 May '10

09 May '10

Op zondag 9 mei 2010 00:36:49 schreef u: > On 5/1/10 1:34 AM, Nils wrote: > > Hi Stefan, > > First of all thanks for the great improvements in Geode (GX2). > > > > On 4/30/10 7:50 PM, Stefan Reinauer wrote: > >> src/northbridge/amd/gx2/chipsetinit.c:271: warning: suggest > >> parentheses around '-' inside '<<' > > > > This would need help from someone with a GX2 (or willing to check out > > the data sheets ;-) > > > > I would be happy if i could be of any help with this, I have a GX2 board > > i can test on. > > Can you test the following two patches: > > Index: northbridge/amd/gx2/chipsetinit.c > =================================================================== > --- northbridge/amd/gx2/chipsetinit.c (revision 5532) > +++ northbridge/amd/gx2/chipsetinit.c (working copy) > @@ -268,7 +268,7 @@ > if ((msr.lo&0xff) == 0x11) > return; > > - totalmem = sizeram() << 20 - 1; > + totalmem = (sizeram() << 20) - 1; > totalmem >>= 12; > totalmem = ~totalmem; > totalmem &= 0xfffff; > > > and this one > > Index: northbridge/amd/gx2/chipsetinit.c > =================================================================== > --- northbridge/amd/gx2/chipsetinit.c (revision 5532) > +++ northbridge/amd/gx2/chipsetinit.c (working copy) > @@ -268,7 +268,7 @@ > if ((msr.lo&0xff) == 0x11) > return; > > - totalmem = sizeram() << 20 - 1; > + totalmem = sizeram() << (20 - 1); > totalmem >>= 12; > totalmem = ~totalmem; > totalmem &= 0xfffff; > > > and see if any of them causes a failure? > > It would seem the first patch is correct and the second is not, but i am > not sure. I tested both patches on rev 5470 and didn`t see a difference, both seem to work fine. See attached patches. > > > I saw your discussion about the warning before and it inspired me to > > dedicate my spare free time to again update my working rev5446 patches to > > current trunk. > > But unfortunately i can`t get it to work anymore on rev5120 and some > > other rev`s i tried. > > (Linux errors out with: "hda: lost interrupt") > > I will send the details in a separate mail. > > We do need to make sure we know the exact revision that broke this. > > Stefan > The exact revision that broke vsa was 5471. Thanks,Nils.

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[commit] r5537 - trunk/util/superiotool
by repository service 09 May '10

09 May '10

Author: stepan Date: Sun May 9 17:30:45 2010 New Revision: 5537 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5537 Log: Begin implementation support to IT8512/IT8513 Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/superiotool/ite.c Modified: trunk/util/superiotool/ite.c ============================================================================== --- trunk/util/superiotool/ite.c Sun May 9 17:15:08 2010 (r5536) +++ trunk/util/superiotool/ite.c Sun May 9 17:30:45 2010 (r5537) @@ -33,6 +33,10 @@ {EOT}}}, {0x8511, "IT8511E/TE/G", { {EOT}}}, + {0x8512, "IT8512E/F/G", { + {EOT}}}, + {0x8513, "IT8513E/F/G", { + {EOT}}}, {0x8661, "IT8661F/IT8770F", { {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x20,0x21,0x22,

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[commit] r5536 - trunk/src/northbridge/intel/i82830
by repository service 09 May '10

09 May '10

Author: stepan Date: Sun May 9 17:15:08 2010 New Revision: 5536 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5536 Log: i82830: fix debugging output and clarify bracketing Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/intel/i82830/i82830_smihandler.c Modified: trunk/src/northbridge/intel/i82830/i82830_smihandler.c ============================================================================== --- trunk/src/northbridge/intel/i82830/i82830_smihandler.c Sun May 9 01:28:33 2010 (r5535) +++ trunk/src/northbridge/intel/i82830/i82830_smihandler.c Sun May 9 17:15:08 2010 (r5536) @@ -258,11 +258,11 @@ if (getobj->objnum == count) { printk(BIOS_DEBUG, "| |- len = %x\n", len); memcpy((void *)(getobj->buffer + OBJ_OFFSET), - ((char *)mbi_header) + 0x20 , (len > getobj->buflen ? getobj->buflen : len)); + ((char *)mbi_header) + 0x20 , (len > getobj->buflen) ? getobj->buflen : len); getobj->banner.retsts = MSH_OK; #ifdef DEBUG_SMI_I82830 - dump(banner_id, sizeof(getobj)); + dump(banner_id, sizeof(*getobj)); dump(getobj->buffer + OBJ_OFFSET, len); #endif break;

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superiotool: Begin implementation support to IT8512/IT8513
by Антон Кочков 09 May '10

09 May '10

Begin implementation support to IT8512/IT8513 Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> ---

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Indtast Bcc [CoreBoot] PATCH: Support for Gigabyte GA-6BXE
by anders＠jenbo.dk 09 May '10

09 May '10

Most of it. IRQ tables is just me, tree is mostly me, the rest is mostly his. People keept telling me to put my name there so I did. Mvh Anders ----- Reply message ----- Fra: "Patrick Georgi" <patrick(a)georgi-clan.de> Dato: søn., maj 9, 2010 15:47 Emne: [coreboot] [CoreBoot] PATCH: Support for Gigabyte GA-6BXE Til: <coreboot(a)coreboot.org> Am 09.05.2010 02:40, schrieb Anders Jenbo: > Quick update to add my name to the headers How much of Uwe's code (which you seemed to have based the board on) is left? Patrick -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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Indtast Bcc PATCH: IT8671F Select CLKIN
by anders＠jenbo.dk 09 May '10

09 May '10

Signed-off-by: Anders Jenbo <anders(a)jenbo.dk> Mvh Anders ----- Reply message ----- Fra: "Stefan Reinauer" <stepan(a)coresystems.de> Dato: søn., maj 9, 2010 14:56 Emne: [coreboot] PATCH: IT8671F Select CLKIN Til: "Anders Jenbo" <anders(a)jenbo.dk> Cc: "Rudolf Marek" <r.marek(a)assembler.cz>, <coreboot(a)coreboot.org>

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[RFC] Getting CAR to work on P6 family; Port SECC P6 L2 cache initialization code to where?
by Keith Hui 09 May '10

09 May '10

Hi all, this is a RFC. While Joseph, Idwer and myself convened on IRC for the past two days trying to get CAR working on the P6 family of CPUs, we found that - The Intel CAR code works as is on Tualatin cores, L2 cache fully enabled The same code works for me on a Katmai, but only L1 cache is enabled This code does not boot at all for Idwer who also has a Katmai, and has stumped everyone We need to port a piece of long code from coreboot v1 that initializes the off-chip L2 cache found on Klamath/Deschutes/Katmai CPUs. They are respectively models 63x,65x and 67x. 16k of L1 is enough. We're only using 4k for CAR on Intel. It was written in C. I looked at the OEM BIOS for P2B-LS and L2 is initialized from the "inner BIOS", like the RAM stage of coreboot, when RAM is fully up and running. This means this can go into model_6xx_init(), which is prefereable as I just need to make enough adjustments to make it work again. Joseph OTOH suggests that I should port this code into cache_as_ram.inc which is much earlier, actually before motherboard romstage. This code is assembly, meaning I'll need to port this thing back to assembly. Question is: Where should I port this code to? CPU driver, or cache_as_ram.inc? A patch to separate model 67x from model 6xx will soon come, either from me or Joseph. A similar one could be done for 65x and 63x. I do not have 66x Celerons to test so I cannot ascertain if this special attention will be needed for them. Thanks Keith

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[RFC] Getting CAR to work on P6 family; Port SECC P6 L2 cache initialization code to where?
by anders＠jenbo.dk 09 May '10

09 May '10

I have two Deschutes and a 1ghz PIII that I would happily test your code on. Mvh Anders ----- Reply message ----- Fra: "Joseph Smith" <joe(a)settoplinux.org> Dato: søn., maj 9, 2010 07:45 Emne: [coreboot] [RFC] Getting CAR to work on P6 family; Port SECC P6 L2 cache initialization code to where? Til: "Keith Hui" <buurin(a)gmail.com> Cc: <coreboot(a)coreboot.org> On 05/09/2010 01:33 AM, Keith Hui wrote: > Hi all, this is a RFC. > > While Joseph, Idwer and myself convened on IRC for the past two days > trying to get CAR working on the P6 family of CPUs, we found that - > > The Intel CAR code works as is on Tualatin cores, L2 cache fully enabled > The same code works for me on a Katmai, but only L1 cache is enabled > This code does not boot at all for Idwer who also has a Katmai, and > has stumped everyone > We need to port a piece of long code from coreboot v1 that initializes > the off-chip L2 cache found on Klamath/Deschutes/Katmai CPUs. > They are respectively models 63x,65x and 67x. > 16k of L1 is enough. We're only using 4k for CAR on Intel. > > It was written in C. I looked at the OEM BIOS for P2B-LS and L2 is > initialized from the "inner BIOS", like the RAM stage of coreboot, > when RAM is fully up and running. This means this can go into > model_6xx_init(), which is prefereable as I just need to make enough > adjustments to make it work again. > > Joseph OTOH suggests that I should port this code into > cache_as_ram.inc which is much earlier, actually before motherboard > romstage. This code is assembly, meaning I'll need to port this thing > back to assembly. > > Question is: Where should I port this code to? CPU driver, or cache_as_ram.inc? > Hmm, I guess it does not really need to be done in cache_as_ram if the 16k is large enough to get things going. So if it would be easier I would suggest early in model_6*x_init(). Especially if the vendor bios enables it post raminit. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] [PATCH] improve realmode api
by Nils 08 May '10

08 May '10

Op zondag 9 mei 2010 00:41:06 schreef u: > > Attached a log from rev5470. > > cool thanks... > could you send one for 5471 too, please? > Here you go, attached. Nils.

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[commit] r5535 - trunk/util/superiotool
by repository service 08 May '10

08 May '10

Author: linux_junkie Date: Sun May 9 01:28:33 2010 New Revision: 5535 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5535 Log: Add registers for the it8671f chip. Signed-off-by: Anders Jenbo <anders(a)jenbo.dk> Acked-by: Joseph Smith <joe(a)settoplinux.org> Modified: trunk/util/superiotool/ite.c Modified: trunk/util/superiotool/ite.c ============================================================================== --- trunk/util/superiotool/ite.c Sun May 9 00:02:54 2010 (r5534) +++ trunk/util/superiotool/ite.c Sun May 9 01:28:33 2010 (r5535) @@ -69,6 +69,33 @@ {0x8673, "IT8673F", { {EOT}}}, {0x8681, "IT8671F/IT8687R", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x2E,0x2F,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,0x00,NANA,0x86,0x81,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x0, "Floppy disk controller", + {0x30,0x31,0x60,0x61,0x70,0x71,0x74,0xF0,EOT}, + {0x00,0x00,0x03,0xF0,0x06,0x02,0x02,0x00,EOT}}, + {0x1, "COM1", + {0x30,0x31,0x60,0x61,0x70,0x71,0xF0,EOT}, + {0x00,0x00,0x03,0xF8,0x04,0x02,0x00,EOT}}, + {0x2, "COM2", + {0x30,0x31,0x60,0x61,0x62,0x63,0x70,0x71,0x72,0x73,0x74,0x75,0xF0,0xF1,EOT}, + {0x00,0x00,0x02,0xF8,0x03,0x00,0x03,0x02,0x0A,0x02,0x00,0x01,0x00,0x00,EOT}}, + {0x3, "Parallel port", + {0x30,0x31,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0xF0,EOT}, + {0x00,0x00,0x01,0x78,0x07,0x78,0x07,0x02,0x03,0x03,EOT}}, + {0x4, "APC", + {0x30,0xF0,0xF1,0xF2,0xF4,0xF5,0xF6,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,NANA,EOT}}, + {0x5, "Keyboard", + {0x30,0x31,0x60,0x61,0x62,0x63,0x70,0x71,0xF0,EOT}, + {0x01,0x00,0x00,0x60,0x00,0x64,0x01,0x02,0x00,EOT}}, + {0x6, "Mouse", + {0x30,0x70,0x71,0xF0,EOT}, + {0x00,0x0C,0x02,0x00,EOT}}, + {0x7, "GPIO and Alternative function", + {0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x70,0x71,0x72,0x73,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF,0xE0,0xE1,0xE2,0xE3,0xE4,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, {EOT}}}, {0x8701, "IT8703F", { {NOLDN, NULL,

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coreboot May 2010