coreboot May 2010

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[commit] r5542 - trunk/src/northbridge/amd/amdfam10
by repository service 10 May '10

10 May '10

Author: myles Date: Mon May 10 21:45:45 2010 New Revision: 5542 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5542 Log: Make show_all_routes work for fam10. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/northbridge/amd/amdfam10/Makefile.inc trunk/src/northbridge/amd/amdfam10/amdfam10.h trunk/src/northbridge/amd/amdfam10/util.c Modified: trunk/src/northbridge/amd/amdfam10/Makefile.inc ============================================================================== --- trunk/src/northbridge/amd/amdfam10/Makefile.inc Mon May 10 21:38:59 2010 (r5541) +++ trunk/src/northbridge/amd/amdfam10/Makefile.inc Mon May 10 21:45:45 2010 (r5542) @@ -10,3 +10,7 @@ obj-$(CONFIG_GENERATE_ACPI_TABLES) += sspr5.o obj-y += get_pci1234.o + +# Enable this if you want to check the values of the PCI routing registers. +# Call show_all_routes() anywhere amdfam10.h is included. +#obj-y += util.o Modified: trunk/src/northbridge/amd/amdfam10/amdfam10.h ============================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10.h Mon May 10 21:38:59 2010 (r5541) +++ trunk/src/northbridge/amd/amdfam10/amdfam10.h Mon May 10 21:45:45 2010 (r5542) @@ -1169,4 +1169,8 @@ #endif +#ifndef __ROMCC__ +void showallroutes(int level, device_t dev); +#endif + #endif /* AMDFAM10_H */ Modified: trunk/src/northbridge/amd/amdfam10/util.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/util.c Mon May 10 21:38:59 2010 (r5541) +++ trunk/src/northbridge/amd/amdfam10/util.c Mon May 10 21:45:45 2010 (r5542) @@ -19,18 +19,18 @@ */ /* - * K8 northbridge utilities (dump routing registers). + * fam10 northbridge utilities (dump routing registers). * Designed to be called at any time. * It can be called before RAM is set up by including this file. - * It can be called after RAM is set up by including amdk8.h and enabling the - * compilation of this file in src/northbridge/amd/amdk8/Makefile.inc. + * It can be called after RAM is set up by including amdfam10.h and enabling the + * compilation of this file in src/northbridge/amd/amdfam10/Makefile.inc. */ #ifndef __PRE_RAM__ #include <console/console.h> #include <device/pci.h> #include <device/pci_ops.h> #endif -#include "amdk8.h" +#include "amdfam10.h" /* Function 1 */ /* the DRAM, MMIO,and PCIIO routing are 64-bit registers, hence the ending at

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[commit] r5541 - in trunk/src/northbridge/amd: amdfam10 amdk8
by repository service 10 May '10

10 May '10

Author: myles Date: Mon May 10 21:38:59 2010 New Revision: 5541 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5541 Log: High tables don't have to be on node 0 on K8. Make it less restrictive. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Added: trunk/src/northbridge/amd/amdfam10/util.c (props changed) - copied unchanged from r5527, trunk/src/northbridge/amd/amdk8/util.c Modified: trunk/src/northbridge/amd/amdk8/northbridge.c Copied: trunk/src/northbridge/amd/amdfam10/util.c (from r5527, trunk/src/northbridge/amd/amdk8/util.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/northbridge/amd/amdfam10/util.c Mon May 10 21:38:59 2010 (r5541, copy of r5527, trunk/src/northbridge/amd/amdk8/util.c) @@ -0,0 +1,273 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Vincent Legoll <vincent.legoll(a)gmail.com> + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +/* + * K8 northbridge utilities (dump routing registers). + * Designed to be called at any time. + * It can be called before RAM is set up by including this file. + * It can be called after RAM is set up by including amdk8.h and enabling the + * compilation of this file in src/northbridge/amd/amdk8/Makefile.inc. + */ +#ifndef __PRE_RAM__ +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#endif +#include "amdk8.h" + +/* Function 1 */ +/* the DRAM, MMIO,and PCIIO routing are 64-bit registers, hence the ending at + * 0x78, 0xb8, and 0xd8 + */ +#define DRAM_ROUTE_START 0x40 +#define DRAM_ROUTE_END 0x78 +#define MMIO_ROUTE_START 0x80 +#define MMIO_ROUTE_END 0xb8 +#define PCIIO_ROUTE_START 0xc0 +#define PCIIO_ROUTE_END 0xd8 +#define CONFIG_ROUTE_START 0xe0 +#define CONFIG_ROUTE_END 0xec + +#define PCI_IO_BASE0 0xc0 +#define PCI_IO_BASE1 0xc8 +#define PCI_IO_BASE2 0xd0 +#define PCI_IO_BASE3 0xd8 +#define PCI_IO_BASE_VGA_EN (1 << 4) +#define PCI_IO_BASE_NO_ISA (1 << 5) + +#define BITS(r, shift, mask) (((r>>shift)&mask)) + +/** + * Return "R" if the register has read-enable bit set. + */ +static const char *re(u32 i) +{ + return ((i & 1) ? "R" : ""); +} + +/** + * Return "W" if the register has write-enable bit set. + */ +static const char *we(u32 i) +{ + return ((i & 1) ? "W" : ""); +} + +/** + * Return a string containing the interleave settings. + */ +static const char *ileave(u32 base) +{ + switch ((base >> 8) & 7) { + case 0: + return "No interleave"; + case 1: + return "2 nodes"; + case 3: + return "4 nodes"; + case 7: + return "8 nodes"; + default: + return "Reserved"; + } +} + +/** + * Return the node number. + * For one case (config registers) these are not the right bit fields. + */ +static int r_node(u32 reg) +{ + return BITS(reg, 0, 0x7); +} + +/** + * Return the link number. + * For one case (config registers) these are not the right bit fields. + */ +static int r_link(u32 reg) +{ + return BITS(reg, 4, 0x3); +} + +/** + * Print the DRAM routing info for one base/limit pair. + * + * Show base, limit, dest node, dest link on that node, read and write + * enable, and interleave information. + * + * @param level Printing level + * @param which Register number + * @param base Base register + * @param lim Limit register + */ +static void showdram(int level, u8 which, u32 base, u32 lim) +{ + printk(level, "DRAM(%02x)%010llx-%010llx, ->(%d), %s, %s, %s, %d\n", + which, (((u64) base & 0xffff0000) << 8), + (((u64) lim & 0xffff0000) << 8) + 0xffffff, + r_node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3); +} + +/** + * Print the config routing info for a config register. + * + * Show base, limit, dest node, dest link on that node, read and write + * enable, and device number compare enable + * + * @param level Printing level + * @param which Register number + * @param reg Config register + */ +static void showconfig(int level, u8 which, u32 reg) +{ + /* Don't use r_node() and r_link() here. */ + printk(level, "CONFIG(%02x)%02x-%02x ->(%d,%d),%s %s (%s numbers)\n", + which, BITS(reg, 16, 0xff), BITS(reg, 24, 0xff), + BITS(reg, 4, 0x7), BITS(reg, 8, 0x3), + re(reg), we(reg), + BITS(reg, 2, 0x1)?"dev":"bus"); +} + +/** + * Print the PCIIO routing info for one base/limit pair. + * + * Show base, limit, dest node, dest link on that node, read and write + * enable, and VGA and ISA Enable. + * + * @param level Printing level + * @param which Register number + * @param base Base register + * @param lim Limit register + */ +static void showpciio(int level, u8 which, u32 base, u32 lim) +{ + printk(level, "PCIIO(%02x)%07x-%07x, ->(%d,%d), %s, %s,VGA %d ISA %d\n", + which, BITS(base, 12, 0x3fff) << 12, + (BITS(lim, 12, 0x3fff) << 12) + 0xfff, r_node(lim), r_link(lim), + re(base), we(base), BITS(base, 4, 0x1), BITS(base, 5, 0x1)); +} + +/** + * Print the MMIO routing info for one base/limit pair. + * + * Show base, limit, dest node, dest link on that node, read and write + * enable, and CPU Disable, Lock, and Non-posted. + * + * @param level Printing level + * @param which Register number + * @param base Base register + * @param lim Limit register + */ +static void showmmio(int level, u8 which, u32 base, u32 lim) +{ + printk(level, "MMIO(%02x)%010llx-%010llx, ->(%d,%d), %s, %s, " + "CPU disable %d, Lock %d, Non posted %d\n", + which, ((u64) BITS(base, 0, 0xffffff00)) << 8, + (((u64) BITS(lim, 0, 0xffffff00)) << 8) + 0xffff, r_node(lim), + r_link(lim), re(base), we(base), BITS(base, 4, 0x1), + BITS(base, 7, 0x1), BITS(lim, 7, 0x1)); +} + +/** + * Show all DRAM routing registers. This function is callable at any time. + * + * @param level The debug level. + * @param dev A 32-bit number in the standard bus/dev/fn format which is used + * raw config space. + */ +static void showalldram(int level, device_t dev) +{ + u8 reg; + for (reg = DRAM_ROUTE_START; reg <= DRAM_ROUTE_END; reg += 8) { + u32 base = pci_read_config32(dev, reg); + u32 lim = pci_read_config32(dev, reg + 4); + if (base || lim!=(reg-DRAM_ROUTE_START)/8) + showdram(level, reg, base, lim); + } +} + +/** + * Show all MMIO routing registers. This function is callable at any time. + * + * @param level The debug level. + * @param dev A 32-bit number in the standard bus/dev/fn format which is used + * raw config space. + */ +static void showallmmio(int level, device_t dev) +{ + u8 reg; + for (reg = MMIO_ROUTE_START; reg <= MMIO_ROUTE_END; reg += 8) { + u32 base = pci_read_config32(dev, reg); + u32 lim = pci_read_config32(dev, reg + 4); + if (base || lim) + showmmio(level, reg, base, lim); + } +} + +/** + * Show all PCIIO routing registers. This function is callable at any time. + * + * @param level The debug level. + * @param dev A 32-bit number in the standard bus/dev/fn format which is used + * raw config space. + */ +static void showallpciio(int level, device_t dev) +{ + u8 reg; + for (reg = PCIIO_ROUTE_START; reg <= PCIIO_ROUTE_END; reg += 8) { + u32 base = pci_read_config32(dev, reg); + u32 lim = pci_read_config32(dev, reg + 4); + if (base || lim) + showpciio(level, reg, base, lim); + } +} + +/** + * Show all config routing registers. This function is callable at any time. + * + * @param level The debug level. + * @param dev A 32-bit number in the standard bus/dev/fn format which is used + * raw config space. + */ +static void showallconfig(int level, device_t dev) +{ + u8 reg; + for (reg = CONFIG_ROUTE_START; reg <= CONFIG_ROUTE_END; reg += 4) { + u32 val = pci_read_config32(dev, reg); + if (val) + showconfig(level, reg, val); + } +} + +/** + * Show all routing registers. This function is callable at any time. + * + * @param level The debug level. + * @param dev A 32-bit number in the standard bus/dev/fn format which is used + * raw config space. + */ +void showallroutes(int level, device_t dev) +{ + showalldram(level, dev); + showallmmio(level, dev); + showallpciio(level, dev); + showallconfig(level, dev); +} Modified: trunk/src/northbridge/amd/amdk8/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/northbridge.c Sun May 9 23:44:52 2010 (r5540) +++ trunk/src/northbridge/amd/amdk8/northbridge.c Mon May 10 21:38:59 2010 (r5541) @@ -1021,7 +1021,7 @@ idx += 0x10; sizek -= pre_sizek; #if CONFIG_WRITE_HIGH_TABLES==1 - if (i==0 && high_tables_base==0) { + if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); @@ -1061,7 +1061,7 @@ #if CONFIG_WRITE_HIGH_TABLES==1 printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); - if (i==0 && high_tables_base==0) { + if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);

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Re: [coreboot] Indtast Bcc Dell Optiplex GX1 support
by Anders Jenbo 10 May '10

10 May '10

Serial Cable is only for debug output. USB should work fine. Start by downloding the source. $ svn co svn://coreboot.org/coreboot/trunk coreboot go to the src/mainboard/tyan folder and copy the folder for the s1846, it has all the same chips as your board so we will use it to base your board of. You should call yor dolder src/mainboard/dell/optiplex_gx1. Edit src/ mainboard/dell/Kconfig, add 'source "src/mainboard/delloptiplex_gx1/ Kconfig"' abouve the existing source line. Open the Kconfig in yor board folder and change all the references to your board. Run lspci -tvnn and make sure that your devicetree.cb seams to match it's output. Open mainboard.c and correct the board name. Go back to the coreboot folder type make menuconfig, select your board and make any other adjustments that you think is needed or would like. Exit and save, run make. Hopfully it will compile a 256kb rom image. We also need to know somthing about your rom chip so run flashrom and post the out put her. Next I'll try to help you saifly flash your board and posibly improve the support for your board. Mvh Anders Den 09/05/2010 kl. 18.27 skrev Cooper Harrison <coop.rocks.123e(a)gmail.com >: > Who cares about ACPI! :D I don't have ECC memory either. Can I use > an USB keyboard as input or do I have to get a serial cable? > > On Thu, May 6, 2010 at 11:24 AM, anders(a)jenbo.dk <anders(a)jenbo.dk> > wrote: > Hi > > As you are the only one who has this board you will have to do a bit > of the work your self. But I would be glad to help you, I recently > ported coreboot to a 440bx board, Ubuntu boots on it so Debians > should work fine. > There is still a few limitations in the support for this chip. No L2 > cache no ecc memory, only sdram and no ACPI. > > Also it looks like you won't have support for any legacy I/O (ps2 > keyboard pc speaker) > > You could of ofcourse fix all this by reading the docs an coding a > bit of C :) > > -Anders > > ----- Reply message ----- > Fra: "Cooper Harrison" <coop.rocks.123e(a)gmail.com> > Dato: tor., maj 6, 2010 14:04 > Emne: [coreboot] Dell Optiplex GX1 support > Til: <coreboot(a)coreboot.org> > > By looking at all the supported hardware, it looks like it should > work at a minimum amount. It has an Intel 440BX, an Intel PIIX4e and > a NSC (formerly National) PC87309. Will I be able to boot Debian and > if not, how soon until whoever is working on it estimates they will > have it at a working status? I am just wondering as I think it would > be cool to have it on my computer. > -- > Cooper > > > > -- > Cooper

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Re: [coreboot] Re Dell Optiplex GX1 support
by Anders Jenbo 10 May '10

10 May '10

Remember to reply to all so that the mail also ends up on the mailing list. I think it should be: bool "Optplex GX1" Also select BOARD_ROMSIZE_MB_2 should be select BOARD_ROMSIZE_KB_2048 Be aware that ROMs are often specified in bit's and not bytes, so if you have a 2Mb (mega bits) is is actually 256KB (kilo bytes), if that is the case it should be: select BOARD_ROMSIZE_KB_256 Witch is what all other 440BX boards seams to have. -Anders man, 10 05 2010 kl. 07:56 -0400, skrev Cooper Harrison: > > bool "Dell Optplex GX1 Mainboard"

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Re Dell Optiplex GX1 support
by anders＠jenbo.dk 10 May '10

10 May '10

You forgot to change bool "S1846 (Tsunami ATX)". 2 MB is not a problem but you should run flashrom to make sure. Mvh Anders ----- Reply message ----- Fra: "Cooper Harrison" <coop.rocks.123e(a)gmail.com> Dato: man., maj 10, 2010 02:23 Emne: Indtast Bcc [coreboot] Dell Optiplex GX1 support Til: "Anders Jenbo" <anders(a)jenbo.dk> Cc: <coreboot(a)coreboot.org>

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[commit] r5540 - in trunk/src: arch/i386/include northbridge/amd/amdht
by repository service 09 May '10

09 May '10

Author: oxygene Date: Sun May 9 23:44:52 2010 New Revision: 5540 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5540 Log: Remove extra NULL #define in amdht code. The common one is enough. Trivial Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/arch/i386/include/stddef.h trunk/src/northbridge/amd/amdht/porting.h Modified: trunk/src/arch/i386/include/stddef.h ============================================================================== --- trunk/src/arch/i386/include/stddef.h Sun May 9 23:15:13 2010 (r5539) +++ trunk/src/arch/i386/include/stddef.h Sun May 9 23:44:52 2010 (r5540) @@ -8,9 +8,7 @@ typedef int wchar_t; typedef unsigned int wint_t; -#ifndef NULL #define NULL ((void *)0) -#endif #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) Modified: trunk/src/northbridge/amd/amdht/porting.h ============================================================================== --- trunk/src/northbridge/amd/amdht/porting.h Sun May 9 23:15:13 2010 (r5539) +++ trunk/src/northbridge/amd/amdht/porting.h Sun May 9 23:44:52 2010 (r5540) @@ -77,10 +77,6 @@ void CALLCONV AmdCPUIDRead(uint32 Address, uint32 Regs[4]); void CALLCONV ErrorStop(uint32 Value); -#ifndef NULL -#define NULL ((void *) 0) -#endif - #define BYTESIZE 1 #define WORDSIZE 2 #define DWORDSIZE 4

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[commit] r5539 - in trunk/src: arch/i386/include cpu/amd/car cpu/amd/model_10xxx cpu/amd/quadcore include/cpu/amd northbridge/amd/amdht northbridge/amd/amdmct/mct superio/smsc/smscsuperio
by repository service 09 May '10

09 May '10

Author: oxygene Date: Sun May 9 23:15:13 2010 New Revision: 5539 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5539 Log: Move includes to where they are needed. This allows to simplify romstage.c files in mainboards. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/arch/i386/include/stddef.h trunk/src/cpu/amd/car/post_cache_as_ram.c trunk/src/cpu/amd/model_10xxx/defaults.h trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/quadcore/quadcore.c trunk/src/include/cpu/amd/model_10xxx_msr.h trunk/src/northbridge/amd/amdht/ht_wrapper.c trunk/src/northbridge/amd/amdmct/mct/mctmtr_d.c trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c Modified: trunk/src/arch/i386/include/stddef.h ============================================================================== --- trunk/src/arch/i386/include/stddef.h Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/arch/i386/include/stddef.h Sun May 9 23:15:13 2010 (r5539) @@ -8,7 +8,9 @@ typedef int wchar_t; typedef unsigned int wint_t; +#ifndef NULL #define NULL ((void *)0) +#endif #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c ============================================================================== --- trunk/src/cpu/amd/car/post_cache_as_ram.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/cpu/amd/car/post_cache_as_ram.c Sun May 9 23:15:13 2010 (r5539) @@ -1,6 +1,7 @@ /* 2005.6 by yhlu * 2006.3 yhlu add copy data from CAR to ram */ +#include <string.h> #include <arch/stages.h> #include "cpu/amd/car/disable_cache_as_ram.c" Modified: trunk/src/cpu/amd/model_10xxx/defaults.h ============================================================================== --- trunk/src/cpu/amd/model_10xxx/defaults.h Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/cpu/amd/model_10xxx/defaults.h Sun May 9 23:15:13 2010 (r5539) @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <northbridge/amd/amdmct/amddefs.h> +#include <cpu/amd/mtrr.h> /* * Default MSR and errata settings. Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Sun May 9 23:15:13 2010 (r5539) @@ -18,6 +18,12 @@ */ #include "defaults.h" +#include <stdlib.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/mtrr.h> +#include <northbridge/amd/amdfam10/amdfam10.h> +#include <northbridge/amd/amdht/AsPsDefs.h> +#include <northbridge/amd/amdht/porting.h> //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID #ifndef SET_FIDVID Modified: trunk/src/cpu/amd/quadcore/quadcore.c ============================================================================== --- trunk/src/cpu/amd/quadcore/quadcore.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/cpu/amd/quadcore/quadcore.c Sun May 9 23:15:13 2010 (r5539) @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <console/console.h> #ifndef SET_NB_CFG_54 #define SET_NB_CFG_54 1 Modified: trunk/src/include/cpu/amd/model_10xxx_msr.h ============================================================================== --- trunk/src/include/cpu/amd/model_10xxx_msr.h Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/include/cpu/amd/model_10xxx_msr.h Sun May 9 23:15:13 2010 (r5539) @@ -20,6 +20,8 @@ #ifndef CPU_AMD_MODEL_10XXX_MSR_H #define CPU_AMD_MODEL_10XXX_MSR_H +#include <cpu/x86/msr.h> + #define HWCR_MSR 0xC0010015 #define NB_CFG_MSR 0xC001001f #define LS_CFG_MSR 0xC0011020 Modified: trunk/src/northbridge/amd/amdht/ht_wrapper.c ============================================================================== --- trunk/src/northbridge/amd/amdht/ht_wrapper.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/northbridge/amd/amdht/ht_wrapper.c Sun May 9 23:15:13 2010 (r5539) @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cpu/x86/msr.h> +#include <console/console.h> +#include <northbridge/amd/amdfam10/amdfam10.h> /*---------------------------------------------------------------------------- * TYPEDEFS, DEFINITIONS AND MACROS Modified: trunk/src/northbridge/amd/amdmct/mct/mctmtr_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctmtr_d.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/northbridge/amd/amdmct/mct/mctmtr_d.c Sun May 9 23:15:13 2010 (r5539) @@ -19,6 +19,7 @@ #include "mct_d.h" +#include <cpu/amd/mtrr.h> static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr); static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType); Modified: trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c ============================================================================== --- trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c Sun May 9 23:09:58 2010 (r5538) +++ trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c Sun May 9 23:15:13 2010 (r5539) @@ -19,6 +19,7 @@ */ #include <arch/romcc_io.h> +#include <device/pnp_def.h> /* All known/supported SMSC Super I/Os have the same logical device IDs * for the serial ports (COM1, COM2).

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[commit] r5538 - in trunk/src: include/console mainboard/a-trend/atc-6220 mainboard/a-trend/atc-6240 mainboard/abit/be6-ii_v2_0 mainboard/advantech/pcm-5820 mainboard/amd/rumba mainboard/asi/mb_5bl...
by repository service 09 May '10

09 May '10

Author: oxygene Date: Sun May 9 23:09:58 2010 New Revision: 5538 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5538 Log: Remove pc80/serial.c includes in ROMCC boards and include it centrally in console/console.h instead. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/include/console/console.h trunk/src/mainboard/a-trend/atc-6220/romstage.c trunk/src/mainboard/a-trend/atc-6240/romstage.c trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c trunk/src/mainboard/advantech/pcm-5820/romstage.c trunk/src/mainboard/amd/rumba/romstage.c trunk/src/mainboard/asi/mb_5blgp/romstage.c trunk/src/mainboard/asi/mb_5blmp/romstage.c trunk/src/mainboard/asus/mew-am/romstage.c trunk/src/mainboard/asus/mew-vm/romstage.c trunk/src/mainboard/asus/p2b-d/romstage.c trunk/src/mainboard/asus/p2b-ds/romstage.c trunk/src/mainboard/asus/p2b-f/romstage.c trunk/src/mainboard/asus/p2b-ls/romstage.c trunk/src/mainboard/asus/p2b/romstage.c trunk/src/mainboard/asus/p3b-f/romstage.c trunk/src/mainboard/axus/tc320/romstage.c trunk/src/mainboard/azza/pt-6ibd/romstage.c trunk/src/mainboard/bcom/winnet100/romstage.c trunk/src/mainboard/biostar/m6tba/romstage.c trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c trunk/src/mainboard/dell/s1850/romstage.c trunk/src/mainboard/digitallogic/msm586seg/romstage.c trunk/src/mainboard/eaglelion/5bcm/romstage.c trunk/src/mainboard/emulation/qemu-x86/romstage.c trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c trunk/src/mainboard/iei/juki-511p/romstage.c trunk/src/mainboard/iei/nova4899r/romstage.c trunk/src/mainboard/intel/jarrell/romstage.c trunk/src/mainboard/intel/mtarvon/romstage.c trunk/src/mainboard/intel/truxton/romstage.c trunk/src/mainboard/intel/xe7501devkit/romstage.c trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/mitac/6513wu/romstage.c trunk/src/mainboard/msi/ms6119/romstage.c trunk/src/mainboard/msi/ms6147/romstage.c trunk/src/mainboard/msi/ms6156/romstage.c trunk/src/mainboard/msi/ms6178/romstage.c trunk/src/mainboard/nec/powermate2000/romstage.c trunk/src/mainboard/nokia/ip530/romstage.c trunk/src/mainboard/olpc/btest/romstage.c trunk/src/mainboard/olpc/rev_a/romstage.c trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c trunk/src/mainboard/supermicro/x6dai_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c trunk/src/mainboard/technologic/ts5300/romstage.c trunk/src/mainboard/televideo/tc7020/romstage.c trunk/src/mainboard/tyan/s1846/romstage.c trunk/src/mainboard/via/epia-m/romstage.c trunk/src/mainboard/via/epia-n/romstage.c trunk/src/mainboard/via/epia/romstage.c trunk/src/mainboard/wyse/s50/romstage.c Modified: trunk/src/include/console/console.h ============================================================================== --- trunk/src/include/console/console.h Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/include/console/console.h Sun May 9 23:09:58 2010 (r5538) @@ -129,6 +129,7 @@ #define print_spew_hex32(HEX) printk(BIOS_SPEW, "%08x", (HEX)) #else +#include <pc80/serial.c> /* __ROMCC__ */ static void __console_tx_byte(unsigned char byte) Modified: trunk/src/mainboard/a-trend/atc-6220/romstage.c ============================================================================== --- trunk/src/mainboard/a-trend/atc-6220/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/a-trend/atc-6220/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/a-trend/atc-6240/romstage.c ============================================================================== --- trunk/src/mainboard/a-trend/atc-6240/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/a-trend/atc-6240/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c ============================================================================== --- trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/advantech/pcm-5820/romstage.c ============================================================================== --- trunk/src/mainboard/advantech/pcm-5820/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/advantech/pcm-5820/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -23,7 +23,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" Modified: trunk/src/mainboard/amd/rumba/romstage.c ============================================================================== --- trunk/src/mainboard/amd/rumba/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/amd/rumba/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -4,7 +4,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Modified: trunk/src/mainboard/asi/mb_5blgp/romstage.c ============================================================================== --- trunk/src/mainboard/asi/mb_5blgp/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asi/mb_5blgp/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -23,7 +23,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" Modified: trunk/src/mainboard/asi/mb_5blmp/romstage.c ============================================================================== --- trunk/src/mainboard/asi/mb_5blmp/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asi/mb_5blmp/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -24,7 +24,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" Modified: trunk/src/mainboard/asus/mew-am/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-am/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asus/mew-am/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" Modified: trunk/src/mainboard/asus/mew-vm/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-vm/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asus/mew-vm/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c" Modified: trunk/src/mainboard/asus/p2b-d/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-d/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asus/p2b-d/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <cpu/x86/lapic.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/asus/p2b-ds/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asus/p2b-ds/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <cpu/x86/lapic.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/asus/p2b-f/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-f/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asus/p2b-f/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/asus/p2b-ls/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ls/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asus/p2b-ls/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/asus/p2b/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asus/p2b/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/asus/p3b-f/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p3b-f/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/asus/p3b-f/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/axus/tc320/romstage.c ============================================================================== --- trunk/src/mainboard/axus/tc320/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/axus/tc320/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -24,7 +24,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" Modified: trunk/src/mainboard/azza/pt-6ibd/romstage.c ============================================================================== --- trunk/src/mainboard/azza/pt-6ibd/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/azza/pt-6ibd/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/bcom/winnet100/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnet100/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/bcom/winnet100/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -24,7 +24,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" Modified: trunk/src/mainboard/biostar/m6tba/romstage.c ============================================================================== --- trunk/src/mainboard/biostar/m6tba/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/biostar/m6tba/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c ============================================================================== --- trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/dell/s1850/romstage.c ============================================================================== --- trunk/src/mainboard/dell/s1850/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/dell/s1850/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -7,7 +7,6 @@ #include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/eaglelion/5bcm/romstage.c ============================================================================== --- trunk/src/mainboard/eaglelion/5bcm/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/eaglelion/5bcm/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" //#include "southbridge/intel/i440bx/i440bx_early_smbus.c" Modified: trunk/src/mainboard/emulation/qemu-x86/romstage.c ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/emulation/qemu-x86/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -7,7 +7,6 @@ #include <arch/hlt.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include <console/console.h> #include "pc80/udelay_io.c" #include "lib/delay.c" Modified: trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c ============================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" /* TODO: It's a PC87364 actually! */ Modified: trunk/src/mainboard/iei/juki-511p/romstage.c ============================================================================== --- trunk/src/mainboard/iei/juki-511p/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/iei/juki-511p/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -24,7 +24,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "superio/winbond/w83977f/w83977f_early_serial.c" Modified: trunk/src/mainboard/iei/nova4899r/romstage.c ============================================================================== --- trunk/src/mainboard/iei/nova4899r/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/iei/nova4899r/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -24,7 +24,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" Modified: trunk/src/mainboard/intel/jarrell/romstage.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/intel/jarrell/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -7,7 +7,6 @@ #include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/intel/mtarvon/romstage.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/intel/mtarvon/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -27,7 +27,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" Modified: trunk/src/mainboard/intel/truxton/romstage.c ============================================================================== --- trunk/src/mainboard/intel/truxton/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/intel/truxton/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -27,7 +27,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include "pc80/udelay_io.c" #include <console/console.h> #include "lib/ramtest.c" Modified: trunk/src/mainboard/intel/xe7501devkit/romstage.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/intel/xe7501devkit/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -8,7 +8,6 @@ #include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c" Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -4,7 +4,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Modified: trunk/src/mainboard/mitac/6513wu/romstage.c ============================================================================== --- trunk/src/mainboard/mitac/6513wu/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/mitac/6513wu/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" Modified: trunk/src/mainboard/msi/ms6119/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6119/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/msi/ms6119/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/msi/ms6147/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6147/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/msi/ms6147/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/msi/ms6156/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6156/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/msi/ms6156/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/msi/ms6178/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6178/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/msi/ms6178/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Modified: trunk/src/mainboard/nec/powermate2000/romstage.c ============================================================================== --- trunk/src/mainboard/nec/powermate2000/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/nec/powermate2000/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" Modified: trunk/src/mainboard/nokia/ip530/romstage.c ============================================================================== --- trunk/src/mainboard/nokia/ip530/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/nokia/ip530/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/olpc/btest/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/btest/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/olpc/btest/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -4,7 +4,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Modified: trunk/src/mainboard/olpc/rev_a/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/rev_a/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/olpc/rev_a/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -4,7 +4,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c ============================================================================== --- trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -7,7 +7,6 @@ #include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "pc80/udelay_io.c" Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -7,7 +7,6 @@ #include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "pc80/udelay_io.c" Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -7,7 +7,6 @@ #include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -7,7 +7,6 @@ #include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -7,7 +7,6 @@ #include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/technologic/ts5300/romstage.c ============================================================================== --- trunk/src/mainboard/technologic/ts5300/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/technologic/ts5300/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -11,7 +11,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/televideo/tc7020/romstage.c ============================================================================== --- trunk/src/mainboard/televideo/tc7020/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/televideo/tc7020/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -24,7 +24,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" Modified: trunk/src/mainboard/tyan/s1846/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s1846/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/tyan/s1846/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" Modified: trunk/src/mainboard/via/epia-m/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/via/epia-m/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -6,7 +6,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "northbridge/via/vt8623/raminit.h" Modified: trunk/src/mainboard/via/epia-n/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-n/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/via/epia-n/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -26,7 +26,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "northbridge/via/cn400/raminit.h" Modified: trunk/src/mainboard/via/epia/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/via/epia/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "northbridge/via/vt8601/raminit.h" Modified: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- trunk/src/mainboard/wyse/s50/romstage.c Sun May 9 17:30:45 2010 (r5537) +++ trunk/src/mainboard/wyse/s50/romstage.c Sun May 9 23:09:58 2010 (r5538) @@ -4,15 +4,12 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include <console/console.h> #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) - #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c"

1 0

[PATCH]Include headers instead of sources in romstage, part 2/many
by Patrick Georgi 09 May '10

09 May '10

Hi, attached patch completes the changes from the first part, by eliminating the direct inclusion of pc80/serial.c in all romstage.c files. So far, they were still around in ROMCC builds. I moved the include to console/console.h, guarded so it's only included for ROMCC, as this file is a direct consumer of the functions in pc80/serial.c It's abuild tested and Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

3 3

[PATCH]Move includes to files that actually use them
by Patrick Georgi 09 May '10

09 May '10

Hi, as part of the ongoing quest to clean up the code to make it easier to use and adapt, I added a couple of #include statements to AMD code, so it gains some self-sufficiency. These includes are necessary because those files use their definitions. It only works so far because the romstage carefully includes files in the right order so everything is included before it's needed by another file. This change, and similar ones that will come after it, allow us to simplify the romstage.c of boards that use these chipsets (ie. Fam10 for this patch), making it easier to support new boards. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 1

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coreboot May 2010