coreboot May 2010

coreboot@coreboot.org

59 participants
300 discussions

Re: [coreboot] Warnings
by Nils 09 May '10

09 May '10

Op zondag 9 mei 2010 00:36:49 schreef u: > On 5/1/10 1:34 AM, Nils wrote: > > Hi Stefan, > > First of all thanks for the great improvements in Geode (GX2). > > > > On 4/30/10 7:50 PM, Stefan Reinauer wrote: > >> src/northbridge/amd/gx2/chipsetinit.c:271: warning: suggest > >> parentheses around '-' inside '<<' > > > > This would need help from someone with a GX2 (or willing to check out > > the data sheets ;-) > > > > I would be happy if i could be of any help with this, I have a GX2 board > > i can test on. > > Can you test the following two patches: > > Index: northbridge/amd/gx2/chipsetinit.c > =================================================================== > --- northbridge/amd/gx2/chipsetinit.c (revision 5532) > +++ northbridge/amd/gx2/chipsetinit.c (working copy) > @@ -268,7 +268,7 @@ > if ((msr.lo&0xff) == 0x11) > return; > > - totalmem = sizeram() << 20 - 1; > + totalmem = (sizeram() << 20) - 1; > totalmem >>= 12; > totalmem = ~totalmem; > totalmem &= 0xfffff; > > > and this one > > Index: northbridge/amd/gx2/chipsetinit.c > =================================================================== > --- northbridge/amd/gx2/chipsetinit.c (revision 5532) > +++ northbridge/amd/gx2/chipsetinit.c (working copy) > @@ -268,7 +268,7 @@ > if ((msr.lo&0xff) == 0x11) > return; > > - totalmem = sizeram() << 20 - 1; > + totalmem = sizeram() << (20 - 1); > totalmem >>= 12; > totalmem = ~totalmem; > totalmem &= 0xfffff; > > > and see if any of them causes a failure? > > It would seem the first patch is correct and the second is not, but i am > not sure. > > > I saw your discussion about the warning before and it inspired me to > > dedicate my spare free time to again update my working rev5446 patches to > > current trunk. > > But unfortunately i can`t get it to work anymore on rev5120 and some > > other rev`s i tried. > > (Linux errors out with: "hda: lost interrupt") > > I will send the details in a separate mail. > > We do need to make sure we know the exact revision that broke this. > > Stefan > Yes, i wil test that next time i find some time for hobby, now i`m of to bed. On what revision would you like me to test? Nils.

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Re: [coreboot] [PATCH] improve realmode api
by Nils 09 May '10

09 May '10

Hi Stefan, After trying all VSA`s i could find on the net back in last December, no one was working. So i hacked up my own. Attached a log from rev5470. Thanks,Nils.

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Re: [coreboot] [commit] r5533 - in trunk/src/mainboard: . wyse wyse/s50
by Nils 09 May '10

09 May '10

>Author: stepan >Date: Sat May 8 23:50:31 2010 >New Revision: 5533 >URL: https://tracker.coreboot.org/trac/coreboot/changeset/5533 >Log: >Add the Wyse S50 thin client to Coreboot. Thanks for committing my board. Now i don`t have to hand adjust my patches for every revision. Since this patchset i have changed the memmory region setup to match the LX boards. I wil send a patch for that later. Thanks,Nils.

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Re: [coreboot] #18: autoprobe apic cluster and application processors on K8 systems
by coreboot 09 May '10

09 May '10

#18: autoprobe apic cluster and application processors on K8 systems -------------------------+-------------------------------------------------- Reporter: stepan | Owner: oxygene Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Keywords: K8, cleanup Dependencies: | Patchstatus: patch needs review -------------------------+-------------------------------------------------- Comment(by stepan): cleanup-lapics.diff applied as r5534. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/18#comment:6> coreboot <http://www.coreboot.org/>

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Re: [coreboot] GX2 problems
by Nils 09 May '10

09 May '10

Op zondag 9 mei 2010 00:00:22 schreef u: x0000FFFFFFFF0000ULL; // Enable reads for C0000-FFFFF > > setShadow(shadowSettings); > > } > > What's this doing? > > Is it potentially dangerous for other systems? > I was strugling with memory regions and saw this in the LX code.

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[commit] r5534 - in trunk/src/mainboard: arima/hdama ibm/e325 iwill/dk8s2 iwill/dk8x newisys/khepri
by repository service 09 May '10

09 May '10

Author: stepan Date: Sun May 9 00:02:54 2010 New Revision: 5534 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5534 Log: autoprobe apic cluster and application processors on K8 systems (fixes #18) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/arima/hdama/devicetree.cb trunk/src/mainboard/ibm/e325/devicetree.cb trunk/src/mainboard/iwill/dk8s2/devicetree.cb trunk/src/mainboard/iwill/dk8x/devicetree.cb trunk/src/mainboard/newisys/khepri/devicetree.cb Modified: trunk/src/mainboard/arima/hdama/devicetree.cb ============================================================================== --- trunk/src/mainboard/arima/hdama/devicetree.cb Sat May 8 23:50:31 2010 (r5533) +++ trunk/src/mainboard/arima/hdama/devicetree.cb Sun May 9 00:02:54 2010 (r5534) @@ -180,14 +180,6 @@ device pci 18.2 on end device pci 18.3 on end end # chip northbridge/amd/amdk8 - chip northbridge/amd/amdk8 - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end end end Modified: trunk/src/mainboard/ibm/e325/devicetree.cb ============================================================================== --- trunk/src/mainboard/ibm/e325/devicetree.cb Sat May 8 23:50:31 2010 (r5533) +++ trunk/src/mainboard/ibm/e325/devicetree.cb Sun May 9 00:02:54 2010 (r5534) @@ -1,4 +1,9 @@ chip northbridge/amd/amdk8/root_complex + device lapic_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on end # LDT 0 @@ -60,22 +65,6 @@ device pci 18.2 on end device pci 18.3 on end end - chip northbridge/amd/amdk8 - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - end - device lapic_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - chip cpu/amd/socket_940 - device lapic 1 on end - end end end Modified: trunk/src/mainboard/iwill/dk8s2/devicetree.cb ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/devicetree.cb Sat May 8 23:50:31 2010 (r5533) +++ trunk/src/mainboard/iwill/dk8s2/devicetree.cb Sun May 9 00:02:54 2010 (r5534) @@ -1,4 +1,9 @@ chip northbridge/amd/amdk8/root_complex + device lapic_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # LDT 0 @@ -68,22 +73,6 @@ device pci 18.2 on end device pci 18.3 on end end - chip northbridge/amd/amdk8 - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - end - device lapic_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - chip cpu/amd/socket_940 - device lapic 1 on end - end end end Modified: trunk/src/mainboard/iwill/dk8x/devicetree.cb ============================================================================== --- trunk/src/mainboard/iwill/dk8x/devicetree.cb Sat May 8 23:50:31 2010 (r5533) +++ trunk/src/mainboard/iwill/dk8x/devicetree.cb Sun May 9 00:02:54 2010 (r5534) @@ -1,4 +1,9 @@ chip northbridge/amd/amdk8/root_complex + device lapic_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # northbridge @@ -47,22 +52,6 @@ device pci 18.2 on end device pci 18.3 on end end - chip northbridge/amd/amdk8 - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - end - device lapic_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - chip cpu/amd/socket_940 - device lapic 1 on end - end end end Modified: trunk/src/mainboard/newisys/khepri/devicetree.cb ============================================================================== --- trunk/src/mainboard/newisys/khepri/devicetree.cb Sat May 8 23:50:31 2010 (r5533) +++ trunk/src/mainboard/newisys/khepri/devicetree.cb Sun May 9 00:02:54 2010 (r5534) @@ -3,9 +3,6 @@ chip cpu/amd/socket_940 device lapic 0 on end end - chip cpu/amd/socket_940 - device lapic 1 on end - end end device pci_domain 0 on @@ -79,14 +76,6 @@ device pci 18.2 on end device pci 18.3 on end end - chip northbridge/amd/amdk8 - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end end end

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[commit] r5533 - in trunk/src/mainboard: . wyse wyse/s50
by repository service 09 May '10

09 May '10

Author: stepan Date: Sat May 8 23:50:31 2010 New Revision: 5533 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5533 Log: Add the Wyse S50 thin client to Coreboot. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/src/mainboard/wyse/ trunk/src/mainboard/wyse/Kconfig trunk/src/mainboard/wyse/s50/ trunk/src/mainboard/wyse/s50/Kconfig trunk/src/mainboard/wyse/s50/chip.h trunk/src/mainboard/wyse/s50/cmos.layout trunk/src/mainboard/wyse/s50/devicetree.cb trunk/src/mainboard/wyse/s50/irq_tables.c trunk/src/mainboard/wyse/s50/mainboard.c trunk/src/mainboard/wyse/s50/romstage.c Modified: trunk/src/mainboard/Kconfig Modified: trunk/src/mainboard/Kconfig ============================================================================== --- trunk/src/mainboard/Kconfig Sat May 8 20:14:50 2010 (r5532) +++ trunk/src/mainboard/Kconfig Sat May 8 23:50:31 2010 (r5533) @@ -100,6 +100,8 @@ bool "VIA" config VENDOR_WINENT bool "Win Enterprises" +config VENDOR_WYSE + bool "Wyse" endchoice @@ -373,6 +375,16 @@ default "Win Enterprise" depends on VENDOR_WINENT +config MAINBOARD_VENDOR + string + default "Wyse" + depends on VENDOR_WYSE + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x102d + depends on VENDOR_WYSE + source "src/mainboard/a-trend/Kconfig" source "src/mainboard/abit/Kconfig" source "src/mainboard/advantech/Kconfig" @@ -421,6 +433,7 @@ source "src/mainboard/tyan/Kconfig" source "src/mainboard/via/Kconfig" source "src/mainboard/winent/Kconfig" +source "src/mainboard/wyse/Kconfig" config BOARD_ROMSIZE_KB_128 bool Added: trunk/src/mainboard/wyse/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/wyse/Kconfig Sat May 8 23:50:31 2010 (r5533) @@ -0,0 +1,8 @@ +choice + prompt "Mainboard model" + depends on VENDOR_WYSE + +source "src/mainboard/wyse/s50/Kconfig" + +endchoice + Added: trunk/src/mainboard/wyse/s50/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/wyse/s50/Kconfig Sat May 8 23:50:31 2010 (r5533) @@ -0,0 +1,51 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_WYSE_S50 + bool "S50" + select ARCH_X86 + select CPU_AMD_GX2 + select NORTHBRIDGE_AMD_GX2 + select SOUTHBRIDGE_AMD_CS5536 + select ROMCC + select UDELAY_TSC + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select BOARD_ROMSIZE_KB_256 + +config MAINBOARD_DIR + string + default wyse/s50 + depends on BOARD_WYSE_S50 + +config MAINBOARD_PART_NUMBER + string + default "s50" + depends on BOARD_WYSE_S50 + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_WYSE_S50 + +config IRQ_SLOT_COUNT + int + default 3 + depends on BOARD_WYSE_S50 Added: trunk/src/mainboard/wyse/s50/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/wyse/s50/chip.h Sat May 8 23:50:31 2010 (r5533) @@ -0,0 +1,5 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config { + int nicirq; +}; Added: trunk/src/mainboard/wyse/s50/cmos.layout ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/wyse/s50/cmos.layout Sat May 8 23:50:31 2010 (r5533) @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + Added: trunk/src/mainboard/wyse/s50/devicetree.cb ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/wyse/s50/devicetree.cb Sat May 8 23:50:31 2010 (r5533) @@ -0,0 +1,32 @@ +chip northbridge/amd/gx2 + register "irqmap" = "0xaa5b" + register "setupflash" = "0" + device lapic_cluster 0 on + chip cpu/amd/model_gx2 + device lapic 0 on end + end + end + device pci_domain 0 on + device pci 1.0 on end + device pci 1.1 on end + chip southbridge/amd/cs5536 + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" #0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "1" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + device pci e.0 on end # Realtek 8139 LAN + device pci f.0 on end # ISA Bridge + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end +end + Added: trunk/src/mainboard/wyse/s50/irq_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/wyse/s50/irq_tables.c Sat May 8 23:50:31 2010 (r5533) @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 200x TODO <TODO@TODO> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x0f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x100b, /* Vendor */ + 0x2b, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xdc, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x0f << 3) | 0x0, {{0x01, 0x0800}, {0x02, 0x0020}, {0x03, 0x0400}, {0x04, 0x0400}}, 0x5, 0x0}, + {0x00, (0x0d << 3) | 0x0, {{0x04, 0x0400}, {0x03, 0x0400}, {0x02, 0x0020}, {0x01, 0x0800}}, 0x1, 0x0}, + {0x00, (0x0e << 3) | 0x0, {{0x01, 0x0800}, {0x02, 0x0020}, {0x03, 0x0400}, {0x04, 0x0400}}, 0x2, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/src/mainboard/wyse/s50/mainboard.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/wyse/s50/mainboard.c Sat May 8 23:50:31 2010 (r5533) @@ -0,0 +1,12 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("WYSE S50 Mainboard") +}; + Added: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/wyse/s50/romstage.c Sat May 8 23:50:31 2010 (r5533) @@ -0,0 +1,167 @@ +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include <console/console.h> +#include "lib/ramtest.c" +#include "cpu/x86/bist.h" +#include "cpu/x86/msr.h" +#include <cpu/amd/gx2def.h> + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +#include "southbridge/amd/cs5536/cs5536_early_smbus.c" +#include "southbridge/amd/cs5536/cs5536_early_setup.c" + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/gx2/raminit.h" + +static inline unsigned int ctz(unsigned int n) +{ + int zeros; + + n = (n ^ (n - 1)) >> 1; + for (zeros = 0; n; zeros++) + { + n >>= 1; + } + return zeros; +} + +static void sdram_set_spd_registers(const struct mem_controller *ctrl) +{ + /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * + * component Banks (byte 17) * module banks, side (byte 5) * + * width in bits (byte 6,7) + * = Density per side (byte 31) * number of sides (byte 5) */ + /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */ + msr_t msr; + unsigned char module_banks, val; + uint16_t dimm_size; + + msr = rdmsr(MC_CF07_DATA); + + /* get module banks (sides) per dimm, SPD byte 5 */ + module_banks = spd_read_byte(0xA0, 5); + if (module_banks < 1 || module_banks > 2) + print_err("Module banks per dimm\n"); + module_banks >>= 1; + msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT); + msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT); + + /* get component banks per module bank, SPD byte 17 */ + val = spd_read_byte(0xA0, 17); + if (val < 2 || val > 4) + print_err("Component banks per module bank\n"); + val >>= 2; + msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT); + msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT); + + dimm_size = spd_read_byte(0xA0, 31); + dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */ + dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */ + /* Module Density * Module Banks */ + dimm_size <<= (0 >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */ + if (dimm_size != 0) { + dimm_size = ctz(dimm_size); + } + if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */ + print_err("Only support up to 512MB \n"); + hlt(); + } + msr.hi |= dimm_size << CF07_UPPER_D0_SZ_SHIFT; + + /* page size = 2^col address */ + val = spd_read_byte(0xA0, 4); + val -= 7; + msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT); + msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT); + + print_debug("computed msr.hi "); + print_debug_hex32(msr.hi); + print_debug("\n"); + + msr.lo = 0x00003400; + wrmsr(MC_CF07_DATA, msr); + + msr = rdmsr(MC_CF8F_DATA); + msr.hi = 0x18000008; + msr.lo = 0x296332a3; + wrmsr(MC_CF8F_DATA, msr); + +} + +#include "northbridge/amd/gx2/raminit.c" +#include "lib/generic_sdram.c" + +#include "northbridge/amd/gx2/pll_reset.c" +#include "cpu/amd/model_gx2/cpureginit.c" +#include "cpu/amd/model_gx2/syspreinit.c" + +static void msr_init(void) +{ + /* total physical memory */ + __builtin_wrmsr(0x1808, 0x11f6bf00, 0x21c00002); + + /* traditional memory 0kB-512kB, 512kB-1MB */ + __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); + __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); + __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2dfbc040); + __builtin_wrmsr(0x10000028, 0x6bf00100, 0x2000001f); + __builtin_wrmsr(0x1000002c, 0xffff0003, 0x2000ffff); + + __builtin_wrmsr(0x10000080, 0x3, 0x0); + + __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); + __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); + __builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040); + __builtin_wrmsr(0x40000029, 0x6bf00100, 0x2000001f); + __builtin_wrmsr(0x4000002d, 0xffff0003, 0x2000ffff); + + __builtin_wrmsr(0x40000080, 0x1, 0x0); + + __builtin_wrmsr(0x50002001, 0x27, 0x0); + __builtin_wrmsr(0x4c002001, 0x1, 0x0); + + /* put code in northbridge[init].c here */ +} + +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl [] = { + {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* disable the power button */ + outl(0x00, PMS_IO_BASE + 0x40); + + cs5536_setup_onchipuart(1); + + uart_init(); + console_init(); + + pll_reset(); + + cpuRegInit(); + print_err("done cpuRegInit\n"); + + sdram_initialize(1, memctrl); + print_err("ram setup done\n"); + + /* Check all of memory */ + /*ram_check(0x00000000, 640*1024);*/ + print_err("ram check done\n"); +} +

2 2

Re: [coreboot] [PATCH] improve realmode api
by Nils 08 May '10

08 May '10

Hi, During my investigations i found this Geode GX2 hardware bug discription, could that have anything to do with my problems? Thanks,Nils. AMD Geode™ GX Processors Silicon Revision 2.1 Specification Update: 1.15 Limit fault during exception in SMM with unreal code segment Description: When an exception or other interseg- ment change of flow (COF) occurs inside an SMI handler and the target offset is higher than the SMI handler's code segment (CS) limit, a spurious general protection fault for a segment limit violation may occur. The CS limit, normally FFFFh in real mode, can be set to a smaller value inside SMM with RSM or with an MSR write. When fetching the first instruction of an exception handler, or the target of a far jump, the CPU mistakenly uses that shortened CS limit instead of the implicit limit of FFFFh that would normally apply to a real mode code segment. This leads to an erroneous general protection excep- tion. Implications: Exceptions may generate a limit fault when a COF occurs while in SMM. Resolution: Leave the SMM's code segment limit at FFFFh, or put any SMM exception handlers and intersegment COF targets lower in their segment, at offsets that are less than the SMM CS limit.

1 0

Re: [coreboot] [PATCH] improve realmode api
by Nils 08 May '10

08 May '10

Hi Stefan, I tested your patch in the hope that my Geode GX2 board started to work again. Unfortunatly it doesn`t. My board stopped working after your vsm loading patches in rev5471. The error after rev5471 was "hda: lost interrupt" . Now after rev5532 with your improve realmode api patch the board oopses. I will not ack nor nack because i know to little about programming. Thanks,Nils. Last part of rev5532 + improve realmode api patch: sizeram: sizem 0x200 setup_gx2_cache: enable for 524288 KB msr 0x00001808 will be set to 25fff002:11ffe000 MSR 0x10000026 is now 0x2dfbe040:0x400fffe0 Preparing for VSA... VSA: Real mode stub @00000600: 628 bytes Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff00000 + 38 + 79ab + align -> fff07a00 Check fallback/payload CBFS: follow chain: fff07a00 + 38 + 11038 + align -> fff18a80 Check vsa Stage: loading vsa @ 0x60000 (57868 bytes), entry @ 0x60020 Stage: done loading. VSA: Buffer @00060000 *[0k]=ba VSA: Signature *[0x20-0x23] is b0:10:e6:80 Calling VSA module... oprom: INT# 0xd oprom: eax: 11ffe000 ebx: 80007800 ecx: 00001012 edx: 25fff002 oprom: ebp: 00000ff4 esp: 00000fec edi: 0000102d esi: 00000028 oprom: ip: 0647 cs: 6000 flags: 00000013 Oops, exception 13 while executing option rom Unexpected Exception: 13 @ 6000:00000647 - Halting Code: 0 eflags: 00000013 eax: 11ffe000 ebx: 80007800 ecx: 00001012 edx: 25fff002 edi: 0000102d esi: 00000028 ebp: 00000ff4 esp: 00000fec

2 1

[PATCH] improve realmode api
by Stefan Reinauer 08 May '10

08 May '10

See patch

1 0

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coreboot May 2010