coreboot May 2010

coreboot@coreboot.org

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Preview: SECC Pentium 2/3 users are gonna love this
by Keith Hui 12 May '10

12 May '10

See this boot log: http://coreboot.pastebin.com/rdmwwvha I have done the 72oz steak ;-P that is porting the L2 enabling code from coreboot v1 to current trunk, made much slimmer by being able to put it post-raminit. The CPU in question is a Pentium III 600MHz, Katmai core, 512KB cache. Tell me if I am headed the right direction. Patch to come soonish. Enjoy Keith PS. Oh by the way... [root@ojisan ~]# cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 7 model name : Pentium III (Katmai) stepping : 3 cpu MHz : 601.352 cache size : 512 KB fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 2 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov pse36 mmx fxsr sse up bogomips : 1202.70 clflush size : 32 power management: [root@ojisan ~]#

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[PATCH] Wyse S50 cleanup
by Nils 12 May '10

12 May '10

This patch cleanes up the Wyse S50 port and unifies the memmory regions with Geode LX , adds gpl2 headers plus some white space fixes. This is build and boot tested.(of course vsa loading is stil not fixed,it now runs forever with :"Oops, exception 13 while executing option rom") Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Hi Stefan, I hope this is what you had in mind regarding the GPLv2 headers? Thanks,Nils.

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Indtast Bcc Preview: SECC Pentium 2/3 users are gonna love this
by anders＠jenbo.dk 12 May '10

12 May '10

Yay this is just what I have been hoping for. Mvh Anders ----- Reply message ----- Fra: "Keith Hui" <buurin(a)gmail.com> Dato: ons., maj 12, 2010 03:53 Emne: [coreboot] Preview: SECC Pentium 2/3 users are gonna love this Til: <coreboot(a)coreboot.org> See this boot log: http://coreboot.pastebin.com/rdmwwvha I have done the 72oz steak ;-P that is porting the L2 enabling code from coreboot v1 to current trunk, made much slimmer by being able to put it post-raminit. The CPU in question is a Pentium III 600MHz, Katmai core, 512KB cache. Tell me if I am headed the right direction. Patch to come soonish. Enjoy Keith PS. Oh by the way... [root@ojisan ~]# cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 7 model name : Pentium III (Katmai) stepping : 3 cpu MHz : 601.352 cache size : 512 KB fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 2 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov pse36 mmx fxsr sse up bogomips : 1202.70 clflush size : 32 power management: [root@ojisan ~]# -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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GX2 problems
by Nils 11 May '10

11 May '10

Hi all, Attached patches add the Wyse S50 thin client to Coreboot. I have rev5446 and some older rev`s working here with different hacks but rev5484 and 5520 (and some i tested in between) are not working anymore. Linux gives the following error: "hda: lost interrupt" . Attached also the bootlogs from rev5446 and rev5520. Could somebody give me a hint (or even better a patch) i can try? Although the patches are probably not ready for inclusion: Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Thanks,Nils.

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[PATCH] h8dme-2: fix most remaining compile-time warnings
by Joe Korty 11 May '10

11 May '10

Clean up some h8dme-2 warnings. Eliminate those warnings in the supermicro h8dme-2 build that are due to the header file w83627hf.h being included multiple times. Signed-off-by: Joe Korty <joe.korty(a)ccur.com> Index: trunk/src/superio/winbond/w83627hf/w83627hf.h =================================================================== --- trunk.orig/src/superio/winbond/w83627hf/w83627hf.h 2010-05-11 07:00:24.000000000 -0400 +++ trunk/src/superio/winbond/w83627hf/w83627hf.h 2010-05-11 13:06:19.000000000 -0400 @@ -20,6 +20,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef __W83627HF_H +#define __W83627HF_H + #define W83627HF_FDC 0 /* Floppy */ #define W83627HF_PP 1 /* Parallel Port */ #define W83627HF_SP1 2 /* Com1 */ @@ -117,3 +120,4 @@ void w83627hf_set_clksel_48(device_t dev); #endif +#endif /* __W83627HF_H */

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[commit] r5543 - in trunk/src: devices/oprom northbridge/via/cx700 northbridge/via/vt8623 northbridge/via/vx800
by repository service 11 May '10

11 May '10

Author: stepan Date: Tue May 11 17:39:20 2010 New Revision: 5543 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5543 Log: Change real mode API to allow passing intXX number or entry point and some register values from C. This theoretically fixes non-vga option roms, but it also allows to use the same assembler code for option roms and vsm. It will also make using the bootsplash without yabel a lot easier. Factor out and improve BDA setup, do some rom segment setup for those option roms that need it. Don't call the coreboot exception handler if an exception occurs in real mode. It's only partly usable, but mainly the Kontron 986LCD-M (and other i945GM boards) choke on an exception #6 (invalid opcode). This particular issue is not introduced by the changes in this patch but has been around for quite a while at least. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/devices/oprom/x86.c trunk/src/devices/oprom/x86_asm.S trunk/src/northbridge/via/cx700/cx700_vga.c trunk/src/northbridge/via/cx700/northbridge.h trunk/src/northbridge/via/vt8623/northbridge.h trunk/src/northbridge/via/vt8623/vga.c trunk/src/northbridge/via/vx800/northbridge.h trunk/src/northbridge/via/vx800/vga.c Modified: trunk/src/devices/oprom/x86.c ============================================================================== --- trunk/src/devices/oprom/x86.c Mon May 10 21:45:45 2010 (r5542) +++ trunk/src/devices/oprom/x86.c Tue May 11 17:39:20 2010 (r5543) @@ -34,12 +34,45 @@ void x86_exception(struct eregs *info); +/* From x86_asm.S */ extern unsigned char __idt_handler, __idt_handler_size; extern unsigned char __realmode_code, __realmode_code_size; -extern unsigned char __run_optionrom, __run_interrupt; +extern unsigned char __realmode_call, __realmode_interrupt; -void (*run_optionrom)(u32 devfn) __attribute__((regparm(0))) = (void *)&__run_optionrom; -void (*vga_enable_console)(void) __attribute__((regparm(0))) = (void *)&__run_interrupt; +void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_call; + +void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_interrupt; + +#define FAKE_MEMORY_SIZE (1024*1024) // only 1MB +#define INITIAL_EBDA_SEGMENT 0xF600 +#define INITIAL_EBDA_SIZE 0x400 + +static void setup_bda(void) +{ + /* clear BIOS DATA AREA */ + memset((void *)0x400, 0, 0x200); + + write16(0x413, FAKE_MEMORY_SIZE / 1024); + write16(0x40e, INITIAL_EBDA_SEGMENT); + + /* Set up EBDA */ + memset((void *)(INITIAL_EBDA_SEGMENT << 4), 0, INITIAL_EBDA_SIZE); + write16((INITIAL_EBDA_SEGMENT << 4) + 0x0, INITIAL_EBDA_SIZE / 1024); +} + +static void setup_rombios(void) +{ + const char date[] = "06/11/99"; + memcpy((void *)0xffff5, &date, 8); + + const char ident[] = "PCI_ISA"; + memcpy((void *)0xfffd9, &ident, 7); + + /* system model: IBM-AT */ + write8(0xffffe, 0xfc); +} int (*intXX_handler[256])(struct eregs *regs) = { NULL }; @@ -47,7 +80,12 @@ { printk(BIOS_INFO, "Oops, exception %d while executing option rom\n", regs->vector); +#if 0 + // Odd: The i945GM VGA oprom chokes on a pushl %eax and will + // die with an exception #6 if we run the coreboot exception + // handler. Just continue, as it executes fine. x86_exception(regs); // Call coreboot exception handler +#endif return 0; // Never returns? } @@ -138,20 +176,38 @@ /* int42 is the relocated int10 */ write_idt_stub((void *)0xff065, 0x42); - - /* VIA's VBIOS calls f000:f859 instead of int15 */ + /* BIOS Int 11 Handler F000:F84D */ + write_idt_stub((void *)0xff84d, 0x11); + /* BIOS Int 12 Handler F000:F841 */ + write_idt_stub((void *)0xff841, 0x12); + /* BIOS Int 13 Handler F000:EC59 */ + write_idt_stub((void *)0xfec59, 0x13); + /* BIOS Int 14 Handler F000:E739 */ + write_idt_stub((void *)0xfe739, 0x14); + /* BIOS Int 15 Handler F000:F859 */ write_idt_stub((void *)0xff859, 0x15); + /* BIOS Int 16 Handler F000:E82E */ + write_idt_stub((void *)0xfe82e, 0x16); + /* BIOS Int 17 Handler F000:EFD2 */ + write_idt_stub((void *)0xfefd2, 0x17); + /* ROM BIOS Int 1A Handler F000:FE6E */ + write_idt_stub((void *)0xffe6e, 0x1a); } void run_bios(struct device *dev, unsigned long addr) { - /* clear vga bios data area */ - memset((void *)0x400, 0, 0x200); + u32 num_dev = (dev->bus->secondary << 8) | dev->path.pci.devfn; + + /* Set up BIOS Data Area */ + setup_bda(); + + /* Set up some legacy information in the F segment */ + setup_rombios(); /* Set up C interrupt handlers */ setup_interrupt_handlers(); - /* Setting up realmode IDT */ + /* Set up real-mode IDT */ setup_realmode_idt(); memcpy(REALMODE_BASE, &__realmode_code, (size_t)&__realmode_code_size); @@ -159,7 +215,9 @@ (u32)&__realmode_code_size); printk(BIOS_DEBUG, "Calling Option ROM...\n"); - run_optionrom((dev->bus->secondary << 8) | dev->path.pci.devfn); + /* TODO ES:DI Pointer to System BIOS PnP Installation Check Structure */ + /* Option ROM entry point is at OPROM start + 3 */ + realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, 0x0); printk(BIOS_DEBUG, "... Option ROM returned.\n"); } @@ -168,9 +226,6 @@ #include <cpu/amd/vr.h> #include <cbfs.h> -extern unsigned char __run_vsa; -void (*run_vsa)(u32 smm, u32 sysmem) __attribute__((regparm(0))) = (void *)&__run_vsa; - #define VSA2_BUFFER 0x60000 #define VSA2_ENTRY_POINT 0x60020 @@ -198,9 +253,6 @@ { printk(BIOS_DEBUG, "Preparing for VSA...\n"); - /* clear bios data area */ - memset((void *)0x400, 0, 0x200); - /* Set up C interrupt handlers */ setup_interrupt_handlers(); @@ -229,8 +281,11 @@ } printk(BIOS_DEBUG, "Calling VSA module...\n"); + /* ECX gets SMM, EDX gets SYSMEM */ - run_vsa(MSR_GLIU0_SMM, MSR_GLIU0_SYSMEM); + realmode_call(VSA2_ENTRY_POINT, 0x0, 0x0, MSR_GLIU0_SMM, + MSR_GLIU0_SYSMEM, 0x0, 0x0); + printk(BIOS_DEBUG, "... VSA module returned.\n"); /* Restart timer 1 */ Modified: trunk/src/devices/oprom/x86_asm.S ============================================================================== --- trunk/src/devices/oprom/x86_asm.S Mon May 10 21:45:45 2010 (r5542) +++ trunk/src/devices/oprom/x86_asm.S Tue May 11 17:39:20 2010 (r5543) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2009-2010 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -57,21 +57,49 @@ __stack = RELOCATED(.) .long 0 +/* Register store for realmode_call and realmode_interrupt */ +__registers = RELOCATED(.) + .long 0 /* 0x00 - EAX */ + .long 0 /* 0x04 - EBX */ + .long 0 /* 0x08 - ECX */ + .long 0 /* 0x0c - EDX */ + .long 0 /* 0x10 - EDI */ + .long 0 /* 0x14 - ESI */ + .code32 - .globl __run_optionrom -__run_optionrom = RELOCATED(.) + .globl __realmode_call +__realmode_call = RELOCATED(.) /* save all registers to the stack */ pushal /* Move the protected mode stack to a safe place */ - mov %esp, __stack - - /* Get devfn into %ecx */ + movl %esp, __stack movl %esp, %ebp + /* This function is called with regparm=0 and we have - * to skip the 32 byte from pushal: + * to skip the 32 byte from pushal. Hence start at 36. */ - movl 36(%ebp), %ecx + + /* entry point */ + movl 36(%ebp), %eax + movw %ax, __lcall_instr + 1 + andl $0xffff0000, %eax + shrl $4, %eax + movw %ax, __lcall_instr + 3 + + /* initial register values */ + movl 40(%ebp), %eax + movl %eax, __registers + 0x00 /* eax */ + movl 44(%ebp), %eax + movl %eax, __registers + 0x04 /* ebx */ + movl 48(%ebp), %eax + movl %eax, __registers + 0x08 /* ecx */ + movl 52(%ebp), %eax + movl %eax, __registers + 0x0c /* edx */ + movl 56(%ebp), %eax + movl %eax, __registers + 0x10 /* esi */ + movl 60(%ebp), %eax + movl %eax, __registers + 0x14 /* esi */ /* Activate the right segment descriptor real mode. */ ljmp $0x28, $RELOCATED(1f) @@ -120,11 +148,18 @@ mov $0x40, %ax mov %ax, %ds + /* initialize registers for option rom lcall */ + movl __registers + 0, %eax + movl __registers + 4, %ebx + movl __registers + 8, %ecx + movl __registers + 12, %edx + movl __registers + 16, %esi + movl __registers + 20, %edi + /* ************************************ */ - mov %cx, %ax // restore ax - // TODO this will not work for non-VGA option ROMs - /* run VGA BIOS at 0xc000:0003 */ - lcall $0xc000, $0x0003 +__lcall_instr = RELOCATED(.) + .byte 0x9a + .word 0x0000, 0x0000 /* ************************************ */ /* If we got here, just about done. @@ -151,126 +186,47 @@ lidt idtarg /* and exit */ - mov __stack, %esp + movl __stack, %esp popal - ret -#if defined(CONFIG_GEODE_VSA) && CONFIG_GEODE_VSA -#define VSA2_ENTRY_POINT 0x60020 + // TODO return AX from OPROM call + ret - .globl __run_vsa -__run_vsa = RELOCATED(.) + .globl __realmode_interrupt +__realmode_interrupt = RELOCATED(.) /* save all registers to the stack */ pushal - - /* Move the protected mode stack to a safe place */ - mov %esp, __stack - + /* save the stack */ + movl %esp, __stack movl %esp, %ebp - /* This function is called with regparm=0 and we have - * to skip the 32 byte from pushal: - */ - movl 36(%ebp), %ecx - movl 40(%ebp), %edx - - /* Activate the right segment descriptor real mode. */ - ljmp $0x28, $RELOCATED(1f) -1: -.code16 - /* 16 bit code from here on... */ - - /* Load the segment registers w/ properly configured - * segment descriptors. They will retain these - * configurations (limits, writability, etc.) once - * protected mode is turned off. - */ - mov $0x30, %ax - mov %ax, %ds - mov %ax, %es - mov %ax, %fs - mov %ax, %gs - mov %ax, %ss - - /* Turn off protection */ - movl %cr0, %eax - andl $~PE, %eax - movl %eax, %cr0 - - /* Now really going into real mode */ - ljmp $0, $RELOCATED(1f) -1: - /* Setup a stack: Put the stack at the end of page zero. - * That way we can easily share it between real and - * protected, since the 16 bit ESP at segment 0 will - * work for any case. */ - mov $0x0, %ax - mov %ax, %ss - movl $0x1000, %eax - movl %eax, %esp - /* Load our 16 bit idt */ - xor %ax, %ax - mov %ax, %ds - lidt __realmode_idt - - /* Set all segments to 0x0000, ds to 0x0040 */ - mov %ax, %es - mov %ax, %fs - mov %ax, %gs - mov $0x40, %ax - mov %ax, %ds - mov %cx, %ax // restore ax - - /* ************************************ */ - lcall $((VSA2_ENTRY_POINT & 0xffff0000) >> 4), $(VSA2_ENTRY_POINT & 0xffff) - /* ************************************ */ - - /* If we got here, just about done. - * Need to get back to protected mode + /* This function is called with regparm=0 and we have + * to skip the 32 byte from pushal. Hence start at 36. */ - movl %cr0, %eax - orl $PE, %eax - movl %eax, %cr0 - - /* Now that we are in protected mode - * jump to a 32 bit code segment. - */ - data32 ljmp $0x10, $RELOCATED(1f) -1: - .code32 - movw $0x18, %ax - mov %ax, %ds - mov %ax, %es - mov %ax, %fs - mov %ax, %gs - mov %ax, %ss - - /* restore proper idt */ - lidt idtarg - - /* and exit */ - mov __stack, %esp - popal - ret -#endif - - .globl __run_interrupt -__run_interrupt = RELOCATED(.) - - pushal - /* save the stack */ - mov %esp, __stack + /* prepare interrupt calling code */ + movl 36(%ebp), %eax + movb %al, __intXX_instr + 1 /* intno */ + + /* initial register values */ + movl 40(%ebp), %eax + movl %eax, __registers + 0x00 /* eax */ + movl 44(%ebp), %eax + movl %eax, __registers + 0x04 /* ebx */ + movl 48(%ebp), %eax + movl %eax, __registers + 0x08 /* ecx */ + movl 52(%ebp), %eax + movl %eax, __registers + 0x0c /* edx */ + movl 56(%ebp), %eax + movl %eax, __registers + 0x10 /* esi */ + movl 60(%ebp), %eax + movl %eax, __registers + 0x14 /* esi */ /* This configures CS properly for real mode. */ ljmp $0x28, $RELOCATED(1f) 1: .code16 /* 16 bit code from here on... */ - // DEBUG - movb $0xec, %al - outb %al, $0x80 - /* Load the segment registers w/ properly configured segment * descriptors. They will retain these configurations (limits, * writability, etc.) once protected mode is turned off. @@ -291,9 +247,9 @@ data32 ljmp $0, $RELOCATED(1f) 1: - /* put the stack at the end of page zero. - * that way we can easily share it between real and protected, - * since the 16-bit ESP at segment 0 will work for any case. + /* put the stack at the end of page zero. That way we can easily + * share it between real mode and protected mode, because %esp and + * %ss:%sp point to the same memory. */ /* setup a stack */ mov $0x0, %ax @@ -312,18 +268,16 @@ mov %ax, %fs mov %ax, %gs - /* Call VGA BIOS int10 function 0x4f14 to enable main console - * Epia-M does not always autosence the main console so forcing - * it on is good. - */ + /* initialize registers for intXX call */ + movl __registers + 0, %eax + movl __registers + 4, %ebx + movl __registers + 8, %ecx + movl __registers + 12, %edx + movl __registers + 16, %esi + movl __registers + 20, %edi - /* Ask VGA option rom to enable main console */ - movw $0x4f14,%ax - movw $0x8003,%bx - movw $1, %cx - movw $0, %dx - movw $0, %di - int $0x10 +__intXX_instr = RELOCATED(.) + .byte 0xcd, 0x00 /* This becomes intXX */ /* Ok, the job is done, now go back to protected mode coreboot */ movl %cr0, %eax @@ -345,13 +299,15 @@ lidt idtarg /* Exit */ - mov __stack, %esp + movl __stack, %esp popal ret /* This is the 16-bit interrupt entry point called by the IDT stub code. + * * Before this code code is called, %eax is pushed to the stack, and the - * interrupt number is loaded into %al + * interrupt number is loaded into %al. On return this function cleans up + * for its caller. */ .code16 __interrupt_handler_16bit = RELOCATED(.) Modified: trunk/src/northbridge/via/cx700/cx700_vga.c ============================================================================== --- trunk/src/northbridge/via/cx700/cx700_vga.c Mon May 10 21:45:45 2010 (r5542) +++ trunk/src/northbridge/via/cx700/cx700_vga.c Tue May 11 17:39:20 2010 (r5543) @@ -144,6 +144,17 @@ } #endif +static void vga_enable_console(void) +{ + /* Call VGA BIOS int10 function 0x4f14 to enable main console + * Epia-M does not always autosense the main console so forcing + * it on is good. + */ + + /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ + realmode_interrupt(0x10, 0x4f1f, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); +} + static void vga_init(device_t dev) { u8 reg8; @@ -166,9 +177,6 @@ if (pci_read_config32(dev, PCI_ROM_ADDRESS) != 0xc0000) return; printk(BIOS_DEBUG, "Enable VGA console\n"); - // this is how it should look: - // call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); - // this is how it looks: vga_enable_console(); /* It's not clear if these need to be programmed before or after Modified: trunk/src/northbridge/via/cx700/northbridge.h ============================================================================== --- trunk/src/northbridge/via/cx700/northbridge.h Mon May 10 21:45:45 2010 (r5542) +++ trunk/src/northbridge/via/cx700/northbridge.h Tue May 11 17:39:20 2010 (r5543) @@ -21,6 +21,6 @@ #define NORTHBRIDGE_VIA_CX700_H extern unsigned int cx700_scan_root_bus(device_t root, unsigned int max); -extern void (*vga_enable_console)(void) __attribute__((regparm(0))); - +extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi) __attribute__((regparm(0))); #endif /* NORTHBRIDGE_VIA_CX700_H */ Modified: trunk/src/northbridge/via/vt8623/northbridge.h ============================================================================== --- trunk/src/northbridge/via/vt8623/northbridge.h Mon May 10 21:45:45 2010 (r5542) +++ trunk/src/northbridge/via/vt8623/northbridge.h Tue May 11 17:39:20 2010 (r5543) @@ -2,7 +2,7 @@ #define NORTHBRIDGE_VIA_VT8623_H unsigned int vt8623_scan_root_bus(device_t root, unsigned int max); -extern void (*vga_enable_console)(void) __attribute__((regparm(0))); -void write_protect_vgabios(void); +extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi) __attribute__((regparm(0))); #endif /* NORTHBRIDGE_VIA_VT8623_H */ Modified: trunk/src/northbridge/via/vt8623/vga.c ============================================================================== --- trunk/src/northbridge/via/vt8623/vga.c Mon May 10 21:45:45 2010 (r5542) +++ trunk/src/northbridge/via/vt8623/vga.c Tue May 11 17:39:20 2010 (r5543) @@ -72,7 +72,8 @@ return res; } -void write_protect_vgabios(void) +#ifdef UNUSED_CODE +static void write_protect_vgabios(void) { device_t dev; @@ -86,6 +87,7 @@ if (dev) pci_write_config8(dev, 0x61, 0xaa); } +#endif static void vga_random_fixup(device_t dev) { @@ -96,6 +98,17 @@ pci_write_config32(dev,0x14,0xdc000000); } +static void vga_enable_console(void) +{ + /* Call VGA BIOS int10 function 0x4f14 to enable main console + * Epia-M does not always autosense the main console so forcing + * it on is good. + */ + + /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ + realmode_interrupt(0x10, 0x4f1f, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); +} + static void vga_init(device_t dev) { vga_random_fixup(dev); @@ -118,9 +131,6 @@ pci_dev_init(dev); printk(BIOS_DEBUG, "Enable VGA console\n"); - // this is how it should look: - // call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); - // this is how it looks: vga_enable_console(); #ifdef MEASURE_VGA_INIT_TIME Modified: trunk/src/northbridge/via/vx800/northbridge.h ============================================================================== --- trunk/src/northbridge/via/vx800/northbridge.h Mon May 10 21:45:45 2010 (r5542) +++ trunk/src/northbridge/via/vx800/northbridge.h Tue May 11 17:39:20 2010 (r5543) @@ -21,6 +21,7 @@ #define NORTHBRIDGE_VIA_VX800_H extern unsigned int vx800_scan_root_bus(device_t root, unsigned int max); -extern void (*vga_enable_console)(void) __attribute__((regparm(0))); +extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi) __attribute__((regparm(0))); #endif /* NORTHBRIDGE_VIA_VX800_H */ Modified: trunk/src/northbridge/via/vx800/vga.c ============================================================================== --- trunk/src/northbridge/via/vx800/vga.c Mon May 10 21:45:45 2010 (r5542) +++ trunk/src/northbridge/via/vx800/vga.c Tue May 11 17:39:20 2010 (r5543) @@ -127,7 +127,7 @@ } #ifdef UNUSED_CODE -void write_protect_vgabios(void) +static void write_protect_vgabios(void) { device_t dev; @@ -144,6 +144,17 @@ } #endif +static void vga_enable_console(void) +{ + /* Call VGA BIOS int10 function 0x4f14 to enable main console + * Epia-M does not always autosense the main console so forcing + * it on is good. + */ + + /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ + realmode_interrupt(0x10, 0x4f1f, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); +} + extern u8 acpi_sleep_type; static void vga_init(device_t dev) { @@ -170,9 +181,6 @@ pci_dev_init(dev); printk(BIOS_DEBUG, "Enable VGA console\n"); - // this is how it should look: - // call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); - // this is how it looks: vga_enable_console(); if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/) {

1 0

[PATCH] improve realmode api
by Nils 11 May '10

11 May '10

I brought back the GX2 code in to the code at: svn://coreboot.org/vsa/trunk/gplvsa2 The biggest chunk of code doesn`t affect the LX code. The resulting LX image is binary compatible with the old one. But a few lines have to be selected for GX2 only. I wanted to invetigate how to do that and send a patch, but i haven`t had time. I am focusing on the board till now. Thanks,Nils.

4 3

Re: [coreboot] wyse s50
by Nils 10 May '10

10 May '10

Op zondag 9 mei 2010 14:42:54 schreef u: > hi Nils, > > could you please make a patch for your wyse s50 target that adds > - GPLv2 headers to all files > - adds your copyright to the files you created or changed (like > irq_tables.c) > > Sorry to ask for this late.. I guess I could add it, too, but it would > be nice if you'd find the time to create a patch as it's "your target" > now ;-) > > Anyways, thanks a lot for all your testing and work on coreboot. > > Stefan > Hi, As soon as i have some spare time i wil send a patch. I feel responsabel for "my target" ;-). Nils.

1 0

Indtast Bcc Re Dell Optiplex GX1 support
by anders＠jenbo.dk 10 May '10

10 May '10

It is strongly advanced that you find a way to recover the BIOS. Mvh Anders ----- Reply message ----- Fra: "Cooper Harrison" <coop.rocks.123e(a)gmail.com> Dato: man., maj 10, 2010 22:41 Emne: Re [coreboot] Dell Optiplex GX1 support Til: "Anders Jenbo" <anders(a)jenbo.dk> Cc: <coreboot(a)coreboot.org>

1 0

Re: [coreboot] Re Dell Optiplex GX1 support
by Anders Jenbo 10 May '10

10 May '10

To improve the support a bit navigate to coreboot/util/getpir/ and run make, then run ./getpir (on the GX1), this will generate a irq_tables.c file. Copy it to your folder, and add the following to the first section of your Kconfig. select HAVE_PIRQ_TABLE Once you have done this you should be ready to compile CoreBoot and flash it on to your board. If the flashing fails or the compiled ROM doesn't work for your board could be unable to boot, so it is strongly recommended that you find or buy a similar ROM chip so that you have a working backup in case something goes wrong. -Anders

3 2

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coreboot May 2010