coreboot May 2010

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How is the Status for 845 Chipset (Akimbo 1150 / Thomson IP1101) ?
by Carsten Müller 14 May '10

14 May '10

Hi, i know that someone is trying to get coreboot to run on the Akimbo 1150 STB with Intel 845 Chipset. I have a Thomson IP1101 which has the same board in it and i'd like to know if there is any news about runnin coreboot on this platform. Thanks! Carsten

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[commit] r5548 - in trunk/src: cpu/amd/car cpu/amd/model_10xxx cpu/amd/quadcore mainboard/amd/mahogany_fam10 mainboard/amd/serengeti_cheetah_fam10 mainboard/amd/tilapia_fam10 mainboard/msi/ms9652_f...
by repository service 14 May '10

14 May '10

Author: oxygene Date: Fri May 14 13:02:56 2010 New Revision: 5548 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5548 Log: Remove another set of includes from Fam10 romstages: northbridge/amd/amdht/ht_wrapper.c northbridge/amd/amdfam10/raminit_amdmct.c cpu/amd/model_10xxx/fidvid.c pc80/mc146818rtc_early.c They are now included by the fam10 chipset code that requires them. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c trunk/src/cpu/amd/model_10xxx/fidvid.c trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/quadcore/quadcore.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c trunk/src/northbridge/amd/amdht/h3gtopo.h Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c ============================================================================== --- trunk/src/cpu/amd/car/post_cache_as_ram.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/cpu/amd/car/post_cache_as_ram.c Fri May 14 13:02:56 2010 (r5548) @@ -3,7 +3,9 @@ */ #include <string.h> #include <arch/stages.h> +#include <cpu/x86/mtrr.h> #include "cpu/amd/car/disable_cache_as_ram.c" +#include "cpu/x86/mtrr/earlymtrr.c" static inline void print_debug_pcar(const char *strval, uint32_t val) { Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Fri May 14 13:02:56 2010 (r5548) @@ -18,7 +18,7 @@ */ #if SET_FIDVID == 1 -#include "../../../northbridge/amd/amdht/AsPsDefs.h" +#include <northbridge/amd/amdht/AsPsDefs.h> #define SET_FIDVID_DEBUG 1 Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Fri May 14 13:02:56 2010 (r5548) @@ -25,6 +25,9 @@ #include <northbridge/amd/amdht/AsPsDefs.h> #include <northbridge/amd/amdht/porting.h> +#include <cpu/x86/mtrr/earlymtrr.c> +#include <northbridge/amd/amdfam10/raminit_amdmct.c> + //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID #ifndef SET_FIDVID #define SET_FIDVID 1 @@ -976,3 +979,5 @@ } #endif } + +#include "fidvid.c" Modified: trunk/src/cpu/amd/quadcore/quadcore.c ============================================================================== --- trunk/src/cpu/amd/quadcore/quadcore.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/cpu/amd/quadcore/quadcore.c Fri May 14 13:02:56 2010 (r5548) @@ -18,6 +18,8 @@ */ #include <console/console.h> +#include <pc80/mc146818rtc_early.c> +#include <northbridge/amd/amdht/ht_wrapper.c> #ifndef SET_NB_CFG_54 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Fri May 14 13:02:56 2010 (r5548) @@ -46,7 +46,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include <console/console.h> #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> @@ -82,10 +81,8 @@ } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -95,7 +92,6 @@ #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Fri May 14 13:02:56 2010 (r5548) @@ -46,7 +46,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include <console/console.h> #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> @@ -104,10 +103,8 @@ } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -117,7 +114,6 @@ #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Fri May 14 13:02:56 2010 (r5548) @@ -46,7 +46,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include <console/console.h> #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> @@ -82,10 +81,8 @@ } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -95,7 +92,6 @@ #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Fri May 14 13:02:56 2010 (r5548) @@ -44,7 +44,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include <console/console.h> #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" @@ -88,10 +87,8 @@ } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -123,7 +120,6 @@ #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Fri May 14 13:02:56 2010 (r5548) @@ -42,7 +42,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include <console/console.h> #include "lib/ramtest.c" @@ -83,10 +82,8 @@ } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -108,7 +105,6 @@ #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Fri May 14 13:02:56 2010 (r5548) @@ -42,7 +42,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include <console/console.h> #include "lib/ramtest.c" @@ -86,10 +85,8 @@ } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -113,7 +110,6 @@ #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Fri May 14 13:02:56 2010 (r5548) @@ -44,7 +44,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include <console/console.h> #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" @@ -88,10 +87,8 @@ } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -120,7 +117,6 @@ #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" Modified: trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c Fri May 14 13:02:56 2010 (r5548) @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <delay.h> static void set_htic_bit(u8 i, u32 val, u8 bit) { Modified: trunk/src/northbridge/amd/amdht/h3gtopo.h ============================================================================== --- trunk/src/northbridge/amd/amdht/h3gtopo.h Fri May 14 11:59:59 2010 (r5547) +++ trunk/src/northbridge/amd/amdht/h3gtopo.h Fri May 14 13:02:56 2010 (r5548) @@ -20,6 +20,8 @@ #ifndef HTTOPO_H #define HTTOPO_H +#include <stddef.h> + /*---------------------------------------------------------------------------- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) *

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[commit] r5547 - trunk/src/northbridge/amd/gx2
by repository service 14 May '10

14 May '10

Author: stepan Date: Fri May 14 11:59:59 2010 New Revision: 5547 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5547 Log: fix SeaBIOS loading on GX2. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridgeinit.c Fri May 14 11:56:46 2010 (r5546) +++ trunk/src/northbridge/amd/gx2/northbridgeinit.c Fri May 14 11:59:59 2010 (r5547) @@ -672,7 +672,7 @@ { uint64_t shadowSettings = getShadow(); shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; // Disable read & writes - shadowSettings |= (uint64_t) 0x00000000F0000000ULL; // Enable reads for F0000-FFFFF + shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; // Enable reads for C0000-FFFFF setShadow(shadowSettings); }

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[commit] r5546 - trunk/src/northbridge/amd/gx2
by repository service 14 May '10

14 May '10

Author: stepan Date: Fri May 14 11:56:46 2010 New Revision: 5546 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5546 Log: Fix warning. Hardware tested and didn't change behavior. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/amd/gx2/chipsetinit.c Modified: trunk/src/northbridge/amd/gx2/chipsetinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/chipsetinit.c Fri May 14 11:48:05 2010 (r5545) +++ trunk/src/northbridge/amd/gx2/chipsetinit.c Fri May 14 11:56:46 2010 (r5546) @@ -268,7 +268,7 @@ if ((msr.lo&0xff) == 0x11) return; - totalmem = sizeram() << 20 - 1; + totalmem = (sizeram() << 20) - 1; // highest address totalmem >>= 12; totalmem = ~totalmem; totalmem &= 0xfffff;

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[commit] r5544 - in trunk/src/mainboard/wyse: . s50
by repository service 14 May '10

14 May '10

Author: stepan Date: Fri May 14 11:45:29 2010 New Revision: 5544 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5544 Log: This patch cleanes up the Wyse S50 port and unifies the memmory regions with Geode LX , adds gpl2 headers plus some white space fixes. This is build and boot tested.(of course vsa loading is stil not fixed,it now runs forever with :"Oops, exception 13 while executing option rom") Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/wyse/Kconfig trunk/src/mainboard/wyse/s50/Kconfig trunk/src/mainboard/wyse/s50/chip.h trunk/src/mainboard/wyse/s50/cmos.layout trunk/src/mainboard/wyse/s50/devicetree.cb trunk/src/mainboard/wyse/s50/irq_tables.c trunk/src/mainboard/wyse/s50/mainboard.c trunk/src/mainboard/wyse/s50/romstage.c Modified: trunk/src/mainboard/wyse/Kconfig ============================================================================== --- trunk/src/mainboard/wyse/Kconfig Tue May 11 17:39:20 2010 (r5543) +++ trunk/src/mainboard/wyse/Kconfig Fri May 14 11:45:29 2010 (r5544) @@ -1,3 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Nils Jacobs +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + choice prompt "Mainboard model" depends on VENDOR_WYSE Modified: trunk/src/mainboard/wyse/s50/Kconfig ============================================================================== --- trunk/src/mainboard/wyse/s50/Kconfig Tue May 11 17:39:20 2010 (r5543) +++ trunk/src/mainboard/wyse/s50/Kconfig Fri May 14 11:45:29 2010 (r5544) @@ -1,12 +1,11 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## Copyright (C) 2010 Nils Jacobs ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -49,3 +48,8 @@ int default 3 depends on BOARD_WYSE_S50 + +config RAMBASE + hex + default 0x4000 + depends on BOARD_WYSE_S50 Modified: trunk/src/mainboard/wyse/s50/chip.h ============================================================================== --- trunk/src/mainboard/wyse/s50/chip.h Tue May 11 17:39:20 2010 (r5543) +++ trunk/src/mainboard/wyse/s50/chip.h Fri May 14 11:45:29 2010 (r5544) @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Nils Jacobs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + extern struct chip_operations mainboard_ops; struct mainboard_config { Modified: trunk/src/mainboard/wyse/s50/cmos.layout ============================================================================== --- trunk/src/mainboard/wyse/s50/cmos.layout Tue May 11 17:39:20 2010 (r5543) +++ trunk/src/mainboard/wyse/s50/cmos.layout Fri May 14 11:45:29 2010 (r5544) @@ -1,3 +1,26 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2010 Nils Jacobs +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- + entries #start-bit length config config-ID name Modified: trunk/src/mainboard/wyse/s50/devicetree.cb ============================================================================== --- trunk/src/mainboard/wyse/s50/devicetree.cb Tue May 11 17:39:20 2010 (r5543) +++ trunk/src/mainboard/wyse/s50/devicetree.cb Fri May 14 11:45:29 2010 (r5544) @@ -1,3 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Nils Jacobs +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + chip northbridge/amd/gx2 register "irqmap" = "0xaa5b" register "setupflash" = "0" Modified: trunk/src/mainboard/wyse/s50/irq_tables.c ============================================================================== --- trunk/src/mainboard/wyse/s50/irq_tables.c Tue May 11 17:39:20 2010 (r5543) +++ trunk/src/mainboard/wyse/s50/irq_tables.c Fri May 14 11:45:29 2010 (r5544) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 200x TODO <TODO@TODO> + * Copyright (C) 2010 Nils Jacobs * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: trunk/src/mainboard/wyse/s50/mainboard.c ============================================================================== --- trunk/src/mainboard/wyse/s50/mainboard.c Tue May 11 17:39:20 2010 (r5543) +++ trunk/src/mainboard/wyse/s50/mainboard.c Fri May 14 11:45:29 2010 (r5544) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Nils Jacobs + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + #include <console/console.h> #include <device/device.h> #include <device/pci.h> Modified: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- trunk/src/mainboard/wyse/s50/romstage.c Tue May 11 17:39:20 2010 (r5543) +++ trunk/src/mainboard/wyse/s50/romstage.c Fri May 14 11:45:29 2010 (r5544) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Nils Jacobs + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -20,16 +41,17 @@ #include "northbridge/amd/gx2/raminit.h" + /* This is needed because ROMCC doesn`t now the ctz bitop */ static inline unsigned int ctz(unsigned int n) { - int zeros; + int zeros; - n = (n ^ (n - 1)) >> 1; + n = (n ^ (n - 1)) >> 1; for (zeros = 0; n; zeros++) { n >>= 1; } - return zeros; + return zeros; } static void sdram_set_spd_registers(const struct mem_controller *ctrl) @@ -42,7 +64,7 @@ msr_t msr; unsigned char module_banks, val; uint16_t dimm_size; - + msr = rdmsr(MC_CF07_DATA); /* get module banks (sides) per dimm, SPD byte 5 */ @@ -97,35 +119,30 @@ #include "northbridge/amd/gx2/raminit.c" #include "lib/generic_sdram.c" - #include "northbridge/amd/gx2/pll_reset.c" #include "cpu/amd/model_gx2/cpureginit.c" #include "cpu/amd/model_gx2/syspreinit.c" static void msr_init(void) { - /* total physical memory */ - __builtin_wrmsr(0x1808, 0x11f6bf00, 0x21c00002); - - /* traditional memory 0kB-512kB, 512kB-1MB */ - __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); - __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2dfbc040); - __builtin_wrmsr(0x10000028, 0x6bf00100, 0x2000001f); - __builtin_wrmsr(0x1000002c, 0xffff0003, 0x2000ffff); - - __builtin_wrmsr(0x10000080, 0x3, 0x0); - - __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); - __builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040); - __builtin_wrmsr(0x40000029, 0x6bf00100, 0x2000001f); - __builtin_wrmsr(0x4000002d, 0xffff0003, 0x2000ffff); - - __builtin_wrmsr(0x40000080, 0x1, 0x0); - - __builtin_wrmsr(0x50002001, 0x27, 0x0); - __builtin_wrmsr(0x4c002001, 0x1, 0x0); + /* Setup access to cache under 1MB. + __builtin_wrmsr(CPU_RCONF_DEFAULT, 0x1000a000, 0x24fffc02); /* Rom Properties: Write Serialize, WriteProtect. + * RomBase: 0xFFFC0 + * SysTop to RomBase Properties: Write Serialize, Cache Disable. + * SysTop: 0x000A0 + * System Memory Properties: (Write Back) */ + + __builtin_wrmsr(CPU_RCONF_A0_BF, 0x00000000, 0x00000000); /* 0xA0000-0xBFFFF : (Write Back) */ + __builtin_wrmsr(CPU_RCONF_C0_DF, 0x00000000, 0x00000000); /* 0xC0000-0xDFFFF : (Write Back) */ + __builtin_wrmsr(CPU_RCONF_E0_FF, 0x00000000, 0x00000000); /* 0xE0000-0xFFFFF : (Write Back) */ + + /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */ + __builtin_wrmsr(MSR_GLIU0_BASE1, 0x000fff80, 0x20000000); /* 0x00000-0x7FFFF */ + __builtin_wrmsr(MSR_GLIU0_BASE2, 0x080fffe0, 0x20000000); /* 0x80000-0x9FFFF */ + __builtin_wrmsr(MSR_GLIU0_SHADOW, 0xffff0003, 0x2000ffff); /* 0xC0000-0xFFFFF */ + __builtin_wrmsr(MSR_GLIU1_BASE1, 0x000fff80, 0x20000000); /* 0x00000-0x7FFFF */ + __builtin_wrmsr(MSR_GLIU1_BASE2, 0x080fffe0, 0x20000000); /* 0x80000-0x9FFFF */ + __builtin_wrmsr(MSR_GLIU1_SHADOW, 0xffff0003, 0x2000ffff); /* 0xC0000-0xFFFFF */ /* put code in northbridge[init].c here */ } @@ -137,13 +154,13 @@ }; SystemPreInit(); - msr_init(); cs5536_early_setup(); - + /* disable the power button */ outl(0x00, PMS_IO_BASE + 0x40); + /* cs5536_disable_internal_uart disable them. Set them up now... */ cs5536_setup_onchipuart(1); uart_init(); @@ -157,6 +174,8 @@ sdram_initialize(1, memctrl); print_err("ram setup done\n"); + msr_init(); + /* Check all of memory */ /*ram_check(0x00000000, 640*1024);*/ print_err("ram check done\n");

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problem compiling Coreboot+SeaBIOS+VGA BIOS
by Nathan Owens 13 May '10

13 May '10

I'm having a bit of a problem compiling Coreboot+SeaBIOS+VGA BIOS Here's my output. Any ideas? GEN build.h CC romstage.inc src/northbridge/amd/amdk8/early_ht.c:5: warning: ‘enumerate_ht_chain’ defined but not used src/northbridge/amd/amdk8/setup_resource_map.c:3: warning: ‘setup_resource_map_offset’ defined but not used src/northbridge/amd/amdk8/setup_resource_map.c:39: warning: ‘setup_resource_map_x_offset’ defined but not used src/northbridge/amd/amdk8/coherent_ht.c:208: warning: ‘fill_row’ defined but not used src/northbridge/amd/amdk8/raminit_f_dqs.c:1720: warning: ‘set_top_mem_ap’ defined but not used src/northbridge/amd/amdk8/raminit_f_dqs.c:1813: warning: ‘wait_till_sysinfo_in_ram’ defined but not used src/cpu/amd/model_fxx/init_cpus.c:182: warning: ‘wait_all_aps_started’ defined but not used POST romstage.inc GEN romstage/crt0.S CC mainboard/asus/m2v-mx_se/crt0.s CC mainboard/asus/m2v-mx_se/crt0.initobj.o CC console/console.initobj.o LINK coreboot.romstage HOSTCC util/sconfig/sconfig (link) SCONFIG mainboard/asus/m2v-mx_se/devicetree.cb CC mainboard/asus/m2v-mx_se/static.o CC lib/version.o CC console/console.o AR coreboot.a CC coreboot_ram.o CC coreboot_ram build/coreboot_ram.o: In function `__wrap___umoddi3': (.text+0x12583): undefined reference to `__umoddi3' build/coreboot_ram.o: In function `__wrap___moddi3': (.text+0x1258e): undefined reference to `__moddi3' build/coreboot_ram.o: In function `__wrap___udivdi3': (.text+0x12599): undefined reference to `__udivdi3' build/coreboot_ram.o: In function `__wrap___divdi3': (.text+0x125a4): undefined reference to `__divdi3' collect2: ld returned 1 exit status make: *** [build/coreboot_ram] Error 1

2 1

Re: [coreboot] FILO bug disk not seen at ata-0 (Doesn't try to detect on ATA only SIL3114)
by Joop Boonen 13 May '10

13 May '10

On Fri, May 7, 2010 11:11 pm, Peter Stuge wrote: > Joop Boonen wrote: >> >> I have an issue with FILO the disk at ata-0 isn't seen. >> >> I've been trying some more. I've used the old IDE in FILO. It now recognises the drive connected to the SIL3114. But still not the ATA drive. > > Curious. Maybe I can ask you to try even older code? I did a bunch of work on the IDE driver in FILO 0.5 but haven't kept up with current code. If you'd like to try the latest 0.5: > > svn co svn://coreboot.org/filo/branches/filo-0.5 > > Please disable the GRUB junk (comment out USE_GRUB), enable > filesystems you need, and enable DEBUG_BLOCKDEV, DEBUG_PCI, and > DEBUG_IDE. > I've just tested with filo-0.50. The IDE drives aren't seen. I've attached the log. > > Thanks. > > > //Peter > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

1 0

[PATCH]Some more removal of c-includes in AMD code
by Patrick Georgi 13 May '10

13 May '10

Hi, attached patch removes another set of includes from Fam10 romstages: northbridge/amd/amdht/ht_wrapper.c northbridge/amd/amdfam10/raminit_amdmct.c cpu/amd/model_10xxx/fidvid.c pc80/mc146818rtc_early.c are included from within other AMD files now (where they are references). They can later be replaced with header file includes and initobj-linking. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 1

Re: [coreboot] Preview: SECC Pentium 2/3 users are gonna love this
by Mick Reed 13 May '10

13 May '10

I'd like to see your work as well, I have a PII SECC board here with a 440BX.

2 1

[PATCH] Wyse S50 cleanup
by Nils 12 May '10

12 May '10

This patch cleanes up the Wyse S50 port and unifies the memmory regions with Geode LX , adds gpl2 headers plus some white space fixes. This is build and boot tested.(of course vsa loading is stil not fixed,it now runs forever with :"Oops, exception 13 while executing option rom") Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Hi Patrick, Thanks for the review! Op woensdag 12 mei 2010 12:49:47 schreef u: >In Kconfig: > >+## the Free Software Foundation; either version 2 of the License, or >+## (at your option) any later version. > >We usually use exactly version 2, not 2 plus whatever the FSF might come >up with in future. The other files already use the "version 2 only" verbage. I am sorry about that mistake, i copied it from AMD Rumba. Attached you find a corrected v2 version of the patch. I looked a little at the current trunk and found a "few" other kconfig`s that had the "wrong" GPLv2 header. I hope everybody knows this new rule because the last wrong one is committed two weeks ago! I think often new patches are copied out of trunk. To stop the chance of copying the wrong version, i prepared a little patch for you.(see attachment 2) > > >+config RAMBASE >+ hex >+ default 0x4000 >+ depends on BOARD_WYSE_S50 > >Is that necessary? If so, we should fix the reason. RAMBASE below 1MB is >going to go away as soon as the remaining issues are fixed. This is necessary in rev5542, otherwise the board hangs after ramtest. See attached log.I didn`t test it with rev5543(the new revisions come faster than i can test). :) So i think this is one of the remaining issues. > > >Everything else is >Acked-by: Patrick Georgi <patrick.georgi at coresystems.de> Thanks,Nils

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coreboot May 2010