coreboot March 2008

coreboot@coreboot.org

75 participants
382 discussions

Re: [coreboot] r636 - in coreboot-v3: include mainboard/artecgroup/dbe61 mainboard/artecgroup/dbe62 mainboard/pcengines/alix1c northbridge/amd/geodelx southbridge/amd/cs5536
by Uwe Hermann 07 Mar '08

07 Mar '08

On Fri, Mar 07, 2008 at 12:33:59AM +0100, svn(a)coreboot.org wrote: > Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c > =================================================================== > --- coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-03-06 23:18:13 UTC (rev 635) > +++ coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-03-06 23:33:59 UTC (rev 636) > @@ -97,13 +97,17 @@ > /* returns 0xFF on any failures */ > u8 ret = 0xff; > > - printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); > + printk(BIOS_DEBUG, "spd_read_byte dev %04x", device); > if (device == DIMM0) { > for (i = 0; i < ARRAY_SIZE(spd_table); i++) { > if (spd_table[i].address == address) { > ret = spd_table[i].data; No break here? > } > } > + > + if (i == ARRAY_SIZE(spd_table)) > + printk(BIOS_DEBUG, " addr %02x does not exist in SPD table", > + address); > } > > printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret); > > Modified: coreboot-v3/northbridge/amd/geodelx/raminit.c > =================================================================== > --- coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-03-06 23:18:13 UTC (rev 635) > +++ coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-03-06 23:33:59 UTC (rev 636) > @@ -130,6 +130,7 @@ > /* Module Density * Module Banks */ > /* Shift to multiply by the number of DIMM banks. */ > dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; > + printk(BIOS_DEBUG, "DIMM size is %x\n", dimm_size); > banner(BIOS_DEBUG, "BEFORT CTZ"); > dimm_size = __builtin_ctz(dimm_size); > banner(BIOS_DEBUG, "TEST DIMM SIZE>8"); > @@ -183,6 +184,7 @@ > banner(BIOS_DEBUG, "RDMSR CF07"); > msr = rdmsr(MC_CF07_DATA); > banner(BIOS_DEBUG, "WRMSR CF07"); > + printk(BIOS_DEBUG, "CF07(%x): %08x.%08x\n", MC_CF07_DATA, msr.hi, msr.lo); > if (dimm == dimm0) { > msr.hi &= 0xFFFF0000; > msr.hi |= dimm_setting; > @@ -223,6 +225,7 @@ > /* Turn SPD ns time into MHz. Check what the asm does to this math. */ > speed = 2 * ((10000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F)))); > > + printk(BIOS_DEBUG, "ddr max speed is %d\n", speed); ddr -> DDR > /* Current speed > max speed? */ > if (geode_link_speed() > speed) { > printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink speed\n"); > @@ -266,6 +269,7 @@ > msr = rdmsr(MC_CF07_DATA); > msr.lo |= ((rate0 * (geode_link_speed() / 2)) / 16) > << CF07_LOWER_REF_INT_SHIFT; > + printk(BIOS_DEBUG, "Refresh rate set to %x\n", rate0); > wrmsr(MC_CF07_DATA, msr); > } > > @@ -385,6 +389,7 @@ > hlt(); > } > > + printk(BIOS_DEBUG, "Set cas latency to %x\n", spd_byte); cas -> CAS > Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.h > =================================================================== > --- coreboot-v3/southbridge/amd/cs5536/cs5536.h 2008-03-06 23:18:13 UTC (rev 635) > +++ coreboot-v3/southbridge/amd/cs5536/cs5536.h 2008-03-06 23:33:59 UTC (rev 636) > @@ -444,6 +444,7 @@ > /* Function prototypes */ > void cs5536_disable_internal_uart(void); > void cs5536_setup_onchipuart(void); > +void cs5536_setup_onchipuart2(void); Is there some more descriptive suffix than "2" for this function? > void cs5536_stage1(void); > > #endif /* SOUTHBRIDGE_AMD_CS5536_CS5536_H */ > > @@ -239,6 +222,40 @@ > wrmsr(MDD_UART1_CONF, msr); > } > > +void cs5536_setup_onchipuart2(void) Please add a (doxygen-)comment for this function, which should also mention what is different to cs5536_setup_onchipuart() and why we need two such functions. > +{ > + struct msr msr; > + > + /* GPIO4 - UART2_TX */ > + /* Set: Output Enable (0x4) */ > + outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); > + /* Set: OUTAUX1 Select (0x10) */ > + outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); > + /* GPIO4 - UART2_RX */ > + /* Set: Input Enable (0x20) */ > + outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); > + /* Set: INAUX1 Select (0x34) */ The (0x4), (0x10), (0x20), (0x34) etc. should be dropped, that's what the defines are used for. We don't _care_ about the actual numbers here. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

3 2

libplayload and coreinfo
by Jordan Crouse 06 Mar '08

06 Mar '08

Greetings. I've been talking about it for a while, and I've gotten a few people excited, so I figured it was time to actually release something useful. I believe that there is a lot of power in coreboot for AMD customers, especially in the embedded market which my team supports. Part of that power is in the low cost and high visibility of the open source code, but also in the flexibility of the payload model. Now, for a very low cost a customer can get not only the hardware initialization, but also an blank page where they can add their own special, be it a fully fledged payload, or just an intermediary before loading an operating system. This is where libpayload comes in - it abstracts away the icky bits of payload initialization, and gives the user a semblance of a normal C library that they can use to develop a payload without having to worry about re-implementing malloc() and printf() and all the other usual friends. I am happy to release the first proof of concept for libpayload: http://coreboot.org/~jcrouse/libpayload_0.1.tar.gz This is a conglomeration of code from three projects - the payload initialization code from FILO, superb curses code from our good friend Uwe Hermann, and various libc and driver bits from coreboot-v3. I combined them together into a library, mixed kconfig into the mix and baked at 300F for 2 hours. This is proof of concept code for the most part, and I wouldn't go off and put this in your airplane autopilot quite yet, but its a good start. And to celebrate the good start, how about something practical to go with it? Here is something I call coreinfo: http://coreboot.org/~jcrouse/coreinfo_0.1.tar.gz Coreinfo is a curses based payload that outputs lots of information about the CPU and system. Or rather, it will - for now it just shows the cpuid of the processor, and has a rather slick PCI device browser. The most important thing is that it shows that libpayload can be used for a relatively complex payload without really breathing hard. Here's a screenshot: http://coreboot.org/~jcrouse/coreinfo_screenshot.png So, please, enjoy. Flame me as needed, and once everybody has digested this for a bit, we'll meet back and discuss what the next step is. Obviously, I think more libc functions are needed, filesystem support is useful, and maybe even graphics are in our future. Jordan -- Jordan Crouse Systems Software Development Engineer Advanced Micro Devices, Inc.

5 7

r636 - in coreboot-v3: include mainboard/artecgroup/dbe61 mainboard/artecgroup/dbe62 mainboard/pcengines/alix1c northbridge/amd/geodelx southbridge/amd/cs5536
by svn＠coreboot.org 06 Mar '08

06 Mar '08

Author: rminnich Date: 2008-03-07 00:33:59 +0100 (Fri, 07 Mar 2008) New Revision: 636 Modified: coreboot-v3/include/lib.h coreboot-v3/mainboard/artecgroup/dbe61/initram.c coreboot-v3/mainboard/artecgroup/dbe62/Makefile coreboot-v3/mainboard/artecgroup/dbe62/dts coreboot-v3/mainboard/artecgroup/dbe62/initram.c coreboot-v3/mainboard/artecgroup/dbe62/stage1.c coreboot-v3/mainboard/pcengines/alix1c/initram.c coreboot-v3/northbridge/amd/geodelx/raminit.c coreboot-v3/southbridge/amd/cs5536/cs5536.c coreboot-v3/southbridge/amd/cs5536/cs5536.h coreboot-v3/southbridge/amd/cs5536/dts coreboot-v3/southbridge/amd/cs5536/stage1.c Log: This is a cumulative set of fixes for LX800 boards. These are all tested on ALIX 1C and DBE62. This includes: - the working power button patch. - onchipuart2 for very early startup -- this will be replaced with a better mechanism soon. - dts mod for powerbutton on cs5536 - dbe62 dts fix for COM1 setup - ram check call in dbe62 initram.c - Carl-Daniel's fix to detect incorrect access to spd variables. - more debug prints in geodelx northbridge support code. This is cumulative since we're lagging on acks a bit and it's hard to keep this stuff all seperated out since it involves a common set of files. I'd like to get it acked and in tree today if possible. It's a very small set of lines changed so please forgive me for the cumulative nature. Thanks Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/include/lib.h =================================================================== --- coreboot-v3/include/lib.h 2008-03-06 23:18:13 UTC (rev 635) +++ coreboot-v3/include/lib.h 2008-03-06 23:33:59 UTC (rev 636) @@ -36,4 +36,7 @@ void beep_short(void); void beep_long(void); +/* Optional ramtest. */ +void ram_check(unsigned long start, unsigned long stop); + #endif /* LIB_H */ Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-03-06 23:18:13 UTC (rev 635) +++ coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-03-06 23:33:59 UTC (rev 636) @@ -97,13 +97,17 @@ /* returns 0xFF on any failures */ u8 ret = 0xff; - printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); + printk(BIOS_DEBUG, "spd_read_byte dev %04x", device); if (device == DIMM0) { for (i = 0; i < ARRAY_SIZE(spd_table); i++) { if (spd_table[i].address == address) { ret = spd_table[i].data; } } + + if (i == ARRAY_SIZE(spd_table)) + printk(BIOS_DEBUG, " addr %02x does not exist in SPD table", + address); } printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret); Modified: coreboot-v3/mainboard/artecgroup/dbe62/Makefile =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/Makefile 2008-03-06 23:18:13 UTC (rev 635) +++ coreboot-v3/mainboard/artecgroup/dbe62/Makefile 2008-03-06 23:33:59 UTC (rev 636) @@ -23,7 +23,7 @@ INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \ - $(src)/arch/x86/geodelx/geodelx.c + $(src)/arch/x86/geodelx/geodelx.c $(src)/lib/ramtest.c STAGE2_MAINBOARD_OBJ = Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-03-06 23:18:13 UTC (rev 635) +++ coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-03-06 23:33:59 UTC (rev 636) @@ -43,6 +43,12 @@ /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. * See virtual PIC spec. */ enable_gpio_int_route = "0x0D0C0700"; + /* we use com2 since that is on the dongle */ + com2_enable = "1"; + /* Set com2 address to be COM1 */ + com2_address = "0x3f8"; + /* Set com2 IRQ to be what is usually COM1 */ + com2_irq = "4"; }; }; }; Modified: coreboot-v3/mainboard/artecgroup/dbe62/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/initram.c 2008-03-06 23:18:13 UTC (rev 635) +++ coreboot-v3/mainboard/artecgroup/dbe62/initram.c 2008-03-06 23:33:59 UTC (rev 636) @@ -53,7 +53,7 @@ /* Save space by using a short list of SPD values used by Geode LX Memory init */ static const struct spd_entry spd_table[] = { - {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, + {SPD_ACCEPTABLE_CAS_LATENCIES, 0xe}, {SPD_BANK_DENSITY, 0x40}, {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, {SPD_MEMORY_TYPE, 7}, @@ -63,7 +63,7 @@ {SPD_PRIMARY_SDRAM_WIDTH, 8}, {SPD_NUM_DIMM_BANKS, 1}, {SPD_NUM_COLUMNS, 0xa}, - {SPD_NUM_ROWS, 3}, + {SPD_NUM_ROWS, 13}, {SPD_REFRESH, 0x3a}, {SPD_SDRAM_CYCLE_TIME_2ND, 60}, {SPD_SDRAM_CYCLE_TIME_3RD, 75}, @@ -87,13 +87,18 @@ /* returns 0xFF on any failures */ u8 ret = 0xff; - printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); + printk(BIOS_DEBUG, "spd_read_byte dev %04x", device); if (device == DIMM0) { for (i = 0; i < ARRAY_SIZE(spd_table); i++) { if (spd_table[i].address == address) { ret = spd_table[i].data; + break; } } + + if (i == ARRAY_SIZE(spd_table)) + printk(BIOS_DEBUG, " addr %02x does not exist in SPD table", + address); } printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret); @@ -147,7 +152,7 @@ printk(BIOS_DEBUG, "done sdram enable\n"); /* Check low memory */ - /*ram_check(0x00000000, 640*1024); */ + ram_check(0x00000000, 640*1024); printk(BIOS_DEBUG, "stage1 returns\n"); return 0; Modified: coreboot-v3/mainboard/artecgroup/dbe62/stage1.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/stage1.c 2008-03-06 23:18:13 UTC (rev 635) +++ coreboot-v3/mainboard/artecgroup/dbe62/stage1.c 2008-03-06 23:33:59 UTC (rev 636) @@ -58,7 +58,7 @@ * NOTE: Must do this AFTER the early_setup! It is counting on some * early MSR setup for the CS5536. */ - cs5536_setup_onchipuart(); + cs5536_setup_onchipuart2(); } void mainboard_pre_payload(void) Modified: coreboot-v3/mainboard/pcengines/alix1c/initram.c =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/initram.c 2008-03-06 23:18:13 UTC (rev 635) +++ coreboot-v3/mainboard/pcengines/alix1c/initram.c 2008-03-06 23:33:59 UTC (rev 636) @@ -97,13 +97,17 @@ /* returns 0xFF on any failures */ u8 ret = 0xff; - printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); + printk(BIOS_DEBUG, "spd_read_byte dev %04x", device); if (device == DIMM0) { for (i = 0; i < ARRAY_SIZE(spd_table); i++) { if (spd_table[i].address == address) { ret = spd_table[i].data; + break; } } + if (i == ARRAY_SIZE(spd_table)) + printk(BIOS_DEBUG, " addr %02x does not exist in SPD table", + address); } printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret); Modified: coreboot-v3/northbridge/amd/geodelx/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-03-06 23:18:13 UTC (rev 635) +++ coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-03-06 23:33:59 UTC (rev 636) @@ -130,6 +130,7 @@ /* Module Density * Module Banks */ /* Shift to multiply by the number of DIMM banks. */ dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; + printk(BIOS_DEBUG, "DIMM size is %x\n", dimm_size); banner(BIOS_DEBUG, "BEFORT CTZ"); dimm_size = __builtin_ctz(dimm_size); banner(BIOS_DEBUG, "TEST DIMM SIZE>8"); @@ -183,6 +184,7 @@ banner(BIOS_DEBUG, "RDMSR CF07"); msr = rdmsr(MC_CF07_DATA); banner(BIOS_DEBUG, "WRMSR CF07"); + printk(BIOS_DEBUG, "CF07(%x): %08x.%08x\n", MC_CF07_DATA, msr.hi, msr.lo); if (dimm == dimm0) { msr.hi &= 0xFFFF0000; msr.hi |= dimm_setting; @@ -223,6 +225,7 @@ /* Turn SPD ns time into MHz. Check what the asm does to this math. */ speed = 2 * ((10000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F)))); + printk(BIOS_DEBUG, "ddr max speed is %d\n", speed); /* Current speed > max speed? */ if (geode_link_speed() > speed) { printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink speed\n"); @@ -266,6 +269,7 @@ msr = rdmsr(MC_CF07_DATA); msr.lo |= ((rate0 * (geode_link_speed() / 2)) / 16) << CF07_LOWER_REF_INT_SHIFT; + printk(BIOS_DEBUG, "Refresh rate set to %x\n", rate0); wrmsr(MC_CF07_DATA, msr); } @@ -385,6 +389,7 @@ hlt(); } + printk(BIOS_DEBUG, "Set cas latency to %x\n", spd_byte); msr = rdmsr(MC_CF8F_DATA); msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT); msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT; Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-03-06 23:18:13 UTC (rev 635) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-03-06 23:33:59 UTC (rev 636) @@ -89,6 +89,26 @@ }; /** + * Power button setup. + * + * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which + * controls all voltage rails except Vstandby & Vmem. We need to enable + * OUT_AUX1 and OUTPUT_ENABLE in this order. + * + * @param sb The southbridge config structure. + * If GPIO24 is not enabled then soft-off will not work. + */ +static void cs5536_setup_power_button(struct southbridge_amd_cs5536_dts_config *sb ) +{ + if (!sb->power_button) + return; + /* TODO: Should be a #define? */ + outl(0x40020000, PMS_IO_BASE + 0x40); + outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT); + outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE); +} + +/** * Program ACPI LBAR and initialize ACPI registers. */ static void pm_chipset_init(void) @@ -617,6 +637,8 @@ if (sb->enable_ide) ide_init(dev); + cs5536_setup_power_button(sb); + printk(BIOS_SPEW, "cs5536: %s() Exit\n", __FUNCTION__); } Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.h =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.h 2008-03-06 23:18:13 UTC (rev 635) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.h 2008-03-06 23:33:59 UTC (rev 636) @@ -444,6 +444,7 @@ /* Function prototypes */ void cs5536_disable_internal_uart(void); void cs5536_setup_onchipuart(void); +void cs5536_setup_onchipuart2(void); void cs5536_stage1(void); #endif /* SOUTHBRIDGE_AMD_CS5536_CS5536_H */ Modified: coreboot-v3/southbridge/amd/cs5536/dts =================================================================== --- coreboot-v3/southbridge/amd/cs5536/dts 2008-03-06 23:18:13 UTC (rev 635) +++ coreboot-v3/southbridge/amd/cs5536/dts 2008-03-06 23:33:59 UTC (rev 636) @@ -56,4 +56,12 @@ com2_enable = "0"; com2_address = "0x2f8"; com2_irq = "3"; + + /* enable/disable power button. On systems with no power switch, + * one usually does not want the button enabled. Example: + * Alix1C, dbe62, dbe61. If you enable this, and the power is + * hard-wired, the board will turn off after 4 seconds, which is + * probably not what you want. + */ + power_button = "0"; }; Modified: coreboot-v3/southbridge/amd/cs5536/stage1.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/stage1.c 2008-03-06 23:18:13 UTC (rev 635) +++ coreboot-v3/southbridge/amd/cs5536/stage1.c 2008-03-06 23:33:59 UTC (rev 636) @@ -113,23 +113,6 @@ } /** - * Power button setup. - * - * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which - * controls all voltage rails except Vstandby & Vmem. We need to enable - * OUT_AUX1 and OUTPUT_ENABLE in this order. - * - * If GPIO24 is not enabled then soft-off will not work. - */ -static void cs5536_setup_power_button(void) -{ - /* TODO: Should be a #define? */ - outl(0x40020000, PMS_IO_BASE + 0x40); - outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT); - outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE); -} - -/** * Set the various GPIOs. * * An unknown question at this point is how general this is to all mainboards. @@ -239,6 +222,40 @@ wrmsr(MDD_UART1_CONF, msr); } +void cs5536_setup_onchipuart2(void) +{ + struct msr msr; + + /* GPIO4 - UART2_TX */ + /* Set: Output Enable (0x4) */ + outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); + /* Set: OUTAUX1 Select (0x10) */ + outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); + /* GPIO4 - UART2_RX */ + /* Set: Input Enable (0x20) */ + outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); + /* Set: INAUX1 Select (0x34) */ + outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); + + /* Set: GPIO 3 + 3 Pull Up (0x18) */ + outl(GPIOL_3_SET | GPIOL_4_SET, GPIO_IO_BASE + GPIOL_PULLUP_ENABLE); + + /* set address to 3F8 */ + msr = rdmsr(MDD_LEG_IO); + msr.lo |= 0x7 << 20; + wrmsr(MDD_LEG_IO, msr); + + /* Bit 1 = DEVEN (device enable) + * Bit 4 = EN_BANKS (allow access to the upper banks + */ + msr.lo = (1 << 4) | (1 << 1); + msr.hi = 0; + + /* enable COM2 */ + wrmsr(MDD_UART2_CONF, msr); +} + + /** * Board setup. * @@ -279,5 +296,4 @@ cs5536_setup_iobase(); cs5536_setup_smbus_gpio(); /* cs5536_enable_smbus(); -- Leave this out for now. */ - cs5536_setup_power_button(); }

1 0

[PATCH] Small lib/ramtest.c fixes
by Uwe Hermann 06 Mar '08

06 Mar '08

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

r635 - coreboot-v3/lib
by svn＠coreboot.org 06 Mar '08

06 Mar '08

Author: uwe Date: 2008-03-07 00:18:13 +0100 (Fri, 07 Mar 2008) New Revision: 635 Modified: coreboot-v3/lib/ramtest.c Log: Small fixes for lib/ramtest.c: - Don't make write_phys/read_phys static, they can be useful elsewhere. - Rename write_phys/read_phys to ram_write_phys/ram_read_phys for consistency with the other RAM-related functions. - Simplify some parts of the code a bit. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/lib/ramtest.c =================================================================== --- coreboot-v3/lib/ramtest.c 2008-03-06 18:26:45 UTC (rev 634) +++ coreboot-v3/lib/ramtest.c 2008-03-06 23:18:13 UTC (rev 635) @@ -29,7 +29,7 @@ * @param addr The memory address to write to. * @param value The value to write into the specified memory address. */ -static void write_phys(unsigned long addr, unsigned long value) +void ram_write_phys(unsigned long addr, unsigned long value) { volatile unsigned long *ptr; ptr = (void *)addr; @@ -42,7 +42,7 @@ * @param addr The memory address to read from. * @return The value read from the specified memory address. */ -static unsigned long read_phys(unsigned long addr) +unsigned long ram_read_phys(unsigned long addr) { volatile unsigned long *ptr; ptr = (void *)addr; @@ -68,7 +68,7 @@ /* Display address being filled. */ if (!(addr & 0xffff)) printk(BIOS_DEBUG, "%lx\r", addr); - write_phys(addr, addr); + ram_write_phys(addr, addr); }; /* Display final address. */ printk(BIOS_DEBUG, "%lx\nDRAM filled.\n", addr); @@ -94,14 +94,13 @@ /* Display address being tested. */ if (!(addr & 0xffff)) printk(BIOS_DEBUG, "%lx\r", addr); - value = read_phys(addr); + value = ram_read_phys(addr); if (value != addr) { /* Display address with error. */ printk(BIOS_ERR, "Fail @%lx Read value=%lx\n", addr, value); - i++; /* Abort after 256 verify errors. */ - if (i > 256) { + if (++i > 256) { printk(BIOS_ERR, "Aborting.\n"); break; } @@ -111,11 +110,8 @@ /* Display final address. */ printk(BIOS_DEBUG, "%lx\r", addr); - if (i) { - printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n"); - } else { - printk(BIOS_DEBUG, "\nDRAM range verified.\n"); - } + /* Print whether or not the verify failed. */ + printk(BIOS_DEBUG, "\nDRAM range %sverified.", i ? "_NOT_ " : ""); } /**

1 0

Amideco
by Mikhail Savchenko 06 Mar '08

06 Mar '08

Amideco download site is down, can anybody mail me this util sources? Thank you!

2 1

LinuxBios for E-pc C10
by giraut benoit 06 Mar '08

06 Mar '08

Hello Is there any chance to get my E-PC C10 board booting a linux bios ? The Northbridge Intel 82810 and the Southbridge Intel* * 82801 are supported now. How can I process to test this board ? I had read few months ago that someone try to port the linuxbios to this board but i can't remember who ? Thx benoit

3 3

FILO loads image but, Linux doesnt boot
by Phani Babu Giddi 06 Mar '08

06 Mar '08

Hello All, I am running Coreboot v2 on AMD's db800 with FILO as the payload. It gets to a point where it intialzes the kernel but the kernel doesnt boot. Any idea whats going on.. I have captured the messages using the serial console. The last few messages are... linux-34w5:~ # tail minicom.cap parse_command_line: initrd=/initrd-2.6.16.46-0.12-default parse_command_line: kernel command line (64 bytes): "root=/dev/hda3 vga=0x317 resume=/dev/hda2 splash=silent showopts" load_linux_kernel: offset=0x2000 addr=0x100000 size=0x13158c Loading kernel... ok file_open: dev=<NULL>, path=/initrd-2.6.16.46-0.12-default load_initrd: start=0x1f502000 end=0x1f7aeb32 Loading initrd... ok malloc_diag: alloc: 312 bytes (4 blocks), free: 16064 bytes (1 blocks) start_linux: eip=0x100000 Jumping to entry point... Is this the last message that one is suppose to see with coreboot ? Regards, Phani

5 9

r634 - coreboot-v3/lib
by svn＠coreboot.org 06 Mar '08

06 Mar '08

Author: uwe Date: 2008-03-06 19:26:45 +0100 (Thu, 06 Mar 2008) New Revision: 634 Modified: coreboot-v3/lib/ram.c coreboot-v3/lib/ramtest.c Log: Various cosmetic fixes, added Doxygen comments (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: coreboot-v3/lib/ram.c =================================================================== --- coreboot-v3/lib/ram.c 2008-03-06 16:35:44 UTC (rev 633) +++ coreboot-v3/lib/ram.c 2008-03-06 18:26:45 UTC (rev 634) @@ -33,10 +33,11 @@ hlt(); } -/* Northbridge or memory controller code must define these functions */ +/* Northbridge or memory controller code must define these functions. */ void ram_set_registers(void *ctrl, int i); int ram_set_spd_registers(void *ctrl, int i); void ram_enable(int controllers, void *ctrl); + /** * ram_initialize() is is the main RAM init function. * @@ -45,10 +46,11 @@ * of making it an empty function. * * @param controllers How many memory controllers there are. - * @param ctrl Pointer to the mem control structure. This is a generic pointer, since the - * structure is wholly chip-dependent, and a survey of all the types makes it clear that a common - * struct is not possible. We can not use the device tree here as this code is run before the device tree - * is available. + * @param ctrl Pointer to the mem control structure. This is a generic pointer, + * since the structure is wholly chip-dependent, and a survey of + * all the types makes it clear that a common struct is not + * possible. We can not use the device tree here as this code is + * run before the device tree is available. */ void ram_initialize(int controllers, void *ctrl) { @@ -61,10 +63,10 @@ ram_set_registers(ctrl, i); } - /* Now setup those things we can auto detect. */ + /* Now setup those things we can auto-detect via SPD. */ for (i = 0; i < controllers; i++) { printk(BIOS_INFO, - "Setting SPD based registers of RAM controller %d\n", i); + "Setting SPD based registers of RAM controller %d\n", i); ram_set_spd_registers(ctrl, i); } Modified: coreboot-v3/lib/ramtest.c =================================================================== --- coreboot-v3/lib/ramtest.c 2008-03-06 16:35:44 UTC (rev 633) +++ coreboot-v3/lib/ramtest.c 2008-03-06 18:26:45 UTC (rev 634) @@ -23,7 +23,12 @@ #include <lib.h> #include <console.h> - +/** + * Write a value into memory. + * + * @param addr The memory address to write to. + * @param value The value to write into the specified memory address. + */ static void write_phys(unsigned long addr, unsigned long value) { volatile unsigned long *ptr; @@ -31,6 +36,12 @@ *ptr = value; } +/** + * Read a value from memory. + * + * @param addr The memory address to read from. + * @return The value read from the specified memory address. + */ static unsigned long read_phys(unsigned long addr) { volatile unsigned long *ptr; @@ -38,71 +49,89 @@ return *ptr; } +/** + * Fill the specified RAM area. + * + * The data which is written into RAM is the address of each memory location. + * E.g., we write a value of 0x1234 into address 0x1234, we write 0x1235 into + * memory address 0x1235, and so on. + * + * @param start The beginning of the RAM area. + * @param stop The end of the RAM area. + */ static void ram_fill(unsigned long start, unsigned long stop) { unsigned long addr; - /* - * Fill. - */ + printk(BIOS_DEBUG, "DRAM fill: %lx-%lx\n", start, stop); - for(addr = start; addr < stop ; addr += 4) { - /* Display address being filled */ - if (!(addr & 0xffff)) { + for (addr = start; addr < stop; addr += 4) { + /* Display address being filled. */ + if (!(addr & 0xffff)) printk(BIOS_DEBUG, "%lx\r", addr); - } write_phys(addr, addr); }; - /* Display final address */ - printk(BIOS_DEBUG, "%lx\nDRAM filled\n", addr); + /* Display final address. */ + printk(BIOS_DEBUG, "%lx\nDRAM filled.\n", addr); } +/** + * Verify the specified RAM area. + * + * This checks whether the specified RAM locations return the "correct" data + * as written by ram_fill(). The value at address 0x1234 for example should + * be 0x1234, the value of address 0x1235 should be 0x1235, and so on. + * + * @param start The beginning of the RAM area. + * @param stop The end of the RAM area. + */ static void ram_verify(unsigned long start, unsigned long stop) { - unsigned long addr; + unsigned long addr, value; int i = 0; - /* - * Verify. - */ + printk(BIOS_DEBUG, "DRAM verify: %lx-%lx\n", start, stop); - for(addr = start; addr < stop ; addr += 4) { - unsigned long value; - /* Display address being tested */ - if (!(addr & 0xffff)) { + for (addr = start; addr < stop; addr += 4) { + /* Display address being tested. */ + if (!(addr & 0xffff)) printk(BIOS_DEBUG, "%lx\r", addr); - } value = read_phys(addr); if (value != addr) { - /* Display address with error */ - printk(BIOS_ERR, "Fail @%lx Read value=%lx\n", - addr, value); + /* Display address with error. */ + printk(BIOS_ERR, "Fail @%lx Read value=%lx\n", + addr, value); i++; - if(i>256) { + /* Abort after 256 verify errors. */ + if (i > 256) { printk(BIOS_ERR, "Aborting.\n"); break; } } } - /* Display final address */ + + /* Display final address. */ printk(BIOS_DEBUG, "%lx\r", addr); + if (i) { printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n"); - } - else { + } else { printk(BIOS_DEBUG, "\nDRAM range verified.\n"); } } - +/** + * Check whether the specified RAM area verifies correctly, and thus whether + * we can be reasonably confident that our DRAM setup is correct. + * + * This is much more of a "Is my DRAM properly configured?" test than + * a "Is my DRAM faulty?" test, though. + * + * @param start The beginning of the RAM area. + * @param stop The end of the RAM area. + */ void ram_check(unsigned long start, unsigned long stop) { - /* - * This is much more of a "Is my DRAM properly configured?" - * test than a "Is my DRAM faulty?" test. Not all bits - * are tested. -Tyson - */ printk(BIOS_DEBUG, "Testing DRAM: %lx-%lx\n", start, stop); ram_fill(start, stop); ram_verify(start, stop); printk(BIOS_DEBUG, "Done.\n"); } -

1 0

add ramtest to lib
by ron minnich 06 Mar '08

06 Mar '08

attached.

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coreboot March 2008