coreboot March 2008

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A lar patch with some cleanup and adding greedy name matching
by Myles Watson 05 Mar '08

05 Mar '08

This patch fixes lar options parsing, a seg fault with long path names, and makes use of functions that were already defined. It also adds greedy name matching for listing and extracting archives, which allows recursive descent into the lar directory structure. An example is: lar -l normal/payload normal/payload/segment0 (172032 bytes, zeroes compressed to 1 bytes @0x4330);loadaddress 0x0x112e60 entry 0x0x10e5fc normal/payload/segment1 (77384 bytes, lzma compressed to 42674 bytes @0x4390);loadaddress 0x0x100000 entry 0x0x10e5fc normal/payload/segment2 (72 bytes, lzma compressed to 47 bytes @0xeaa0);loadaddress 0x0x13ce60 entry 0x0x10e5fc Total size = 42962B 41KB (0xa7d2) instead of No matching lar entries found. Myles file-by-file changes: util/lar/lar.c: add more options to the usage message use get_larsize() instead of using larsize rearrange errors from parsing args to be more correct util/lar/stream.c: change elfname size to MAX_PATHLEN instead of 64 make file_in_list greedy with filename matches change total_size calculation to include file names change lar_add_entry to use header_len function instead of reinventing Signed-off-by: Myles Watson <mylesgw(a)gmail.com>

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r632 - coreboot-v3/util/lar
by svn＠coreboot.org 05 Mar '08

05 Mar '08

Author: myles Date: 2008-03-05 15:51:35 +0100 (Wed, 05 Mar 2008) New Revision: 632 Modified: coreboot-v3/util/lar/lar.c coreboot-v3/util/lar/stream.c Log: This patch fixes lar options parsing, a seg fault with long path names, and makes use of functions that were already defined. It also adds greedy name matching for listing and extracting archives, which allows recursive descent into the lar directory structure. changes file-by-file: util/lar/lar.c: add more options to the usage message use get_larsize() instead of using larsize rearrange errors from parsing args to be more correct util/lar/stream.c: change elfname size to MAX_PATHLEN instead of 64 make file_in_list greedy with filename matches change total_size calculation to include file names change lar_add_entry to use header_len function instead of reinventing Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/util/lar/lar.c =================================================================== --- coreboot-v3/util/lar/lar.c 2008-03-05 12:57:10 UTC (rev 631) +++ coreboot-v3/util/lar/lar.c 2008-03-05 14:51:35 UTC (rev 632) @@ -44,8 +44,9 @@ static void usage(char *name) { - printf("\nLAR - the Lightweight Archiver " VERSION "\n" COPYRIGHT "\n\n" - "Usage: %s [-ecxal] archive.lar [[[file1] file2] ...]\n\n", name); + printf("\nLAR - the Lightweight Archiver " VERSION "\n" COPYRIGHT "\n\n"); + printf("Usage: %s [-ecxal] archive.lar [-b NAME] [-s SIZE[M|k]]\n",name); + printf("\t[[[file1] file2] ...]\n\n"); printf("Examples:\n"); printf(" lar -c -s 32k -b bootblock myrom.lar foo nocompress:bar\n"); printf(" lar -a myrom.lar foo blob:baz\n"); @@ -121,7 +122,7 @@ int create_lar(const char *archivename, struct file *files) { - struct lar *lar = lar_new_archive(archivename, larsize); + struct lar *lar = lar_new_archive(archivename, get_larsize()); if (lar == NULL) { fprintf(stderr, "Unable to create %s as a LAR archive.\n", @@ -343,24 +344,21 @@ } /* size only makes sense when creating a lar */ - if (larmode != CREATE && larsize) { + if (larmode != CREATE && get_larsize()) { printf("Warning: size parameter ignored since " "not creating an archive.\n"); } - if (bootblock) { + if (larmode == CREATE && !get_larsize()) { + printf("When creating a LAR archive, " + "you must specify an archive size.\n"); + exit(1); + } - /* adding a bootblock only makes sense when creating a lar */ - if (larmode != CREATE) { - printf("Warning: bootblock parameter ignored since " - "not creating an archive.\n"); - } - - /* adding a bootblock only makes sense when creating a lar */ - if (!larsize) { - printf("When creating a LAR archive, you must specify an archive size.\n"); - exit(1); - } + /* adding a bootblock only makes sense when creating a lar */ + if (bootblock && larmode != CREATE) { + printf("Warning: bootblock parameter ignored since " + "not creating an archive.\n"); } if (optind < argc) { Modified: coreboot-v3/util/lar/stream.c =================================================================== --- coreboot-v3/util/lar/stream.c 2008-03-05 12:57:10 UTC (rev 631) +++ coreboot-v3/util/lar/stream.c 2008-03-05 14:51:35 UTC (rev 632) @@ -82,7 +82,7 @@ int size; int segment = 0; char *header; - char ename[64]; + char ename[MAX_PATHLEN]; int headers; char *temp; enum compalgo thisalgo; @@ -529,7 +529,7 @@ return 1; for(p = files ; p; p = p->next) { - if (!strcmp(p->name, filename)) + if (!strncmp(p->name, filename, strlen(p->name))) return 1; } @@ -560,17 +560,17 @@ break; filename = (char *) (ptr + sizeof(struct lar_header)); - total_size += sizeof(struct lar_header); if (file_in_list(files, filename)) { printf(" %s ", filename); + total_size += ntohl(header->offset); + total_size += ntohl(header->len); if (ntohl(header->compression) == ALGO_NONE) { printf("(%d bytes @0x%lx);", ntohl(header->len), (unsigned long)(ptr - lar->map) + ntohl(header->offset)); - total_size += ntohl(header->len); } else { printf("(%d bytes, %s compressed to %d bytes " "@0x%lx);", @@ -579,7 +579,6 @@ ntohl(header->len), (unsigned long)(ptr - lar->map) + ntohl(header->offset)); - total_size += ntohl(header->len); } printf("loadaddress 0x%#x entry 0x%#x\n", ntohl(header->loadaddress), @@ -603,8 +602,11 @@ } /* Print the total size */ - printf ("Total size = %d bytes (0x%x)\n", total_size, total_size); - + if (total_size >0) + printf("Total size = %dB %dKB (0x%x)\n", + total_size, total_size/1024, total_size); + else + printf("No matching lar entries found.\n"); } /** @@ -797,9 +799,10 @@ * Given a name, return the size of the header for that name. * * @param name header name + * @param new_pathlen pointer to the (possibly truncated) pathlen * @return header size */ -int hlen(char *pathname) +int header_len(char *pathname, int *new_pathlen) { int pathlen; int len; @@ -808,6 +811,8 @@ MAX_PATHLEN : strlen(pathname) + 1; len = sizeof(struct lar_header) + pathlen; len = (len + 15) & 0xFFFFFFF0; + if (new_pathlen!=NULL) + *new_pathlen = pathlen; return len; } @@ -827,7 +832,7 @@ offset = lar_empty_offset(lar); /* Figure out how big our header will be */ - size = get_bootblock_offset(lar->size) - offset - hlen(name) - 1; + size = get_bootblock_offset(lar->size) - offset - header_len(name,NULL) - 1; return size; } @@ -878,12 +883,8 @@ /* Find the beginning of the available space in the LAR */ offset = lar_empty_offset(lar); - pathlen = strlen(pathname) + 1 > MAX_PATHLEN ? - MAX_PATHLEN : strlen(pathname) + 1; - /* Figure out how big our header will be */ - hlen = sizeof(struct lar_header) + pathlen; - hlen = (hlen + 15) & 0xFFFFFFF0; + hlen = header_len(pathname, &pathlen); if (offset + hlen + complen >= get_bootblock_offset(lar->size)) { err("Not enough room in the LAR to add the file.\n");

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Re: [coreboot] Problems with VIA EPIA-ME6000
by Uwe Hermann 05 Mar '08

05 Mar '08

[Forwarding to list] On Tue, Mar 04, 2008 at 09:04:58PM -0500, mercury(a)wirebros.com wrote: > As we talk about images, do we need both of them (normal and fallback)? No, fallback-only will also work. Normal-only does _not_ work. > I managed to build working coreboot using fallback image only, no VGA bios. Yep. > The problem is that from power-up to first console log it takes roughly > 10seconds. I never managed to build coreboot with both images (normal, > fallback). Platform: EPIA MII-1.2GHz, 512MB ram. Hm, should work, at least it does for many other boards. What was the problem? > Please also see my comment in patch below; > > > > > On Tue, Mar 04, 2008 at 05:10:40PM +0100, Klaus Stammermann wrote: > >> Here the diff: > >> ----------------------------------------------------------------------------------------------------------------------------------- > >> Index: src/mainboard/via/epia-m/Options.lb > >> =================================================================== > >> --- src/mainboard/via/epia-m/Options.lb (Revision 3086) > >> +++ src/mainboard/via/epia-m/Options.lb (Arbeitskopie) > >> @@ -51,8 +51,8 @@ > >> ### > >> ### Build options > >> ### > >> -default CONFIG_PCI_ROM_RUN=0 > >> -default CONFIG_CONSOLE_VGA=0 > >> +default CONFIG_PCI_ROM_RUN=1 > >> +default CONFIG_CONSOLE_VGA=1 > > > > Looks ok. > > > > > >> ## > >> ## Build code for the fallback boot > >> Index: targets/via/epia-m/Config.lb > >> =================================================================== > >> --- targets/via/epia-m/Config.lb (Revision 3086) > >> +++ targets/via/epia-m/Config.lb (Arbeitskopie) > >> @@ -7,21 +7,21 @@ > >> option DEFAULT_CONSOLE_LOGLEVEL=8 > >> option CONFIG_CONSOLE_SERIAL8250=1 > >> > >> -option ROM_SIZE=256*1024 > >> +option ROM_SIZE=(256*1024)-(64*1024) > > > > OK, assuming you have a 256KB ROM chip and your VGA BIOS is 64KB. > > if it's less than 64k, do we pad it or adjust ROM_SIZE to be exactly > 256k-vgabios? You set ROM_SIZE to '(256*1024)-12345' if the VGA blob is exactly 12345 bytes, for example. No extra manual padding or such. But you prepend the 12345 bytes big VGA blob to coreboot.rom later (to make it exactly 256KB big). > >> option HAVE_OPTION_TABLE=1 > >> option CONFIG_ROM_PAYLOAD=1 > >> option HAVE_FALLBACK_BOOT=1 > >> #option CONFIG_COMPRESSED_PAYLOAD_NRV2B=1 > >> -option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 > >> +#option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 > > > > Why? > > > > > >> ### Compute the location and size of where this firmware image > >> ### (coreboot plus bootloader) will live in the boot rom chip. > >> ### > >> -option FALLBACK_SIZE=131072 > >> +option FALLBACK_SIZE=(96*1024) > > > what this parameter is for? > where is it used? Size of the fallback image. > > Not sure about this. I'd rather not change it unless really necessary > > (it isn't in this case, I think). > > > > > >> ## Coreboot C code runs at this location in RAM > >> option _RAMBASE=0x00004000 > >> @@ -31,18 +31,22 @@ > >> # > >> romimage "normal" > >> option USE_FALLBACK_IMAGE=0 > >> -#option ROM_IMAGE_SIZE=128*1024 > >> - option ROM_IMAGE_SIZE=64*1024 > >> +# option ROM_IMAGE_SIZE=(128*1024)-27312 > >> + option ROM_IMAGE_SIZE=(96*1024)-27312 > > > > This is wrong. > > > > ROM_IMAGE_SIZE is the maximum size the coreboot code can use (without > > payload, without VGA ROM, etc). > > > > Something like 64*1024 is usually ok. > We can use ROM_SECTION_SIZE to specify size of "normal" image, but we need > to offset it using ROM_SECTION_OFFSET=vgabiossize so I believe you need to > use these 2 variables. Hm, I wouldn't do that. I don't think ROM_SECTION_SIZE is meant to be modified, it's for internal use only. For prepending VGA images, using a correct ROM_SIZE should be enough, e.g. 'option ROM_SIZE=(256*1024)-(64*1024)' for a 64KB VGA image. If that's not enough it's probably a bug in the build system/configuration. > > > > > >> +# option ROM_IMAGE_SIZE=0xc000 > >> +# option ROM_SECTION_OFFSET=0x10000 > >> +# option ROM_SECTION_SIZE=0x18000 > >> option COREBOOT_EXTRA_VERSION=".0-Normal" > >> - payload $(HOME)/svn/payload.elf > >> + payload $(HOME)/Entwicklung/LinuxBIOS/VIA-BIOS/filo.small.elf > > > > Never used $(HOME) here, but I assume it works? If not, try > > /tmp/filo.elf and copy your payload there. > > > > > >> end > >> > >> romimage "fallback" > >> option USE_FALLBACK_IMAGE=1 > >> - #option ROM_IMAGE_SIZE=128*1024 > >> - option ROM_IMAGE_SIZE=60*1024 > >> +# option ROM_IMAGE_SIZE=(128*1024)-27312 > >> + option ROM_IMAGE_SIZE=(96*1024)-27312 > > > > Also wrong, see above. > Should this section be offset by 128k? No, don't think so, will be done internally, you don't have to manually fix it. > or buildrom will take care of it? Yes, but I think you mean 'targets/buildtarget'? > > > > > > >> +# option ROM_IMAGE_SIZE=0xc000 > >> option COREBOOT_EXTRA_VERSION=".0-Fallback" > >> - payload $(HOME)/svn/payload.elf > >> + payload $(HOME)/Entwicklung/LinuxBIOS/VIA-BIOS/filo.small.elf > >> end > >> > >> buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" > >> ----------------------------------------------------------------------------------------------------------------------------------- > > > > > >> In an earlier version I changed Config.lb in src dir to get VGA BIOS. > >> But now > >> it isn't included. If it is important, I could post it later. > > > > Plese post it. > > > > But the above patch comes from an 'svn diff' at the top-level directory, > > correct? I.e. all your current changes are in there? > > > > > >> > Also, where did you get your VGA ROM from? Using which tools > >> (awardeco, > >> > amideco, phnxdeco, other)? How big is it exactly? > >> > > >> On http://www.coreboot.org/VGA_support at bottom there is a perl script. > >> Using > >> this I got my VGABIOS. This is 60416 bytes big > > > > OK. Which vendor BIOS does the board have? Can you use > > awardeco/amideco/phnxdeco to get the VGA BIOS and compare it with the > > one from the script? Just to be sure that worked fine... > > > > > >> (optionsrom is 57344 bytes which I used at last). > > > > Huh, what's that? Where from? > > > > > >> filo.small.elf is 27312 bytes big. So don't wonder what number this is. > > > > Are you sure this is ok? The smallest usable FILO I've used so far is > > ca. 57 KB. Your 27 KB FILO looks _very_ small. > > > > Also, please use the latest version from > > > > % svn co svn://coreboot.org/filo/trunk/filo-0.5 > > > > Type 'make' (that will generate a Config file), then edit Config, then > > type make again. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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r631 - coreboot-v3/device
by svn＠coreboot.org 05 Mar '08

05 Mar '08

Author: hailfinger Date: 2008-03-05 13:57:10 +0100 (Wed, 05 Mar 2008) New Revision: 631 Modified: coreboot-v3/device/device.c coreboot-v3/device/pci_device.c Log: Fix two NULL pointer dereferences in device code. Add a nasty warning if one of the cases triggers because that should not happen. We should fix the cases where the warning triggers. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/device/device.c =================================================================== --- coreboot-v3/device/device.c 2008-03-03 16:14:15 UTC (rev 630) +++ coreboot-v3/device/device.c 2008-03-05 12:57:10 UTC (rev 631) @@ -278,8 +278,13 @@ struct device *curdev; printk(BIOS_SPEW, "%s: %s(%s) read_resources bus %d link: %d\n", - __func__, bus->dev->dtsname, dev_path(bus->dev), + __func__, + (bus->dev ? bus->dev->dtsname : "No dtsname for NULL device"), + (bus->dev ? dev_path(bus->dev) : "No path for NULL device"), bus->secondary, bus->link); + if (!bus->dev) + printk(BIOS_WARNING, "%s: ERROR: bus->dev is NULL!\n", + __func__); /* Walk through all devices and find which resources they need. */ for (curdev = bus->children; curdev; curdev = curdev->sibling) { Modified: coreboot-v3/device/pci_device.c =================================================================== --- coreboot-v3/device/pci_device.c 2008-03-03 16:14:15 UTC (rev 630) +++ coreboot-v3/device/pci_device.c 2008-03-05 12:57:10 UTC (rev 631) @@ -1101,7 +1101,7 @@ dev = pci_probe_dev(dev, bus, devfn); printk(BIOS_SPEW, "PCI: pci_scan_bus pci_probe_dev returns dev %p(%s)\n", - dev, dev->dtsname); + dev, dev ? dev->dtsname : "None (not found)"); /* If this is not a multi function device, or the device is * not present don't waste time probing another function.

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[PATCH] v3: Fix one NULL pointer dereference, add code to debug another one.
by Carl-Daniel Hailfinger 05 Mar '08

05 Mar '08

Fix one NULL pointer dereference, add code to debug another one. Don't commit yet, I'd rather apply a fix for the NULL pointer than just debugging it. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: device/device.c =================================================================== --- device/device.c (Revision 630) +++ device/device.c (Arbeitskopie) @@ -277,8 +277,9 @@ { struct device *curdev; - printk(BIOS_SPEW, "%s: %s(%s) read_resources bus %d link: %d\n", - __func__, bus->dev->dtsname, dev_path(bus->dev), + printk(BIOS_SPEW, "%s: bus->dev %p, bus->dev->dtsname %p, %s(%s) read_resources bus %d link: %d\n", + __func__, bus->dev, bus->dev->dtsname, + bus->dev->dtsname, dev_path(bus->dev), bus->secondary, bus->link); /* Walk through all devices and find which resources they need. */ Index: device/pci_device.c =================================================================== --- device/pci_device.c (Revision 630) +++ device/pci_device.c (Arbeitskopie) @@ -1101,7 +1101,7 @@ dev = pci_probe_dev(dev, bus, devfn); printk(BIOS_SPEW, "PCI: pci_scan_bus pci_probe_dev returns dev %p(%s)\n", - dev, dev->dtsname); + dev, dev ? dev->dtsname : "None (not found)"); /* If this is not a multi function device, or the device is * not present don't waste time probing another function. -- http://www.hailfinger.org/

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make problem
by Klaus Stammermann 05 Mar '08

05 Mar '08

Hi there On my EPIA-ME6000 I try to get some free space to insert VGA BIOS. But I get often this error message: "XIP_ROM_BASE is not a multiple of XIP_ROM_SIZE". Could anyone explain what this means? What do I have looking for to get some free space in my image? An overview of all possible options and their description would be very nice. Is there something like that available? Greetings Klaus

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PIC, APIC, XAPIC and XIOAPIC
by Feng, Libo 05 Mar '08

05 Mar '08

Hi, all, I am a little confused by PIC, APIC, XAPIC and XIOAPIC. In LB stage, only PIC mode is applied, isn't it? However, I remember some people of LB community told me there was no ISR except the debug ISR during LB. So does this mean it totally unnecessary to setup PIC via C00h/C001h IO port in LB? APIC is setup only after OS runs and gets the interrupt routing from MPTable or ACPI table, is it correct? Then, what difference between APIC and XAPIC? Some documents say APIC has MMIO space registers at FEC00000h while XAPIC has PCI configuration space registers. But some documents seems to refer the same controller by APIC and XAPIC. And XAPIC and XIOAPIC are the same things, aren’t they? Please help me out, I am completely confused by these terms. Best Regards 丰立波 Feng Libo @ AMD Ext: 20906 Mobile Phone: 13683249071 Office Phone: 0086-010-62801406

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3.3V PCI Post Card
by Phani Babu Giddi 04 Mar '08

04 Mar '08

Hello All, Is anybody aware of a 3.3V PCI Post Card. I happen to purchase a PCI Post Card from ElstonSystems and looks like it operates on 5V. Unfortunately the Geode DB800 board that I have doesnt provide 5V. Regards, Phani

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r3127 - trunk/util/superiotool
by svn＠coreboot.org 04 Mar '08

04 Mar '08

Author: uwe Date: 2008-03-04 18:21:04 +0100 (Tue, 04 Mar 2008) New Revision: 3127 Modified: trunk/util/superiotool/README Log: Drop some duplicate documentation from the README. The manpage and 'superiotool --help' already provide the same information (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/README =================================================================== --- trunk/util/superiotool/README 2008-03-04 16:29:54 UTC (rev 3126) +++ trunk/util/superiotool/README 2008-03-04 17:21:04 UTC (rev 3127) @@ -30,15 +30,8 @@ Usage ----- - $ superiotool [-d] [-e] [-l] [-V] [-v] [-h] +Please read the superiotool(1) manpage or type 'superiotool --help'. - -d | --dump Dump Super I/O register contents - -e | --extra-dump Dump secondary registers too (e.g. EC registers) - -l | --list-supported Show the list of supported Super I/O chips - -V | --verbose Verbose mode - -v | --version Show the superiotool version - -h | --help Show a short help text - Per default (no options) superiotool will just probe for a Super I/O and print its vendor, name, ID, revision, and config port.

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patch: dbe62
by ron minnich 04 Mar '08

04 Mar '08

This is probably just about done save for dram timing. ron

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coreboot March 2008