coreboot March 2008

coreboot@coreboot.org

75 participants
382 discussions

[PATCH] flashrom: Add missing license to layout.c
by Uwe Hermann 04 Mar '08

04 Mar '08

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

r3126 - trunk/util/flashrom
by svn＠coreboot.org 04 Mar '08

04 Mar '08

Author: uwe Date: 2008-03-04 17:29:54 +0100 (Tue, 04 Mar 2008) New Revision: 3126 Modified: trunk/util/flashrom/layout.c Log: Add missing license header to layout.c. The file was written by Stefan Reinauer for coresystems GmbH in 2005, as confirmed on IRC. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/layout.c =================================================================== --- trunk/util/flashrom/layout.c 2008-03-01 19:13:50 UTC (rev 3125) +++ trunk/util/flashrom/layout.c 2008-03-04 16:29:54 UTC (rev 3126) @@ -1,3 +1,23 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2005-2008 coresystems GmbH + * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <stdio.h> #include <stdlib.h> #include <string.h>

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VGA and Asus a8v-e_se
by Jonathan Rogers 04 Mar '08

04 Mar '08

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 I have successfully built coreboot-v2-3119 with a FILO payload and booted my Asus a8v-e_se mainboard with the resulting image. However, VGA is not initialized and I can only interact with it via serial console. The video card is a PNY Nvidia 7900GS PCIe card. I can boot Linux from my SATA disk normally except a few devices aren't working, most notably the video card. Neither Linux nor the proprietary Nvidia driver see any VGA devices. When I reflash the legacy Award BIOS I copied from the BIOS before installing the coreboot image, everything returns to normal and the VGA card works. I tried to follow the wiki page http://www.coreboot.org/VGA_support, so I opened src/mainboard/asus/a8v-e_se/Options.lb. However, that file contains the following lines instead of ones starting with "option" as in the wiki: #VGA default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 So, I'm not sure what that means. Has the configuration method changed? Do the default lines enable those features? During boot, I see many initialization messages on the serial console from coreboot, but nothing about VGA or PCI_ROM_RUN. The wiki page http://www.coreboot.org/ASUS_A8V-E_SE_Build_Tutorial doesn't have much in the way of instructions, but it does say that PCIe video cards work. Any pointers would be appreciated. Jonathan Rogers -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFHymLSMs6f82yVS5wRAhh3AJ9LBivG+U+ZINyMs2xVYb+5b5/WQgCgq/ch TAZzvfZzrAW7cqPfNGcw1nc= =Kki+ -----END PGP SIGNATURE-----

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[LinuxBIOS] W39V040BPZ or vt8237. Flashing problems.
by Adam Talbot 04 Mar '08

04 Mar '08

Have three motherboards running cn700, VT8237 chips set. All three boards have W39V040BPZ bios chips. I can not program them with flashrom. Flashrom see the chip as W39V040B. Flashrom start on the flash and just sits there. When flashed with the -V option I can see the memory address is not changing. But, big problem is the fact that the chip does get a bit flashed, as, I can no longer boot. So there is something happening. Looking at the data sheet for the W39V040B, all the PZ gives me is the PLCC package and lead free. So, is this a problem with the vt8237 south bridge? Where should I go to start debugging? -Adam

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coreboot system analyzer
by Carl-Daniel Hailfinger 04 Mar '08

04 Mar '08

This is a ready-made script which gathers all information about a system we could want to evaluate whether porting is possible and/or easy. The idea behind it is to get loads of people to run the script and help us analyze coverage of flashrom and superiotool, together with board distribution among willing testers. In the future, this could include the ICH GPIO dumper, the K8 resource dumper, the MCP55 configuration dumper and a few other utilities. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> -- http://www.hailfinger.org/ #!/bin/bash # Coreboot system information gathering script # This is very Linux-specific right now. # # This script is Copyright (C) 2008 Carl-Daniel Hailfinger # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License along # with this program; if not, write to the Free Software Foundation, Inc., # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. mkdir coreboot_data parentdir=`pwd` cd coreboot_data lspci -vvvnnxxx >lspci-vvvnnxxx.txt lspci -t >lspci-t.txt dmidecode >dmidecode.txt svn co svn://linuxbios.org/repos/trunk/util/flashrom cd flashrom make cd - ./flashrom/flashrom -V >flashrom.txt rm -rf flashrom svn co svn://linuxbios.org/repos/trunk/util/superiotool cd superiotool make cd - ./superiotool/superiotool -d -e -V >superiotool.txt rm -rf superiotool cat /proc/ioports >ioports.txt cat /proc/iomem >iomem.txt cat /proc/interrupts >interrupts.txt cat /proc/cpuinfo >cpuinfo.txt acpidump >acpidump.txt cd $parentdir tar cjf coreboot_data.tar.bz2 coreboot_data/ echo echo All done. Please send coreboot_data.tar.bz2 to dumps(a)coreboot.org. Thanks.

4 4

Video ROM and VSA for Geode LX
by Phani Babu Giddi 03 Mar '08

03 Mar '08

Hi, I am having trouble getting AMD's DB800 board to boot Linux with FILO. I am using buildrom to build the image. Now for debugging purposses I want to get Video ROM in coreboot image. Has anybody tried patching Video ROM to coreboot image for Geode LX, if so which part of the BIOS image does this fit in. Is it after VSA or before that ? I think I have to reduce ROM_SIZE by the size of VSA and Video ROM. Is there any other way I can debug coreboot/filo ? Can all the post codes and other stuff be seen on serial console ? Regards, Phani

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Two questions about 690/600
by Feng, Libo 03 Mar '08

03 Mar '08

Hi, all, Marc and Yinghai, We are adapting LB for AMD Herring board based on Turion 64x2 and 690/600. Now we have two questions, could you give us some guide? 1. How to enable the VGA controller on 690? LB has detected the controller, from the previous experience, we seem to need a VBIOS to initialize the controller. But the controller is integrated into the 690, can we handle it just like an onboard controller and put VBIOS at 0xfff80000 and run VBIOS in the function of dev_initialize? 2. 600 is attached to 690 via A-Link, from my understanding, 600 should be on another PCI bus, but from the LB trace, it seems 600 is still on PCI bus 0. Why? The 690 Datasheet says NB/SB Link P2P bridge is hidden by default, is this the reason? Thanks. Best Regards 丰立波 Feng Libo @ AMD Ext: 20906 Mobile Phone: 13683249071 Office Phone: 0086-010-62801406

3 2

r630 - coreboot-v3/util
by svn＠coreboot.org 03 Mar '08

03 Mar '08

Author: uwe Date: 2008-03-03 17:14:15 +0100 (Mon, 03 Mar 2008) New Revision: 630 Modified: coreboot-v3/util/ Log: Missing linuxbios.org -> coreboot.org rename in v3 svn:externals (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Property changes on: coreboot-v3/util ___________________________________________________________________ Modified: svn:externals - flashrom svn://linuxbios.org/repos/trunk/util/flashrom nvramtool svn://linuxbios.org/repos/trunk/util/nvramtool superiotool svn://linuxbios.org/repos/trunk/util/superiotool + flashrom svn://coreboot.org/repos/trunk/util/flashrom nvramtool svn://coreboot.org/repos/trunk/util/nvramtool superiotool svn://coreboot.org/repos/trunk/util/superiotool

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Probe missing on W49F002U
by Jun Ma 03 Mar '08

03 Mar '08

Hi, all. I downloaded flashrom from http://www.openbios.org/viewvc/trunk/util/flashrom.tar.gz?view=tar, also it was built correctly, when I scp it to an SIS530/SIS5595 board with debian-4.0r2, it just can't recognize my Winbond W49G002U EEPROM, here comes the verbose log: Sis530:~# ./flashrom -c W49F002U Calibrating delay loop... OK. No coreboot table found. Found chipset "SIS5595", enabling flash write... OK. No EEPROM/flash device found. Sis530:~# ./flashrom -R flashrom r Sis530:~# ./flashrom --version flashrom r Sis530:~# ./flashrom -V -r Calibrating delay loop... 59M loops per second. OK. No coreboot table found. Found chipset "SIS5595", enabling flash write... OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Probing for Am29LV040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for At29C040A, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for At29C020, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for At49F002(N), 256 KB probe_jedec: id1 0xff, id2 0xff Probing for At49F002(N)T, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for EN29F002(A)(N)T, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for EN29F002(A)(N)B, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for MBM29F400TC, 512 KB probe_m29f400bt: id1 0xff, id2 0xff Probing for MX29F002, 256 KB probe_29f002: id1 0xff, id2 0xff Probing for MX25L4005, 512 KB generic_spi_command called, but no SPI chipset detected Probing for MX25L8005, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for MX25L3205, 4096 KB generic_spi_command called, but no SPI chipset detected Probing for S25FL016A, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for SST25VF040B, 512 KB generic_spi_command called, but no SPI chipset detected Probing for SST25VF016B, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for SST29EE020A, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for SST28SF040A, 512 KB probe_28sf040: id1 0xff, id2 0xff Probing for SST39SF010A, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for SST39SF020A, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for SST39SF040, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for SST39VF020, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF040B, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF040, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF020A, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF002A/B, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF003A/B, 384 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF004A/B, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF008A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF004C, 512 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF008C, 1024 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF016C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF160C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for Pm49FL002, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for Pm49FL004, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for Pm25LV512, 64 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV010, 128 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV020, 256 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV040, 512 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV080B, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV016B, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for W29C011, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for W29C040P, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for W29C020C, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for W29EE011, 128 KB probe_w29ee011: id1 0xff, id2 0xff Probing for W49F002U, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for W49V002A, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for W49V002FA, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for W39V040FA, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for W39V040A, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for W39V040B, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for W39V080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for W25x10, 128 KB generic_spi_command called, but no SPI chipset detected Probing for W25x20, 256 KB generic_spi_command called, but no SPI chipset detected Probing for W25x40, 512 KB generic_spi_command called, but no SPI chipset detected Probing for W25x80, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for M29F002B, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FW040, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for M29W040B, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for M29F002T/NT, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for M29F400BT, 512 KB probe_m29f400bt: id1 0xff, id2 0xff Probing for M50FLW040A, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FLW040B, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FLW080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FLW080B, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FW080, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FW016, 2048 KB probe_jedec: id1 0xff, id2 0xff Probing for M50LPW116, 2048 KB probe_jedec: id1 0xff, id2 0xff Probing for M29W010B, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for M29F040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Probing for M25P05-A, 64 KB generic_spi_command called, but no SPI chipset detected Probing for M25P10-A, 128 KB generic_spi_command called, but no SPI chipset detected Probing for M25P20, 256 KB generic_spi_command called, but no SPI chipset detected Probing for M25P40, 512 KB generic_spi_command called, but no SPI chipset detected Probing for M25P80, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for M25P16, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for M25P32, 4096 KB generic_spi_command called, but no SPI chipset detected Probing for M25P64, 8192 KB generic_spi_command called, but no SPI chipset detected Probing for M25P128, 16384 KB generic_spi_command called, but no SPI chipset detected Probing for 82802ab, 512 KB probe_82802ab: id1 0xff, id2 0xff Probing for 82802ac, 1024 KB probe_82802ab: id1 0xff, id2 0xff Probing for F49B002UA, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for LHF00L04, 1024 KB probe_lhf00l04: id1 0xff, id2 0xff Probing for S29C51001T, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for S29C51002T, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for S29C51004T, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for S29C31004T, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for EON unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for MX unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for PMC unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for SST unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for ST unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected No EEPROM/flash device found. Sis530:~# After quick reading of your source code, I saw this probing function: int probe_jedec(struct flashchip *flash) { volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ *(volatile uint8_t *)(bios + 0x5555) = 0xAA; myusec_delay(10); *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; myusec_delay(10); *(volatile uint8_t *)(bios + 0x5555) = 0x90; /* Older chips may need up to 100 us to respond. The ATMEL 29C020 * needs 10 ms according to the data sheet, but it has been tested * to work reliably with 20 us. Allow a factor of 2 safety margin. */ myusec_delay(40); /* Read product ID */ id1 = *(volatile uint8_t *)bios; id2 = *(volatile uint8_t *)(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; id1 = *(volatile uint8_t *)(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; id2 = *(volatile uint8_t *)(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ *(volatile uint8_t *)(bios + 0x5555) = 0xAA; myusec_delay(10); *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; myusec_delay(10); *(volatile uint8_t *)(bios + 0x5555) = 0xF0; myusec_delay(40); printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, largeid1, largeid2); if (largeid1 == flash->manufacture_id && largeid2 == flash->model_id) return 1; return 0; } Seems flashrom routing got 0xff, 0xff on largeid1, largeid2. Has anybody tested this routing on SIS530? Thanks. -- FIXME if it is wrong.

4 8

LinuxBios on Tyan Tiger S2460 760MP/AMD766
by Joop Boonen 03 Mar '08

03 Mar '08

All, I've bought a SATAII controller (SIL3124-2) But it doesn't seem to work in combination with the bios (1.05) on my Tyan main board (Isn't recognised in the boot process). Therefore I'm thinking of putting LinuxBios on the main board. has anyone succeeded in putting LinuxBios on this main board? Regards, Joop Boonen.

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coreboot March 2008