coreboot March 2008

coreboot@coreboot.org

75 participants
382 discussions

s2881 - IDE path problem in GRUB if SATA is enabled
by Baski 08 Mar '08

08 Mar '08

My Config - tyan 2881 + FILO payload + ubuntu on IDE-0 + LBv2 So far I've been using this setup with onboard SATA disabled. Today I opened the jumper and enabled the SATA. It stopped at Grub console. I manually entered the path for the boot drive "root (hd0,0)", but it says something like hda1:/boot/vmlinuz.... 'Drive 0 not present'. The original BIOS boots ok. Any ideas? TIA- Baski --------------------------------- Never miss a thing. Make Yahoo your homepage.

2 2

OLPC A-Test and flash compatibility
by Carl-Daniel Hailfinger 08 Mar '08

08 Mar '08

Hi, since the laptop.org lists are mostly software-oriented nowadays and they dropped support for A-Test boards long ago, I'm going to ask here: Does anybody know whether I can also flash LPC SST49LF080A in the PLCC32 socket on that board or am I limited to LPC flash? Booting from that flash chip is not necessary, flashing the chip is my only goal right now. Regards, Carl-Daniel -- http://www.hailfinger.org/

3 3

[BUILDROM] Fix memtest bug
by Jordan Crouse 07 Mar '08

07 Mar '08

Fix a bug in memtest - apparently we haven't _ever_ passed the CFLAGS correctly. Doesn't anybody ever try the memtest payload? :) Jordan -- Jordan Crouse Systems Software Development Engineer Advanced Micro Devices, Inc.

2 2

r135 - buildrom-devel/packages/memtest
by svn＠coreboot.org 07 Mar '08

07 Mar '08

Author: jcrouse Date: 2008-03-07 17:22:35 +0100 (Fri, 07 Mar 2008) New Revision: 135 Modified: buildrom-devel/packages/memtest/memtest.mk Log: [BUILDROM] Fix typo in memtest Fix a typo in memtest that let our good friend _stack_chk_fail get through. How did this buglet last this long? Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: buildrom-devel/packages/memtest/memtest.mk =================================================================== --- buildrom-devel/packages/memtest/memtest.mk 2008-02-26 04:38:29 UTC (rev 134) +++ buildrom-devel/packages/memtest/memtest.mk 2008-03-07 16:22:35 UTC (rev 135) @@ -36,7 +36,7 @@ $(MEMTEST_SRC_DIR)/memtest: $(MEMTEST_CONFIG_TARGET) @ echo "Building memtest..." - @ $(MAKE) -C $(MEMTEST_SRC_DIR) AS="$(AS) $(CROSS_ASFLAGS)" CC="$(CC) $(CROSS_CFLAGS)" LD="$(LD) $(CROSS_LDFLAGS)" CCFLAGS="$(CFLAGS)" memtest > $(MEMTEST_BUILD_LOG) 2>&1 + @ $(MAKE) -C $(MEMTEST_SRC_DIR) AS="$(AS) $(CROSS_ASFLAGS)" CC="$(CC) $(CROSS_CFLAGS)" LD="$(LD) $(CROSS_LDFLAGS)" CFLAGS="$(CFLAGS)" memtest > $(MEMTEST_BUILD_LOG) 2>&1 $(MEMTEST_STAMP_DIR) $(MEMTEST_LOG_DIR): @ mkdir -p $@

1 0

Geode GX / CS5535 / PIC
by Martin Trautmann 07 Mar '08

07 Mar '08

Hi all, I'm lost how to build a new BIOS for a Geode GX / CS5535 board. http://www.coreboot.org/AMD_Geode_Porting_Guide is focused on the Geode LX and a db800 reference board. I've found the CS5535 sources at http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/sou… but don't know how to use them. The CPU is a Geode GX 500 http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/cpu… The board is an AMD Personal Internet Communicator (PIC, now DecTOP): http://50x15.amd.com/en-us/sol_tech_dectop.aspx http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_233… Unfortunately I do not know any access to the board's schematics. AMD has cancelled this project. I'm afraid that its docu is lost. coreboot v3 does not include the GX/CS5535 yet. I don't know whether I should learn how to use v2 or whether v3 will include those soon. Thanks for any help, Martin

5 13

ASUS A8V-E Deluxe now supported
by Uwe Hermann 07 Mar '08

07 Mar '08

Hi, I'm happy to announce that the ASUS A8V-E Deluxe board works pretty well in coreboot v2 already. I haven't even touched more than 1 (in words: one) lines of code. This is all thanks to Rudolf Marek's great work on the ASUS A8V-E SE board, which is very similar to this one. I've posted the full status table and a small build tutorial in the wiki: http://www.coreboot.org/ASUS_A8V-E_Deluxe_Build_Tutorial It boots up to a Linux login prompt, CPU, RAM, SATA (port 1), audio, ethernet, USB, VGA, and lots of other stuff work fine. Even 'poweroff' and 'reboot' work, probably thanks to the ACPI implementation by Rudolf. There are some TODOs left (IDE seems to have a problem, SATA port 2 also, and a few other things hasn't yet been tested), I'll work on fixing them in the next few days or so. Thanks, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 1

patch: cumulative LX changes
by ron minnich 07 Mar '08

07 Mar '08

This is all from work last night. I'd lke to get these in. Thanks ron

2 4

r638 - in coreboot-v3: mainboard/amd/norwich mainboard/artecgroup/dbe61 mainboard/artecgroup/dbe62 southbridge/amd/cs5536
by svn＠coreboot.org 07 Mar '08

07 Mar '08

Author: rminnich Date: 2008-03-07 07:33:05 +0100 (Fri, 07 Mar 2008) New Revision: 638 Modified: coreboot-v3/mainboard/amd/norwich/stage1.c coreboot-v3/mainboard/artecgroup/dbe61/initram.c coreboot-v3/mainboard/artecgroup/dbe61/stage1.c coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h coreboot-v3/mainboard/artecgroup/dbe62/stage1.c coreboot-v3/southbridge/amd/cs5536/cs5536.h coreboot-v3/southbridge/amd/cs5536/stage1.c Log: Make cs5536_setup_onchipuart() handle both UARTs and add missing break in dbe61 initram. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested on dbe62. I had to run cs5536/stage1.c through indent -kr -i8 because emacs is somehow confused by parts of it. Weird. indent made some parts ugly, at least to my eyes. Oh well. Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/amd/norwich/stage1.c =================================================================== --- coreboot-v3/mainboard/amd/norwich/stage1.c 2008-03-07 01:20:36 UTC (rev 637) +++ coreboot-v3/mainboard/amd/norwich/stage1.c 2008-03-07 06:33:05 UTC (rev 638) @@ -42,7 +42,7 @@ * early MSR setup for the CS5536. We do this early for debug. * Real setup should be done in chipset init via dts settings. */ - cs5536_setup_onchipuart(); + cs5536_setup_onchipuart(1); } void mainboard_pre_payload(void) Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-03-07 01:20:36 UTC (rev 637) +++ coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-03-07 06:33:05 UTC (rev 638) @@ -102,6 +102,7 @@ for (i = 0; i < ARRAY_SIZE(spd_table); i++) { if (spd_table[i].address == address) { ret = spd_table[i].data; + break; } } Modified: coreboot-v3/mainboard/artecgroup/dbe61/stage1.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/stage1.c 2008-03-07 01:20:36 UTC (rev 637) +++ coreboot-v3/mainboard/artecgroup/dbe61/stage1.c 2008-03-07 06:33:05 UTC (rev 638) @@ -59,7 +59,7 @@ * NOTE: Must do this AFTER the early_setup! It is counting on some * early MSR setup for the CS5536. */ - cs5536_setup_onchipuart(); + cs5536_setup_onchipuart(2); } void mainboard_pre_payload(void) Modified: coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h 2008-03-07 01:20:36 UTC (rev 637) +++ coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h 2008-03-07 06:33:05 UTC (rev 638) @@ -20,8 +20,7 @@ #include <pirq_routing.h> /* Number of slots and devices in the PIR table */ -#error IRQ_SLOT_COUNT does not match PIR table contents, IRQ routing setup will access uninitialied memory -#define IRQ_SLOT_COUNT 5 +#define IRQ_SLOT_COUNT 3 /* Platform IRQs */ #define PIRQA 10 Modified: coreboot-v3/mainboard/artecgroup/dbe62/stage1.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/stage1.c 2008-03-07 01:20:36 UTC (rev 637) +++ coreboot-v3/mainboard/artecgroup/dbe62/stage1.c 2008-03-07 06:33:05 UTC (rev 638) @@ -58,7 +58,7 @@ * NOTE: Must do this AFTER the early_setup! It is counting on some * early MSR setup for the CS5536. */ - cs5536_setup_onchipuart2(); + cs5536_setup_onchipuart(2); } void mainboard_pre_payload(void) Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.h =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.h 2008-03-07 01:20:36 UTC (rev 637) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.h 2008-03-07 06:33:05 UTC (rev 638) @@ -443,8 +443,7 @@ /* Function prototypes */ void cs5536_disable_internal_uart(void); -void cs5536_setup_onchipuart(void); -void cs5536_setup_onchipuart2(void); +void cs5536_setup_onchipuart(int uart); void cs5536_stage1(void); #endif /* SOUTHBRIDGE_AMD_CS5536_CS5536_H */ Modified: coreboot-v3/southbridge/amd/cs5536/stage1.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/stage1.c 2008-03-07 01:20:36 UTC (rev 637) +++ coreboot-v3/southbridge/amd/cs5536/stage1.c 2008-03-07 06:33:05 UTC (rev 638) @@ -49,10 +49,10 @@ /* TODO: unsigned char -> u8? */ #if CS5536_GLINK_PORT_NUM <= 4 msr.lo = CS5536_DEV_NUM << - (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8); + (unsigned char) ((CS5536_GLINK_PORT_NUM - 1) * 8); #else msr.hi = CS5536_DEV_NUM << - (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8); + (unsigned char) ((CS5536_GLINK_PORT_NUM - 5) * 8); #endif wrmsr(GLPCI_ExtMSR, msr); @@ -90,11 +90,11 @@ } static const struct msrinit msr_table[] = { - {MDD_LBAR_SMB, {.hi = 0x0000f001, .lo = SMBUS_IO_BASE}}, - {MDD_LBAR_GPIO, {.hi = 0x0000f001, .lo = GPIO_IO_BASE}}, - {MDD_LBAR_MFGPT, {.hi = 0x0000f001, .lo = MFGPT_IO_BASE}}, - {MDD_LBAR_ACPI, {.hi = 0x0000f001, .lo = ACPI_IO_BASE}}, - {MDD_LBAR_PMS, {.hi = 0x0000f001, .lo = PMS_IO_BASE}}, + {MDD_LBAR_SMB, {.hi = 0x0000f001,.lo = SMBUS_IO_BASE}}, + {MDD_LBAR_GPIO, {.hi = 0x0000f001,.lo = GPIO_IO_BASE}}, + {MDD_LBAR_MFGPT, {.hi = 0x0000f001,.lo = MFGPT_IO_BASE}}, + {MDD_LBAR_ACPI, {.hi = 0x0000f001,.lo = ACPI_IO_BASE}}, + {MDD_LBAR_PMS, {.hi = 0x0000f001,.lo = PMS_IO_BASE}}, }; /** @@ -147,15 +147,15 @@ * Disable and reset them and configure them later (SIO init). */ msr = rdmsr(MDD_UART1_CONF); - msr.lo = 1; /* Reset */ + msr.lo = 1; /* Reset */ wrmsr(MDD_UART1_CONF, msr); - msr.lo = 0; /* Disable */ + msr.lo = 0; /* Disable */ wrmsr(MDD_UART1_CONF, msr); msr = rdmsr(MDD_UART2_CONF); - msr.lo = 1; /* Reset */ + msr.lo = 1; /* Reset */ wrmsr(MDD_UART2_CONF, msr); - msr.lo = 0; /* Disable */ + msr.lo = 0; /* Disable */ wrmsr(MDD_UART2_CONF, msr); } @@ -182,7 +182,7 @@ * * See page 412 of the AMD Geode CS5536 Companion Device data book. */ -void cs5536_setup_onchipuart(void) +void cs5536_setup_onchipuart1(void) { struct msr msr; @@ -238,7 +238,8 @@ outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); /* Set: GPIO 3 + 3 Pull Up (0x18) */ - outl(GPIOL_3_SET | GPIOL_4_SET, GPIO_IO_BASE + GPIOL_PULLUP_ENABLE); + outl(GPIOL_3_SET | GPIOL_4_SET, + GPIO_IO_BASE + GPIOL_PULLUP_ENABLE); /* set address to 3F8 */ msr = rdmsr(MDD_LEG_IO); @@ -255,7 +256,19 @@ wrmsr(MDD_UART2_CONF, msr); } +void cs5536_setup_onchipuart(int uart) +{ + switch (uart) { + case 1: + cs5536_setup_onchipuart1(); + break; + case 2: + cs5536_setup_onchipuart2(); + break; + } +} + /** * Board setup. *

1 0

[PATCH] v3: PIRQ table cosmetics
by Carl-Daniel Hailfinger 07 Mar '08

07 Mar '08

PIRQ table cosmetics/cleanup. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-db800/mainboard/amd/norwich/irq_tables.h =================================================================== --- LinuxBIOSv3-db800/mainboard/amd/norwich/irq_tables.h (Revision 630) +++ LinuxBIOSv3-db800/mainboard/amd/norwich/irq_tables.h (Arbeitskopie) @@ -17,17 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <lib.h> -#include <console.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#include <msr.h> -#include <io.h> #include <pirq_routing.h> -#include <amd_geodelx.h> -#include "../../../southbridge/amd/cs5536/cs5536.h" /* Number of slots and devices in the PIR table */ #define SLOT_COUNT 6 @@ -83,13 +73,19 @@ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* Checksum */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ - {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */ - {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */ - {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */ - {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */ + /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* CPU */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + /* chipset */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, + /* slot1 */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, + /* slot2 */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, + /* slot3 */ + {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, + /* slot4 */ + {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, } }; Index: LinuxBIOSv3-db800/mainboard/artecgroup/dbe62/irq_tables.h =================================================================== --- LinuxBIOSv3-db800/mainboard/artecgroup/dbe62/irq_tables.h (Revision 630) +++ LinuxBIOSv3-db800/mainboard/artecgroup/dbe62/irq_tables.h (Arbeitskopie) @@ -17,20 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <lib.h> -#include <console.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#include <msr.h> -#include <io.h> #include <pirq_routing.h> -#include <amd_geodelx.h> -#include "../../../southbridge/amd/cs5536/cs5536.h" +/* Number of slots and devices in the PIR table */ +#warning SLOT_COUNT does not match PIR table contents +#define SLOT_COUNT 5 - /* Platform IRQs */ #define PIRQA 10 #define PIRQB 11 @@ -52,7 +44,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * 5, /* Max. number of devices on the bus */ + 32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -62,9 +54,12 @@ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ - {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* CPU */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + /* chipset */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, + /* ethernet */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, } }; Index: LinuxBIOSv3-db800/mainboard/pcengines/alix1c/irq_tables.h =================================================================== --- LinuxBIOSv3-db800/mainboard/pcengines/alix1c/irq_tables.h (Revision 630) +++ LinuxBIOSv3-db800/mainboard/pcengines/alix1c/irq_tables.h (Arbeitskopie) @@ -19,6 +19,8 @@ #include <pirq_routing.h> +/* Number of slots and devices in the PIR table */ +#define SLOT_COUNT 5 /* Platform IRQs */ #define PIRQA 11 @@ -71,7 +73,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * 5, /* Max. number of devices on the bus */ + 32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ -- http://www.hailfinger.org/

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r637 - in coreboot-v3: arch/x86 mainboard/amd/norwich mainboard/artecgroup/dbe61 mainboard/artecgroup/dbe62 mainboard/pcengines/alix1c
by svn＠coreboot.org 07 Mar '08

07 Mar '08

Author: hailfinger Date: 2008-03-07 02:20:36 +0100 (Fri, 07 Mar 2008) New Revision: 637 Modified: coreboot-v3/arch/x86/pirq_routing.c coreboot-v3/mainboard/amd/norwich/irq_tables.h coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.h coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h coreboot-v3/mainboard/pcengines/alix1c/irq_tables.h Log: PIRQ table cosmetics/cleanup. Bugfixes and #error for uninitialized memory accesses. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: coreboot-v3/arch/x86/pirq_routing.c =================================================================== --- coreboot-v3/arch/x86/pirq_routing.c 2008-03-06 23:33:59 UTC (rev 636) +++ coreboot-v3/arch/x86/pirq_routing.c 2008-03-07 01:20:36 UTC (rev 637) @@ -37,16 +37,6 @@ printk(BIOS_INFO, "Checking IRQ routing table consistency...\n"); -#if defined(IRQ_SLOT_COUNT) - if (sizeof(struct irq_routing_table) != rt->size) { - printk_warning("Inconsistent IRQ routing table size (0x%x/0x%x)\n", - sizeof(struct irq_routing_table), - rt->size - ); - rt->size=sizeof(struct irq_routing_table); - } -#endif - for (i = 0; i < rt->size; i++) sum += addr[i]; Modified: coreboot-v3/mainboard/amd/norwich/irq_tables.h =================================================================== --- coreboot-v3/mainboard/amd/norwich/irq_tables.h 2008-03-06 23:33:59 UTC (rev 636) +++ coreboot-v3/mainboard/amd/norwich/irq_tables.h 2008-03-07 01:20:36 UTC (rev 637) @@ -17,20 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <lib.h> -#include <console.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#include <msr.h> -#include <io.h> #include <pirq_routing.h> -#include <amd_geodelx.h> -#include "../../../southbridge/amd/cs5536/cs5536.h" /* Number of slots and devices in the PIR table */ -#define SLOT_COUNT 6 +#define IRQ_SLOT_COUNT 6 /* Platform IRQs */ #define PIRQA 11 @@ -73,7 +63,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */ + 32 + 16 * IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -83,13 +73,19 @@ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* Checksum */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ - {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */ - {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */ - {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */ - {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */ + /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* CPU */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + /* chipset */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, + /* slot1 */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, + /* slot2 */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, + /* slot3 */ + {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, + /* slot4 */ + {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, } }; Modified: coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.h =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.h 2008-03-06 23:33:59 UTC (rev 636) +++ coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.h 2008-03-07 01:20:36 UTC (rev 637) @@ -5,7 +5,7 @@ * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM */ -#include <arch/pirq_routing.h> +#include <pirq_routing.h> #define ID_SLOT_PCI_NET 1 // ThinCan ethernet #define ID_SLOT_PCI_RSVD1 2 // reserved entry 1 Modified: coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h 2008-03-06 23:33:59 UTC (rev 636) +++ coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h 2008-03-07 01:20:36 UTC (rev 637) @@ -17,20 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <lib.h> -#include <console.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#include <msr.h> -#include <io.h> #include <pirq_routing.h> -#include <amd_geodelx.h> -#include "../../../southbridge/amd/cs5536/cs5536.h" +/* Number of slots and devices in the PIR table */ +#error IRQ_SLOT_COUNT does not match PIR table contents, IRQ routing setup will access uninitialied memory +#define IRQ_SLOT_COUNT 5 - /* Platform IRQs */ #define PIRQA 10 #define PIRQB 11 @@ -52,7 +44,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * 5, /* Max. number of devices on the bus */ + 32 + 16 * IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -62,9 +54,13 @@ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ - {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ + /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* CPU */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + /* chipset */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, + /* ethernet */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, } }; Modified: coreboot-v3/mainboard/pcengines/alix1c/irq_tables.h =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/irq_tables.h 2008-03-06 23:33:59 UTC (rev 636) +++ coreboot-v3/mainboard/pcengines/alix1c/irq_tables.h 2008-03-07 01:20:36 UTC (rev 637) @@ -19,6 +19,8 @@ #include <pirq_routing.h> +/* Number of slots and devices in the PIR table */ +#define IRQ_SLOT_COUNT 5 /* Platform IRQs */ #define PIRQA 11 @@ -71,7 +73,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * 5, /* Max. number of devices on the bus */ + 32 + 16 * IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */

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coreboot March 2008