coreboot March 2008

coreboot@coreboot.org

75 participants
382 discussions

r3133 - trunk/util/flashrom
by svn＠coreboot.org 12 Mar '08

12 Mar '08

Author: uwe Date: 2008-03-12 12:54:51 +0100 (Wed, 12 Mar 2008) New Revision: 3133 Modified: trunk/util/flashrom/board_enable.c trunk/util/flashrom/chipset_enable.c trunk/util/flashrom/flash.h trunk/util/flashrom/flashrom.8 trunk/util/flashrom/flashrom.c Log: Add --list-supported option to flashrom which lists the supported ROM chips, chipsets, and mainboards (Closes #90). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: trunk/util/flashrom/board_enable.c =================================================================== --- trunk/util/flashrom/board_enable.c 2008-03-10 22:26:18 UTC (rev 3132) +++ trunk/util/flashrom/board_enable.c 2008-03-12 11:54:51 UTC (rev 3133) @@ -500,6 +500,18 @@ {0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */ }; +void print_supported_boards(void) +{ + int i; + + printf("\nSupported mainboards (this list is not exhaustive!):\n\n"); + + for (i = 0; board_pciid_enables[i].name != NULL; i++) + printf("%s\n", board_pciid_enables[i].name); + + printf("\nSee also: http://coreboot.org/Flashrom\n"); +} + /** * Match boards on coreboot table gathered vendor and part name. * Require main PCI IDs to match too as extra safety. Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2008-03-10 22:26:18 UTC (rev 3132) +++ trunk/util/flashrom/chipset_enable.c 2008-03-12 11:54:51 UTC (rev 3133) @@ -561,6 +561,17 @@ {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000}, }; +void print_supported_chipsets(void) +{ + int i; + + printf("\nSupported chipsets:\n\n"); + + for (i = 0; i < ARRAY_SIZE(enables); i++) + printf("%s (%04x:%04x)\n", enables[i].name, + enables[i].vendor, enables[i].device); +} + int chipset_flash_enable(void) { struct pci_dev *dev = 0; @@ -568,8 +579,7 @@ int i; /* Now let's try to find the chipset we have... */ - /* TODO: Use ARRAY_SIZE. */ - for (i = 0; i < sizeof(enables) / sizeof(enables[0]); i++) { + for (i = 0; i < ARRAY_SIZE(enables); i++) { dev = pci_dev_find(enables[i].vendor, enables[i].device); if (dev) break; Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-03-10 22:26:18 UTC (rev 3132) +++ trunk/util/flashrom/flash.h 2008-03-12 11:54:51 UTC (rev 3133) @@ -30,6 +30,8 @@ #include <stdint.h> #include <stdio.h> +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + struct flashchip { const char *name; /* With 32bit manufacture_id and model_id we can cover IDs up to @@ -287,11 +289,14 @@ struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, uint16_t card_vendor, uint16_t card_device); + /* board_enable.c */ int board_flash_enable(const char *vendor, const char *part); +void print_supported_boards(void); /* chipset_enable.c */ int chipset_flash_enable(void); +void print_supported_chipsets(void); /* Physical memory mapping device */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) Modified: trunk/util/flashrom/flashrom.8 =================================================================== --- trunk/util/flashrom/flashrom.8 2008-03-10 22:26:18 UTC (rev 3132) +++ trunk/util/flashrom/flashrom.8 2008-03-12 11:54:51 UTC (rev 3133) @@ -2,13 +2,13 @@ .SH NAME flashrom \- a universal BIOS/ROM/flash programming utility .SH SYNOPSIS -.B flashrom \fR[\fB\-rwvEVfhR\fR] [\fB\-c\fR chipname] [\fB\-s\fR exclude_start] [\fB\-e\fR exclude_end] +.B flashrom \fR[\fB\-rwvEVfLhR\fR] [\fB\-c\fR chipname] [\fB\-s\fR exclude_start] [\fB\-e\fR exclude_end] [\fB-m\fR vendor:part] [\fB-l\fR file.layout] [\fB-i\fR image_name] [file] .SH DESCRIPTION .B flashrom is a universal flash programming utility for DIP, PLCC, or SPI flash ROM chips. It can be used to flash BIOS/coreboot/firmware images, for example. - +.sp (see .B http://coreboot.org for details on coreboot) @@ -61,6 +61,17 @@ .B <name> from flash layout. .TP +.B "\-L, \-\-list\-supported" +List the ROM chips, chipsets, and mainboards supported by flashrom. +The list of mainboards consists of those boards which need a special +ROM write-enable function for flashrom to work. +.sp +There are many other boards which will work out of the box, without such +special support in flashrom. Some of the known-good/known-bad and tested ones +are listed at +.BR http://coreboot.org/Flashrom#Supported_mainboards , +but the list is not exhaustive, of course. +.TP .B "\-h, \-\-help" Show a help text and exit. .TP Modified: trunk/util/flashrom/flashrom.c =================================================================== --- trunk/util/flashrom/flashrom.c 2008-03-10 22:26:18 UTC (rev 3132) +++ trunk/util/flashrom/flashrom.c 2008-03-12 11:54:51 UTC (rev 3133) @@ -193,9 +193,19 @@ return 0; } +void print_supported_chips(void) +{ + int i; + + printf("Supported ROM chips:\n\n"); + + for (i = 0; flashchips[i].name != NULL; i++) + printf("%s\n", flashchips[i].name); +} + void usage(const char *name) { - printf("usage: %s [-rwvEVfhR] [-c chipname] [-s exclude_start]\n", name); + printf("usage: %s [-rwvEVfLhR] [-c chipname] [-s exclude_start]\n", name); printf(" [-e exclude_end] [-m [vendor:]part] [-l file.layout] [-i imagename] [file]\n"); printf (" -r | --read: read flash and save into file\n" @@ -210,8 +220,10 @@ " -f | --force: force write without checking image\n" " -l | --layout <file.layout>: read rom layout from file\n" " -i | --image <name>: only flash image name from flash layout\n" + " -L | --list-supported: print supported devices\n" + " -h | --help: print this help text\n" " -R | --version: print the version (release)\n" - "\n" " If no file is specified, then all that happens" + "\n" " If no file is specified, then all that happens" " is that flash info is dumped.\n\n"); exit(1); } @@ -245,6 +257,7 @@ {"force", 0, 0, 'f'}, {"layout", 1, 0, 'l'}, {"image", 1, 0, 'i'}, + {"list-supported", 0, 0, 'L'}, {"help", 0, 0, 'h'}, {"version", 0, 0, 'R'}, {0, 0, 0, 0} @@ -264,7 +277,7 @@ } setbuf(stdout, NULL); - while ((opt = getopt_long(argc, argv, "rRwvVEfc:s:e:m:l:i:h", + while ((opt = getopt_long(argc, argv, "rRwvVEfc:s:e:m:l:i:Lh", long_options, &option_index)) != EOF) { switch (opt) { case 'r': @@ -317,6 +330,12 @@ tempstr = strdup(optarg); find_romentry(tempstr); break; + case 'L': + print_supported_chips(); + print_supported_chipsets(); + print_supported_boards(); + exit(0); + break; case 'R': print_version(); exit(0);

1 0

genpowernow
by Rudolf Marek 12 Mar '08

12 Mar '08

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi all, I'm attaching my very experimental util, which can generate ACPI powernow objects. It needs for pre K8 rev F a table entry which can be easily added from datasheet. (So far there is Opteron 175 and some 4400 system. For k8 revF it should follow an algorithm in BKDG to generate the table. That code is totally UNTESTED - I dont have any access to revF system. For pre revF it works quite fine, it produces same result as proprietary BIOS except the bus latency value, which is recommended to 7 by AMD but my BIOS gives there 9. (output.txt) If you want to compare with original bios use acpidump to dump the SSDT table and iasl -d to get the text result. So if you want to give a try, you will need to add your system to atable and check the http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/304… For the table. Maybe AMD has some other form of the table ready to use by programs/parsers? The C structure quite follows the table entries so it is easy to add it there. If someone have time (I dont :/) it would be nice to see if the revF algo works or get fixed. It uses cpuid.c from x86info - it must be linked like gcc cpuid.c genpowernow.c - -o genpowernow Comments/suggestions/FIXES/IMPROVEMENTS welcome :) Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFH1xvc3J9wPJqZRNURAqLIAJoDYgfXKVkU3qXEh1YIlfXVk2OL8ACgvE0Y Ia7brZQnUNYnEAZQmIFi1fs= =4382 -----END PGP SIGNATURE----- Scope (\_PR.CPU0) { Name (_PCT, Package (0x02) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) } }) Name (_PSS, Package (0x04) { /* P#0 freq 2200 [MHz] voltage 1.350000 [V] TDP 110.000000 [W] */ Package (0x06) { 0x00000898, 0x0001adb0, 0x00000064, 0x00000007, 0xe0202a0e, 0x0000020e }, /* P#1 freq 2000 [MHz] voltage 1.300000 [V] TDP 105.600000 [W] */ Package (0x06) { 0x000007d0, 0x00019c80, 0x00000064, 0x00000007, 0xe0202a8c, 0x0000028c }, /* P#2 freq 1800 [MHz] voltage 1.250000 [V] TDP 89.100000 [W] */ Package (0x06) { 0x00000708, 0x00015c0c, 0x00000064, 0x00000007, 0xe0202b0a, 0x0000030a }, /* P#3 freq 1000 [MHz] voltage 1.100000 [V] TDP 49.000000 [W] */ Package (0x06) { 0x000003e8, 0x0000bf68, 0x00000064, 0x00000007, 0xe0202c82, 0x00000482 }, }) Method (_PPC, 0, NotSerialized) { Return (0x00) } } Scope (\_PR.CPU1) { Name (_PCT, Package (0x02) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) } }) Name (_PSS, Package (0x04) { /* P#0 freq 2200 [MHz] voltage 1.350000 [V] TDP 110.000000 [W] */ Package (0x06) { 0x00000898, 0x0001adb0, 0x00000064, 0x00000007, 0xe0202a0e, 0x0000020e }, /* P#1 freq 2000 [MHz] voltage 1.300000 [V] TDP 105.600000 [W] */ Package (0x06) { 0x000007d0, 0x00019c80, 0x00000064, 0x00000007, 0xe0202a8c, 0x0000028c }, /* P#2 freq 1800 [MHz] voltage 1.250000 [V] TDP 89.100000 [W] */ Package (0x06) { 0x00000708, 0x00015c0c, 0x00000064, 0x00000007, 0xe0202b0a, 0x0000030a }, /* P#3 freq 1000 [MHz] voltage 1.100000 [V] TDP 49.000000 [W] */ Package (0x06) { 0x000003e8, 0x0000bf68, 0x00000064, 0x00000007, 0xe0202c82, 0x00000482 }, }) Method (_PPC, 0, NotSerialized) { Return (0x00) } }

1 1

Re: [coreboot] Intel Core 2 Duo L7400 with MB chipset Intel 7100
by Remi Lefevre 12 Mar '08

12 Mar '08

---------- Forwarded message ---------- From: Remi Lefevre <rlefevre(a)gmail.com> Date: Wed, Mar 12, 2008 at 12:19 AM Subject: Re: [coreboot] Intel Core 2 Duo L7400 with MB chipset Intel 7100 To: ron minnich <rminnich(a)gmail.com> Hi Ron, On Tue, Mar 11, 2008 at 11:59 PM, ron minnich <rminnich(a)gmail.com> wrote: > It's a lot harder with Intel CPUs as they will not help you. > > AMD on the other hand will help you-- they support coreboot. > > Do you have to use Intel CPUs? Why do you talk only about Intel CPU ? Isn't the chipset (3100) more difficult to integrate than the CPU ? To answer your question, we have a very (I mean very) long life cycle on our product, and my hardware team seems to think (perhaps not wrongly) that they will be able to support Intel CPU longer than AMD ones... (they may change their mind with good arguments, but I doubt it, or they will propose ppc). And yes, I'm the software part ;) I have to understand that I would have to do a lot of reverse engeniering for Intel support (too bad they don't support this kind of Industry need). Warmly, rémi > > thanks > > ron >

2 1

Re: [coreboot] flashrom issues found??
by joe＠smittys.pointclark.net 11 Mar '08

11 Mar '08

Quoting joe(a)smittys.pointclark.net: >>>> So maybe there is an issue with erase_chip_jedec than?? >>> >>> Indeed. Have you tried to erase only, then read back the result >>> immediately? That would be very interesting. If the readback is all >>> 0xff, try commenting out erase_chip_jedec(flash) in write_jedec() and >>> leave the "dumb check if erase successful" in place, erase the memory >>> with flashrom -E, wait 30 seconds, write to the memory with the flashrom >>> version which does not call erase_chip_jedec(flash) in write_jedec(). I >>> would be very interested in the result. >>> > Well, I did just want you said above and the readback is not 0xff it > looks like a coreboot image. Then I commented out > erase_chip_jedec(flash) in write_jedec() > and did this: > > [root@localhost flashrom]# flashrom -E > Calibrating delay loop... OK. > Found coreboot table at 0x00000530. > Vendor ID: RCA, part ID: RM4100 > Found chipset "ICH4/ICH4-L", enabling flash write... OK. > NOT FOUND RCA:RM4100 > M50FW080 found at physical address 0xfff00000. > Flash part is M50FW080 (1024 KB). > Erasing flash chip > [root@localhost flashrom]# flashrom -wv test.rom > Calibrating delay loop... OK. > Found coreboot table at 0x00000530. > Vendor ID: RCA, part ID: RM4100 > Found chipset "ICH4/ICH4-L", enabling flash write... OK. > NOT FOUND RCA:RM4100 > M50FW080 found at physical address 0xfff00000. > Flash part is M50FW080 (1024 KB). > ERASE FAILED @0, val 55! > Verifying flash... VERIFIED. > [root@localhost flashrom]# > > > There is definatly something funky going on with > erase_chip_jedec(flash) here. I don't think it is a GPIO or anything, I > have them setup just like the original bios and uniflash is able to > write to it just fine with the original bios.........please help:-( > > > > > Thanks - Joe Thanks - Joe

1 0

qemu error message: "Unrecognized partitioning scheme"
by David Edrich 11 Mar '08

11 Mar '08

Can anyone tell me why when following the coreboot wiki procedure for using qemu I would get the error message: "Unrecognized partitioning scheme" The last few lines are below: So.FILO does seem to be able to read something from this disk image, from the output. If relevant, the OS I was using was knoppix. Also I'd like to know if there an easy way to exit qemu. I keep having to run kill -9 <task number> -------------------------- Jumping to boot code at 0x10e77c FILO version 0.5 (dsedrich@nwell) Mon Feb 25 20:06:44 EST 2008 menu: hda3:/boot/filo/menu.lst IDE time out reset failed, but slave maybe exist hda: LBA48 2147MB: QEMU HARDDISK Unrecognized partitioning scheme -------------------------------------------------- Here is everything that was outputted: ------------------------------------------- Welcome to elfboot, the open sourced starter. [dsedrich@nwell:~] $ qemu -L ~ -hda /home/tmp/disk.img -nographic Could not configure '/dev/rtc' to have a 1024 Hz timer. This is not a fatal error, but for better emulation accuracy either use a 2.6 host Linux kernel or type 'echo 1024 > /proc/sys/dev/rtc/max-user-freq' as root. coreboot-2.0.0-GRUB2 Tue Feb 26 13:31:40 EST 2008 starting... Copying coreboot to RAM. (qemu) Jumping to coreboot. coreboot-2.0.0-GRUB2 Tue Feb 26 13:31:40 EST 2008 booting... Enumerating buses... Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1237] enabled PCI: 00:01.0 [8086/7000] enabled PCI: 00:01.1 [8086/7010] enabled PCI: 00:01.3 [8086/7113] enabled PCI: 00:02.0 [1013/00b8] enabled PCI: 00:03.0 [10ec/8029] enabled PCI: pci_scan_bus returning with max=000 done Allocating resources... Reading resources... Done reading resources. Setting resources... I would set ram size to 0x20000 Kbytes PCI: 00:01.1 20 <- [0x0000001400 - 0x000000140f] size 0x00000010 gran 0x04 io PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 prefmem PCI: 00:02.0 14 <- [0x00fe000000 - 0x00fe000fff] size 0x00001000 gran 0x0c mem PCI: 00:03.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io Done setting resources. Done allocating resources. Enabling resources... PCI: 00:00.0 subsystem <- 00/00 PCI: 00:00.0 cmd <- 00 PCI: 00:01.0 subsystem <- 00/00 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 cmd <- 01 PCI: 00:01.3 cmd <- 00 PCI: 00:02.0 cmd <- 03 PCI: 00:03.0 cmd <- 01 done. Initializing devices... Root Device init PCI: 00:00.0 init PCI: 00:01.0 init PCI: 00:01.1 init PCI: 00:01.3 init PCI: 00:02.0 init INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1013, did=b8 rom base, size: c0000 BAD SIGNATURE 0x0 0x0 biosint: INT# 0x10 biosint: eax 0x2 ebx 0x0 ecx 0x80000001 edx 0x0 biosint: ebp 0x11fac esp 0xffa edi 0x0 esi 0x12538 biosint: ip 0x806e cs 0x0 flags 0x46 BIOSINT: Unsupport int #0x10 PCI: 00:03.0 init Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. Moving GDT to 0x500...ok Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f0400 to 0x00100000 Wrote coreboot table at: 00000530 - 00000bc4 checksum eb9d Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 rom_stream: 0xfffc0000 - 0xfffeffff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 New segment addr 0x100000 size 0x3cfe0 offset 0xc0 filesize 0x12fc8 (cleaned up) New segment addr 0x100000 size 0x3cfe0 offset 0xc0 filesize 0x12fc8 New segment addr 0x13cfe0 size 0x48 offset 0x130a0 filesize 0x48 (cleaned up) New segment addr 0x13cfe0 size 0x48 offset 0x130a0 filesize 0x48 Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x000000000003cfe0 filesz: 0x0000000000012fc8 Clearing Segment: addr: 0x0000000000112fc8 memsz: 0x000000000002a018 Loading Segment: addr: 0x000000000013cfe0 memsz: 0x0000000000000048 filesz: 0x0000000000000048 Jumping to boot code at 0x10e77c FILO version 0.5 (dsedrich@nwell) Mon Feb 25 20:06:44 EST 2008 menu: hda3:/boot/filo/menu.lst IDE time out reset failed, but slave maybe exist hda: LBA48 2147MB: QEMU HARDDISK Unrecognized partitioning scheme

3 11

denver summit, preliminary schedule
by ron minnich 11 Mar '08

11 Mar '08

OK,first news, AMD is now a "Silver" sponsor of the Denver summit. I can not thank AMD enough. I don't know if all of us put together can thank AMD enough. But, we should try! Thanks, AMD! Here is a very tentative schedule. I think it's going to be pretty exciting, I intend to bring as much hardware as I can for us to work on. I still need to line up breaks, lunch, dinner, etc. with the main workshop; this is still a bit tentative. 1-2 Ron opens the meeting and discusses how things went in '07 and late '06 from the last meeting. I think the Big News is the meteoric rise of v3, how nice it is, and the growth in our platforms. Also talk about other things I learned from talks with vendors. You'll be amazed by something I learned at SC 07 ... 2-230 break 230-400 Stepan talks about - the automated testbed, what it is, how to set it up. The automated testbed is a quite amazing resource we should all understand. - the GSOC projects - his work with the german army - his recent ports 4-430 break 430-rest of day hack session -- Please, bring your hardware! Friday 0830-1000 AMD talks about: - consumer issues - what's going on - new ports this year - "Fam 10". - Jordan's fantastic new library and his use of Uwe's micro-curses 1000-1030 break 1030-1200 Marc talks about his work at Sun with the simulator 1200-0130 lunch 0130- 0300 an overview of v3, from the smallest to the large bits. Sample v3 build/burn session 0300-0330 break 0330- 0400 open questions (please add some) 1. how do we tell when a board is good enough to move from v2 to v3? What's the test? 2. How do we make life easy for vendors? 3. What pending issues are there. 0400-0500 The view from the FSF -- what's going on, etc. Note: I hope to have one or two more hardware speakers. I welcome volunteers from this list. We're a friendly group and always interested in hearing more. saturday -- hack, hack, hack. Please bring hardware for this session. We hope to really do more improvement on v3! sunday -- more hacking at starbucks :-) (but Ron has to leave, sadly, about 3 or 4 pm) Hope to see you there. This is going to be a good one. Thanks ron

2 2

r3132 build service
by coreboot information 11 Mar '08

11 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "hailfinger" checked in revision 3132 to the coreboot source repository and caused the following changes: Change Log: Add GPIO dumping utility for Intel ICH series southbridges. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Signed-off-by: Joseph Smith <joe(a)smittys.pointclark.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3132&device=serengeti_chee… Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3132&device=rm4100&vendor=… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

vm86 for gigabyte m57sli
by Ronald Hoogenboom 10 Mar '08

10 Mar '08

Hi, In my quest to get some life in my nvidia 8600GT board, I've been trying to get the VGA rom executed by vm86 instead of x86emu. There are a few other mainboards that do this too. The source file implementing this turns out to be called 'vgabios.c', of which some variants exist. I also figured out that the _RAMBASE must be set to 0x4000 for this to be linkable (otherwise truncated 16 bit relocations). The one for via epia-m needs some support in the northbridge (vt8623) to call the do_vgabios. The vgabios file is in the mainboard/via/epia-m directory. The one for artecgroup dbe61 seems to be the most stand-alone/versatile, but it needs some modification of the device tree in Config.lb. The vgabios.c is in mainboard/artecgroup/dbe61/realmode and it looks like the intention is that this directory should be copied under drivers/pci and some section chip drivers/pci/realmode device pci 1.1 on end # VGA register "rom_address" = "0xf4100000" # at the beginning of 256k end should be added to the Config.lb of the mainboard. But I cannot figure out where it should be exactly. Putting it just after the 'end # PCI domain' will just make the boot stops in 'Reading resources' without any clue. Putting it just before the 'end # PCI domain' produces 'PCI: Left over static devices....' in 'Enumerating busses'. Also setting the rom address in there like this looks awkward to me, as it will most probably be different for a different VGA card. What is the way to go forward? Would I be better off using the epia-m vm86 and change the northbridge for the m57sli (amdk8)? Ronald.

1 0

[PATCH]ich_gpio_dump util
by joe＠smittys.pointclark.net 10 Mar '08

10 Mar '08

Here you go, this work great, thanks again Stefan. Signed-off-by: Joseph Smith <joe(a)smittys.pointclark.net> Thanks - Joe

6 23

r3132 - in trunk/util: . inteltools
by svn＠coreboot.org 10 Mar '08

10 Mar '08

Author: hailfinger Date: 2008-03-10 23:26:18 +0100 (Mon, 10 Mar 2008) New Revision: 3132 Added: trunk/util/inteltools/ trunk/util/inteltools/Makefile trunk/util/inteltools/ich_gpio.8 trunk/util/inteltools/ich_gpio.c Log: Add GPIO dumping utility for Intel ICH series southbridges. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Signed-off-by: Joseph Smith <joe(a)smittys.pointclark.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: trunk/util/inteltools/Makefile =================================================================== --- trunk/util/inteltools/Makefile (rev 0) +++ trunk/util/inteltools/Makefile 2008-03-10 22:26:18 UTC (rev 3132) @@ -0,0 +1,62 @@ +# +# Makefile for ich_gpio utility +# +# (C) 2008 by coresystems GmbH +# written by Stefan Reinauer <stepan(a)coresystems.de> +# Copyright (C) 2008 Joseph Smith <joe(a)smittys.pointclark.net> +# + +PROGRAM = ich_gpio + +CC = gcc +STRIP = strip +INSTALL = /usr/bin/install +PREFIX = /usr/local +CFLAGS = -O2 -g -Wall +OS_ARCH = $(shell uname) +ifeq ($(OS_ARCH), SunOS) +LDFLAGS = -lpci -lz +else +LDFLAGS = -lpci -lz -static +STRIP_ARGS = -s +endif + +OBJS = ich_gpio.o + +all: pciutils dep $(PROGRAM) + +$(PROGRAM): $(OBJS) + $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS) + $(STRIP) $(STRIP_ARGS) $(PROGRAM) + +clean: + rm -f *.o *~ + +distclean: clean + rm -f $(PROGRAM) .dependencies + +dep: + @$(CC) -MM *.c > .dependencies + +pciutils: + @echo; echo -n "Checking for pciutils and zlib... " + @$(shell ( echo "#include <pci/pci.h>"; \ + echo "struct pci_access *pacc;"; \ + echo "int main(int argc, char **argv)"; \ + echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c ) + @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \ + echo "found." || ( echo "not found."; echo; \ + echo "Please install pciutils-devel and zlib-devel."; \ + echo "See README for more information."; echo; \ + rm -f .test.c .test; exit 1) + @rm -f .test.c .test + +install: $(PROGRAM) + $(INSTALL) $(PROGRAM) $(PREFIX)/sbin + mkdir -p $(PREFIX)/share/man/man8 + $(INSTALL) $(PROGRAM).8 $(PREFIX)/share/man/man8 + +.PHONY: all clean distclean dep pciutils + +-include .dependencies + Added: trunk/util/inteltools/ich_gpio.8 =================================================================== --- trunk/util/inteltools/ich_gpio.8 (rev 0) +++ trunk/util/inteltools/ich_gpio.8 2008-03-10 22:26:18 UTC (rev 3132) @@ -0,0 +1,59 @@ +.TH ICH_GPIO 8 "March 8, 2008" +.SH NAME +ich_gpio \- Intel southbridge GPIO Dump Utility +.SH SYNOPSIS +.B ich_gpio +.SH DESCRIPTION +.B ich_gpio +is a user-space utility which can dump all +register contents of the Intel ICH series Southbridges. +.PP +It is mainly used for coreboot development purposes (see coreboot.org +for details on coreboot), but it may also be useful for other things. +.PP +Here is an example output: +.br +[root@localhost dumpgpio]# ich_gpio +.br +Intel Southbridge: 8086:24c0 +.br +GPIOBASE = 0x0500 +.br +gpiobase+0x0000: 0x1a003180 +.br +gpiobase+0x0004: 0x0900ffff +.br +gpiobase+0x0008: 0x00000000 +.br +gpiobase+0x000c: 0x1bbf0000 +.br +gpiobase+0x0010: 0x00000000 +.br +gpiobase+0x0014: 0x00000000 +.br +gpiobase+0x0018: 0x00040000 +.br +gpiobase+0x001c: 0x00000000 +.br +gpiobase+0x0020: 0x00000000 +.br +gpiobase+0x0024: 0x00000000 +.br +gpiobase+0x0028: 0x00000000 +.br +gpiobase+0x002c: 0x00003000 +.br +gpiobase+0x0030: 0x00000fff +.br +gpiobase+0x0034: 0x00000e00 +.br +gpiobase+0x0038: 0x00000fff +.br +gpiobase+0x003c: 0x00000000 +.PP +Please consult your datasheet for the register meanings. +.SH OPTIONS +No command line options needed just run ich_gpio. +.SH AUTHORS +Please see the individual source code files. + Added: trunk/util/inteltools/ich_gpio.c =================================================================== --- trunk/util/inteltools/ich_gpio.c (rev 0) +++ trunk/util/inteltools/ich_gpio.c 2008-03-10 22:26:18 UTC (rev 3132) @@ -0,0 +1,91 @@ +/* + * dump gpio on intel ICH series southbridges + * + * Copyright (C) 2008 by coresystems GmbH + * written by Stefan Reinauer <stepan(a)coresystems.de> + * Copyright (C) 2008 Joseph Smith <joe(a)smittys.pointclark.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <errno.h> +#include <fcntl.h> +#include <sys/mman.h> +#include <unistd.h> +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <stdint.h> +#include <getopt.h> + +#include <sys/io.h> +#include <pci/pci.h> + +int map_gpio(uint16_t gpio) +{ + int i; + unsigned long size=0x40; + + for (i=0; i<size; i+=4) { + printf("gpiobase+0x%04x: 0x%08x\n", i, inl(gpio+i)); + } + + return 0; +} + +int main(int argc, char *argv[]) +{ + struct pci_access *pacc; + struct pci_dev *sb; + uint16_t gpiobadd; + uint16_t device; + + if (iopl(3)) { + perror("You need to be root.\n"); + exit(1); + } + + pacc = pci_alloc(); + pci_init(pacc); + pci_scan_bus(pacc); + + sb = pci_get_dev(pacc, 0, 0, 0x1f, 0); + if (!sb) { + printf("No southbridge found.\n"); + exit(1); + } + + if (pci_read_word(sb, 0) != 0x8086) { + printf("Not an Intel southbridge.\n"); + exit(1); + } + + printf("Intel Southbridge: %04x:%04x\n", + pci_read_word(sb, 0), pci_read_word(sb, 2)); + + device = pci_read_word(sb, 2); + + if (device < 0x2640) { + gpiobadd = pci_read_word(sb, 0x58) & 0xfffc; + } else if (device >= 0x2640) { + gpiobadd = pci_read_word(sb, 0x48) & 0xfffc; + } + printf("GPIOBASE = 0x%04x\n\n", gpiobadd); + + map_gpio(gpiobadd); + + + return 0; +}

1 0

← Newer
1
...
26
27
28
29
30
31
32
...
39
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot March 2008