coreboot March 2008

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382 discussions

r633 - coreboot-v3/lib
by svn＠coreboot.org 06 Mar '08

06 Mar '08

Author: rminnich Date: 2008-03-06 17:35:44 +0100 (Thu, 06 Mar 2008) New Revision: 633 Added: coreboot-v3/lib/ramtest.c Log: Add ramtest for development. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: coreboot-v3/lib/ramtest.c =================================================================== --- coreboot-v3/lib/ramtest.c (rev 0) +++ coreboot-v3/lib/ramtest.c 2008-03-06 16:35:44 UTC (rev 633) @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2001 Tyson Sawyer, irobot + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> + + +static void write_phys(unsigned long addr, unsigned long value) +{ + volatile unsigned long *ptr; + ptr = (void *)addr; + *ptr = value; +} + +static unsigned long read_phys(unsigned long addr) +{ + volatile unsigned long *ptr; + ptr = (void *)addr; + return *ptr; +} + +static void ram_fill(unsigned long start, unsigned long stop) +{ + unsigned long addr; + /* + * Fill. + */ + printk(BIOS_DEBUG, "DRAM fill: %lx-%lx\n", start, stop); + for(addr = start; addr < stop ; addr += 4) { + /* Display address being filled */ + if (!(addr & 0xffff)) { + printk(BIOS_DEBUG, "%lx\r", addr); + } + write_phys(addr, addr); + }; + /* Display final address */ + printk(BIOS_DEBUG, "%lx\nDRAM filled\n", addr); +} + +static void ram_verify(unsigned long start, unsigned long stop) +{ + unsigned long addr; + int i = 0; + /* + * Verify. + */ + printk(BIOS_DEBUG, "DRAM verify: %lx-%lx\n", start, stop); + for(addr = start; addr < stop ; addr += 4) { + unsigned long value; + /* Display address being tested */ + if (!(addr & 0xffff)) { + printk(BIOS_DEBUG, "%lx\r", addr); + } + value = read_phys(addr); + if (value != addr) { + /* Display address with error */ + printk(BIOS_ERR, "Fail @%lx Read value=%lx\n", + addr, value); + i++; + if(i>256) { + printk(BIOS_ERR, "Aborting.\n"); + break; + } + } + } + /* Display final address */ + printk(BIOS_DEBUG, "%lx\r", addr); + if (i) { + printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n"); + } + else { + printk(BIOS_DEBUG, "\nDRAM range verified.\n"); + } +} + + +void ram_check(unsigned long start, unsigned long stop) +{ + /* + * This is much more of a "Is my DRAM properly configured?" + * test than a "Is my DRAM faulty?" test. Not all bits + * are tested. -Tyson + */ + printk(BIOS_DEBUG, "Testing DRAM: %lx-%lx\n", start, stop); + ram_fill(start, stop); + ram_verify(start, stop); + printk(BIOS_DEBUG, "Done.\n"); +} +

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r3127 build service
by coreboot information 06 Mar '08

06 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3127 to the coreboot source repository and caused the following changes: Change Log: Drop some duplicate documentation from the README. The manpage and 'superiotool --help' already provide the same information (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3127&device=serengeti_chee… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3126 build service
by coreboot information 06 Mar '08

06 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3126 to the coreboot source repository and caused the following changes: Change Log: Add missing license header to layout.c. The file was written by Stefan Reinauer for coresystems GmbH in 2005, as confirmed on IRC. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3126&device=serengeti_chee… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

programming 101
by ron minnich 06 Mar '08

06 Mar '08

how the hell did we miss this: if (device == DIMM0) { for (i = 0; i < ARRAY_SIZE(spd_table); i++) { if (spd_table[i].address == address) { ret = spd_table[i].data; } } } if (i == ARRAY_SIZE(spd_table)) printk(BIOS_DEBUG, " addr %02x does not exist in SPD table", address); So, maybe we need a break in there? As it is, it always prints that things are not found :-) thanks ron

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add on
by Wang, Qingpei 06 Mar '08

06 Mar '08

Jason Wang Intern Beijing Technology Development Center Advanced Micro Devices(AMD) E-mail:Qingpei.Wang@amd.com <mailto:Qingpei.Wang@amd.com> <mailto:i@hotmail.com>

1 0

first output: dbe62 and v3
by ron minnich 06 Mar '08

06 Mar '08

attached. It dies and I'm sure it is bad ram settings, but it's a start. One thing I plan to change pretty soon: power button control can move from stage1 to stage2, and power button control will be managed in dts (another dts setting we would NOT want visible in Kconfig; you could render a board totally unbootable and unrepairable with the wrong setting. Kconfig should be for settings that are safe to change). There are other things in stage1 for the lx that we should try to move to stage 2: cs5536_setup_extmsr(); cs5536_setup_cis_mode(); msr = rdmsr(GLCP_SYS_RSTPLL); if (msr.lo & (0x3f << 26)) { /* PLL is already set and we are reboot from PLL reset. */ return; } cs5536_setup_idsel(); cs5536_usb_swapsif(); cs5536_setup_iobase(); cs5536_setup_smbus_gpio(); /* cs5536_enable_smbus(); -- Leave this out for now. */ // cs5536_setup_power_button(); how much of this do we want managed in stage1? How much is unchanging, board to board? How much MUST be there? Really, a lot is going on; what can we leave to stage 2. Power button for sure; what else? And how do we parameterize this? Just pass in a set of booleans for those things we wish to control (e.g. smbus). At this rate, carl-daniel, we may soon have another board for your list. thanks ron p.s. thanks to artecgroup for such great product design and support.

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Re: [coreboot] VGA and Asus a8v-e_se
by Rudolf Marek 06 Mar '08

06 Mar '08

Hi, To fix the powernow add following after following line into dsdt.asl Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {} Scope (\_PR.CPU0) { Name (_PCT, Package (0x02) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) } }) Name (_PSS, Package (0x04) { Package (0x06) { 0x00000898, 0x00014D34, 0x00000064, 0x00000009, 0xE020298E, 0x0000018E }, Package (0x06) { 0x000007D0, 0x00014438, 0x00000064, 0x00000009, 0xE0202A0C, 0x0000020C }, Package (0x06) { 0x00000708, 0x00011300, 0x00000064, 0x00000009, 0xE0202A8A, 0x0000028A }, Package (0x06) { 0x000003E8, 0x00008D04, 0x00000064, 0x00000009, 0xE0202C82, 0x00000482 } }) Name (_PPC, 0x00) } Then just recompile Coreboot. I'm using the powernowd and it does work. If possible could you send me the lspci -xxx when the coreboot is running too? You may also try /LinuxBIOSv2/src/southbridge/via/k8t890/k8t890_pcie.c to edit the init function: static void peg_init(struct device *dev) I think you can put return at the beginning of the function. There is a chance that it will work without anything else. I think problem is in card reset. I have in plan to cleanup the PCIe init a bit but frankly I dont know if the reset is needed and even not sure about the link retrain. Thanks, Rudolf

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Audio mute problem
by joe＠smittys.pointclark.net 06 Mar '08

06 Mar '08

Hello, The audio on the RM4100 is muted by default. I know the assembly code to unmute it but I am not so good with the assembly, could someone translate this for me into human??? seg000:00000000 mov edx, 84Dh seg000:00000005 mov eax, 0C0h ; '+' seg000:0000000A out dx, al Thanks - Joe

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patch: set dbe62 to have com2 on com1 address
by ron minnich 06 Mar '08

06 Mar '08

I still have no LPC dongle, but I am getting closer. I really liked this as it shows off the power of our new config system, the dts. There is a whole function in v2 to make com2 operate at the com1 address. For v3, we just set a value in the mainboard dts and we're done (in theory ; I can't tell if this works). DBE62 is getting through a lot of POST btw but hangs at 13. I just realized this exampel also shows that you do NOT want all dts values to be visible in Kconfig. It would make no sense to change these values on the dbe62. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Index: mainboard/artecgroup/dbe62/dts =================================================================== --- mainboard/artecgroup/dbe62/dts (revision 630) +++ mainboard/artecgroup/dbe62/dts (working copy) @@ -43,6 +43,10 @@ /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. * See virtual PIC spec. */ enable_gpio_int_route = "0x0D0C0700"; + /* we use com2 since that is on the dongle */ + com2_enable = "1"; + /* Set com2 address to be COM1 */ + com2_address = "0x3f8"; }; }; };

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v3 makefile bugs
by Carl-Daniel Hailfinger 05 Mar '08

05 Mar '08

Hi, I just tried make randconfig to test whether all allowed configuations can be built. The result was disastrous. Without a make distclean before make randconfig, I get all sorts of compile errors for about 60% of the randomly generated .config files. With make distclean before make randconfig, most of the configurations built successfully. This means that some dependencies are wrong, resulting in incorrect builds. To reproduce, simply run "make randconfig; make;" in a loop. It will fail after two or three iterations. Regards, Carl-Daniel -- http://www.hailfinger.org/

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coreboot March 2008