r638 - in coreboot-v3: mainboard/amd/norwich mainboard/artecgroup/dbe61 mainboard/artecgroup/dbe62 southbridge/amd/cs5536
Author: rminnich Date: 2008-03-07 07:33:05 +0100 (Fri, 07 Mar 2008) New Revision: 638
Modified: coreboot-v3/mainboard/amd/norwich/stage1.c coreboot-v3/mainboard/artecgroup/dbe61/initram.c coreboot-v3/mainboard/artecgroup/dbe61/stage1.c coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h coreboot-v3/mainboard/artecgroup/dbe62/stage1.c coreboot-v3/southbridge/amd/cs5536/cs5536.h coreboot-v3/southbridge/amd/cs5536/stage1.c Log: Make cs5536_setup_onchipuart() handle both UARTs and add missing break in dbe61 initram.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Tested on dbe62. I had to run cs5536/stage1.c through indent -kr -i8 because emacs is somehow confused by parts of it. Weird. indent made some parts ugly, at least to my eyes. Oh well. Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: coreboot-v3/mainboard/amd/norwich/stage1.c =================================================================== --- coreboot-v3/mainboard/amd/norwich/stage1.c 2008-03-07 01:20:36 UTC (rev 637) +++ coreboot-v3/mainboard/amd/norwich/stage1.c 2008-03-07 06:33:05 UTC (rev 638) @@ -42,7 +42,7 @@ * early MSR setup for the CS5536. We do this early for debug. * Real setup should be done in chipset init via dts settings. */ - cs5536_setup_onchipuart(); + cs5536_setup_onchipuart(1); }
void mainboard_pre_payload(void)
Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-03-07 01:20:36 UTC (rev 637) +++ coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-03-07 06:33:05 UTC (rev 638) @@ -102,6 +102,7 @@ for (i = 0; i < ARRAY_SIZE(spd_table); i++) { if (spd_table[i].address == address) { ret = spd_table[i].data; + break; } }
Modified: coreboot-v3/mainboard/artecgroup/dbe61/stage1.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/stage1.c 2008-03-07 01:20:36 UTC (rev 637) +++ coreboot-v3/mainboard/artecgroup/dbe61/stage1.c 2008-03-07 06:33:05 UTC (rev 638) @@ -59,7 +59,7 @@ * NOTE: Must do this AFTER the early_setup! It is counting on some * early MSR setup for the CS5536. */ - cs5536_setup_onchipuart(); + cs5536_setup_onchipuart(2); }
void mainboard_pre_payload(void)
Modified: coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h 2008-03-07 01:20:36 UTC (rev 637) +++ coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h 2008-03-07 06:33:05 UTC (rev 638) @@ -20,8 +20,7 @@ #include <pirq_routing.h>
/* Number of slots and devices in the PIR table */ -#error IRQ_SLOT_COUNT does not match PIR table contents, IRQ routing setup will access uninitialied memory -#define IRQ_SLOT_COUNT 5 +#define IRQ_SLOT_COUNT 3
/* Platform IRQs */ #define PIRQA 10
Modified: coreboot-v3/mainboard/artecgroup/dbe62/stage1.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/stage1.c 2008-03-07 01:20:36 UTC (rev 637) +++ coreboot-v3/mainboard/artecgroup/dbe62/stage1.c 2008-03-07 06:33:05 UTC (rev 638) @@ -58,7 +58,7 @@ * NOTE: Must do this AFTER the early_setup! It is counting on some * early MSR setup for the CS5536. */ - cs5536_setup_onchipuart2(); + cs5536_setup_onchipuart(2); }
void mainboard_pre_payload(void)
Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.h =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.h 2008-03-07 01:20:36 UTC (rev 637) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.h 2008-03-07 06:33:05 UTC (rev 638) @@ -443,8 +443,7 @@
/* Function prototypes */ void cs5536_disable_internal_uart(void); -void cs5536_setup_onchipuart(void); -void cs5536_setup_onchipuart2(void); +void cs5536_setup_onchipuart(int uart); void cs5536_stage1(void);
#endif /* SOUTHBRIDGE_AMD_CS5536_CS5536_H */
Modified: coreboot-v3/southbridge/amd/cs5536/stage1.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/stage1.c 2008-03-07 01:20:36 UTC (rev 637) +++ coreboot-v3/southbridge/amd/cs5536/stage1.c 2008-03-07 06:33:05 UTC (rev 638) @@ -49,10 +49,10 @@ /* TODO: unsigned char -> u8? */ #if CS5536_GLINK_PORT_NUM <= 4 msr.lo = CS5536_DEV_NUM << - (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8); + (unsigned char) ((CS5536_GLINK_PORT_NUM - 1) * 8); #else msr.hi = CS5536_DEV_NUM << - (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8); + (unsigned char) ((CS5536_GLINK_PORT_NUM - 5) * 8); #endif
wrmsr(GLPCI_ExtMSR, msr); @@ -90,11 +90,11 @@ }
static const struct msrinit msr_table[] = { - {MDD_LBAR_SMB, {.hi = 0x0000f001, .lo = SMBUS_IO_BASE}}, - {MDD_LBAR_GPIO, {.hi = 0x0000f001, .lo = GPIO_IO_BASE}}, - {MDD_LBAR_MFGPT, {.hi = 0x0000f001, .lo = MFGPT_IO_BASE}}, - {MDD_LBAR_ACPI, {.hi = 0x0000f001, .lo = ACPI_IO_BASE}}, - {MDD_LBAR_PMS, {.hi = 0x0000f001, .lo = PMS_IO_BASE}}, + {MDD_LBAR_SMB, {.hi = 0x0000f001,.lo = SMBUS_IO_BASE}}, + {MDD_LBAR_GPIO, {.hi = 0x0000f001,.lo = GPIO_IO_BASE}}, + {MDD_LBAR_MFGPT, {.hi = 0x0000f001,.lo = MFGPT_IO_BASE}}, + {MDD_LBAR_ACPI, {.hi = 0x0000f001,.lo = ACPI_IO_BASE}}, + {MDD_LBAR_PMS, {.hi = 0x0000f001,.lo = PMS_IO_BASE}}, };
/** @@ -147,15 +147,15 @@ * Disable and reset them and configure them later (SIO init). */ msr = rdmsr(MDD_UART1_CONF); - msr.lo = 1; /* Reset */ + msr.lo = 1; /* Reset */ wrmsr(MDD_UART1_CONF, msr); - msr.lo = 0; /* Disable */ + msr.lo = 0; /* Disable */ wrmsr(MDD_UART1_CONF, msr);
msr = rdmsr(MDD_UART2_CONF); - msr.lo = 1; /* Reset */ + msr.lo = 1; /* Reset */ wrmsr(MDD_UART2_CONF, msr); - msr.lo = 0; /* Disable */ + msr.lo = 0; /* Disable */ wrmsr(MDD_UART2_CONF, msr); }
@@ -182,7 +182,7 @@ * * See page 412 of the AMD Geode CS5536 Companion Device data book. */ -void cs5536_setup_onchipuart(void) +void cs5536_setup_onchipuart1(void) { struct msr msr;
@@ -238,7 +238,8 @@ outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
/* Set: GPIO 3 + 3 Pull Up (0x18) */ - outl(GPIOL_3_SET | GPIOL_4_SET, GPIO_IO_BASE + GPIOL_PULLUP_ENABLE); + outl(GPIOL_3_SET | GPIOL_4_SET, + GPIO_IO_BASE + GPIOL_PULLUP_ENABLE);
/* set address to 3F8 */ msr = rdmsr(MDD_LEG_IO); @@ -255,7 +256,19 @@ wrmsr(MDD_UART2_CONF, msr); }
+void cs5536_setup_onchipuart(int uart) +{ + switch (uart) { + case 1: + cs5536_setup_onchipuart1(); + break; + case 2: + cs5536_setup_onchipuart2(); + break; + } +}
+ /** * Board setup. *
-
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