r636 - in coreboot-v3: include mainboard/artecgroup/dbe61 mainboard/artecgroup/dbe62 mainboard/pcengines/alix1c northbridge/amd/geodelx southbridge/amd/cs5536

Author: rminnich
Date: 2008-03-07 00:33:59 +0100 (Fri, 07 Mar 2008)
New Revision: 636

Modified:
   coreboot-v3/include/lib.h
   coreboot-v3/mainboard/artecgroup/dbe61/initram.c
   coreboot-v3/mainboard/artecgroup/dbe62/Makefile
   coreboot-v3/mainboard/artecgroup/dbe62/dts
   coreboot-v3/mainboard/artecgroup/dbe62/initram.c
   coreboot-v3/mainboard/artecgroup/dbe62/stage1.c
   coreboot-v3/mainboard/pcengines/alix1c/initram.c
   coreboot-v3/northbridge/amd/geodelx/raminit.c
   coreboot-v3/southbridge/amd/cs5536/cs5536.c
   coreboot-v3/southbridge/amd/cs5536/cs5536.h
   coreboot-v3/southbridge/amd/cs5536/dts
   coreboot-v3/southbridge/amd/cs5536/stage1.c
Log:
 This is a cumulative set of fixes for LX800 boards. These are all tested on ALIX 1C and DBE62.
 This includes:
 - the working power button patch.
 - onchipuart2 for very early startup -- this will be replaced with a better mechanism soon.
 - dts mod for powerbutton on cs5536
 - dbe62 dts fix for COM1 setup
 - ram check call in dbe62 initram.c
 - Carl-Daniel's fix to detect incorrect access to spd variables.
 - more debug prints in geodelx northbridge support code.

This is cumulative since we're lagging on acks a bit and it's hard to keep this
 stuff all seperated out since it involves a common set of files. I'd like to get
 it acked and in tree today if possible. It's a very small set of lines changed so please
 forgive me for the cumulative nature.

Thanks

Signed-off-by: Ronald G. Minnich

Acked-by: Carl-Daniel Hailfinger

Modified: coreboot-v3/include/lib.h
===================================================================
--- coreboot-v3/include/lib.h	2008-03-06 23:18:13 UTC (rev 635)
+++ coreboot-v3/include/lib.h	2008-03-06 23:33:59 UTC (rev 636)
@@ -36,4 +36,7 @@
 void beep_short(void);
 void beep_long(void);

+/* Optional ramtest. */
+void ram_check(unsigned long start, unsigned long stop);
+
 #endif /* LIB_H */

Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe61/initram.c	2008-03-06 23:18:13 UTC (rev 635)
+++ coreboot-v3/mainboard/artecgroup/dbe61/initram.c	2008-03-06 23:33:59 UTC (rev 636)
@@ -97,13 +97,17 @@
    /* returns 0xFF on any failures */
    u8 ret = 0xff;

-	printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device);
+	printk(BIOS_DEBUG, "spd_read_byte dev %04x", device);
    if (device == DIMM0) {
    	for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
    		if (spd_table[i].address == address) {
    			ret = spd_table[i].data;
    		}
    	}
+
+		if (i == ARRAY_SIZE(spd_table))
+			printk(BIOS_DEBUG, " addr %02x does not exist in SPD table",
+				address);
    }

printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret);

Modified: coreboot-v3/mainboard/artecgroup/dbe62/Makefile
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe62/Makefile	2008-03-06 23:18:13 UTC (rev 635)
+++ coreboot-v3/mainboard/artecgroup/dbe62/Makefile	2008-03-06 23:33:59 UTC (rev 636)
@@ -23,7 +23,7 @@

INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
    	$(src)/northbridge/amd/geodelx/raminit.c \
-		$(src)/arch/x86/geodelx/geodelx.c
+		$(src)/arch/x86/geodelx/geodelx.c $(src)/lib/ramtest.c

STAGE2_MAINBOARD_OBJ =

Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe62/dts	2008-03-06 23:18:13 UTC (rev 635)
+++ coreboot-v3/mainboard/artecgroup/dbe62/dts	2008-03-06 23:33:59 UTC (rev 636)
@@ -43,6 +43,12 @@
    		/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. 
    		 * See virtual PIC spec. */
    		enable_gpio_int_route = "0x0D0C0700";
+			/* we use com2 since that is on the dongle */
+			com2_enable = "1";
+			/* Set com2 address to be COM1 */
+			com2_address = "0x3f8";
+			/* Set com2 IRQ to be what is usually COM1 */
+			com2_irq = "4";
    	};
    };
 };

Modified: coreboot-v3/mainboard/artecgroup/dbe62/initram.c
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe62/initram.c	2008-03-06 23:18:13 UTC (rev 635)
+++ coreboot-v3/mainboard/artecgroup/dbe62/initram.c	2008-03-06 23:33:59 UTC (rev 636)
@@ -53,7 +53,7 @@

/* Save space by using a short list of SPD values used by Geode LX Memory init */
 static const struct spd_entry spd_table[] = {
-	{SPD_ACCEPTABLE_CAS_LATENCIES, 0x10},
+	{SPD_ACCEPTABLE_CAS_LATENCIES, 0xe},
    {SPD_BANK_DENSITY, 0x40},
    {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff},
    {SPD_MEMORY_TYPE, 7},
@@ -63,7 +63,7 @@
    {SPD_PRIMARY_SDRAM_WIDTH, 8},
    {SPD_NUM_DIMM_BANKS, 1},
    {SPD_NUM_COLUMNS, 0xa},
-	{SPD_NUM_ROWS, 3},
+	{SPD_NUM_ROWS, 13},
    {SPD_REFRESH, 0x3a},
    {SPD_SDRAM_CYCLE_TIME_2ND, 60},
    {SPD_SDRAM_CYCLE_TIME_3RD, 75},
@@ -87,13 +87,18 @@
    /* returns 0xFF on any failures */
    u8 ret = 0xff;

-	printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device);
+	printk(BIOS_DEBUG, "spd_read_byte dev %04x", device);
    if (device == DIMM0) {
    	for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
    		if (spd_table[i].address == address) {
    			ret = spd_table[i].data;
+				break;
    		}
    	}
+
+		if (i == ARRAY_SIZE(spd_table))
+			printk(BIOS_DEBUG, " addr %02x does not exist in SPD table",
+				address);
    }

printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret);
@@ -147,7 +152,7 @@
    printk(BIOS_DEBUG, "done sdram enable\n");

/* Check low memory */
-	/*ram_check(0x00000000, 640*1024); */
+	ram_check(0x00000000, 640*1024);

printk(BIOS_DEBUG, "stage1 returns\n");
    return 0;

Modified: coreboot-v3/mainboard/artecgroup/dbe62/stage1.c
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe62/stage1.c	2008-03-06 23:18:13 UTC (rev 635)
+++ coreboot-v3/mainboard/artecgroup/dbe62/stage1.c	2008-03-06 23:33:59 UTC (rev 636)
@@ -58,7 +58,7 @@
     * NOTE: Must do this AFTER the early_setup! It is counting on some
     * early MSR setup for the CS5536.
     */
-	cs5536_setup_onchipuart();
+	cs5536_setup_onchipuart2();
 }

void mainboard_pre_payload(void)

Modified: coreboot-v3/mainboard/pcengines/alix1c/initram.c
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/initram.c	2008-03-06 23:18:13 UTC (rev 635)
+++ coreboot-v3/mainboard/pcengines/alix1c/initram.c	2008-03-06 23:33:59 UTC (rev 636)
@@ -97,13 +97,17 @@
    /* returns 0xFF on any failures */
    u8 ret = 0xff;

-	printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device);
+	printk(BIOS_DEBUG, "spd_read_byte dev %04x", device);
    if (device == DIMM0) {
    	for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
    		if (spd_table[i].address == address) {
    			ret = spd_table[i].data;
+				break;
    		}
    	}
+		if (i == ARRAY_SIZE(spd_table))
+			printk(BIOS_DEBUG, " addr %02x does not exist in SPD table",
+				address);
    }

printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret);

Modified: coreboot-v3/northbridge/amd/geodelx/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/raminit.c	2008-03-06 23:18:13 UTC (rev 635)
+++ coreboot-v3/northbridge/amd/geodelx/raminit.c	2008-03-06 23:33:59 UTC (rev 636)
@@ -130,6 +130,7 @@
    /* Module Density * Module Banks */
    /* Shift to multiply by the number of DIMM banks. */
    dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1;
+	printk(BIOS_DEBUG, "DIMM size is %x\n", dimm_size);
    banner(BIOS_DEBUG, "BEFORT CTZ");
    dimm_size = __builtin_ctz(dimm_size);
    banner(BIOS_DEBUG, "TEST DIMM SIZE>8");
@@ -183,6 +184,7 @@
    banner(BIOS_DEBUG, "RDMSR CF07");
    msr = rdmsr(MC_CF07_DATA);
    banner(BIOS_DEBUG, "WRMSR CF07");
+	printk(BIOS_DEBUG, "CF07(%x): %08x.%08x\n", MC_CF07_DATA, msr.hi, msr.lo);
    if (dimm == dimm0) {
    	msr.hi &= 0xFFFF0000;
    	msr.hi |= dimm_setting;
@@ -223,6 +225,7 @@
    /* Turn SPD ns time into MHz. Check what the asm does to this math. */
    speed = 2 * ((10000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F))));

+	printk(BIOS_DEBUG, "ddr max speed is %d\n", speed);
    /* Current speed > max speed? */
    if (geode_link_speed() > speed) {
    	printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink speed\n");
@@ -266,6 +269,7 @@
    msr = rdmsr(MC_CF07_DATA);
    msr.lo |= ((rate0 * (geode_link_speed() / 2)) / 16)
    	   << CF07_LOWER_REF_INT_SHIFT;
+	printk(BIOS_DEBUG, "Refresh rate set to %x\n", rate0);
    wrmsr(MC_CF07_DATA, msr);
 }

@@ -385,6 +389,7 @@
    	hlt();
    }

+	printk(BIOS_DEBUG, "Set cas latency to %x\n", spd_byte);
    msr = rdmsr(MC_CF8F_DATA);
    msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
    msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;

Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/cs5536.c	2008-03-06 23:18:13 UTC (rev 635)
+++ coreboot-v3/southbridge/amd/cs5536/cs5536.c	2008-03-06 23:33:59 UTC (rev 636)
@@ -89,6 +89,26 @@
 };

/**
+ * Power button setup.
+ *
+ * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which
+ * controls all voltage rails except Vstandby & Vmem. We need to enable
+ * OUT_AUX1 and OUTPUT_ENABLE in this order.
+ *
+ * @param sb The southbridge config structure. 
+ * If GPIO24 is not enabled then soft-off will not work.
+ */
+static void cs5536_setup_power_button(struct southbridge_amd_cs5536_dts_config *sb )
+{
+	if (!sb->power_button)
+		return;
+	/* TODO: Should be a #define? */
+	outl(0x40020000, PMS_IO_BASE + 0x40);
+	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
+	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
+}
+
+/**
  * Program ACPI LBAR and initialize ACPI registers.
  */
 static void pm_chipset_init(void)
@@ -617,6 +637,8 @@
    if (sb->enable_ide)
    	ide_init(dev);

+	cs5536_setup_power_button(sb);
+
    printk(BIOS_SPEW, "cs5536: %s() Exit\n", __FUNCTION__);
 }

Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.h
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/cs5536.h	2008-03-06 23:18:13 UTC (rev 635)
+++ coreboot-v3/southbridge/amd/cs5536/cs5536.h	2008-03-06 23:33:59 UTC (rev 636)
@@ -444,6 +444,7 @@
 /* Function prototypes */
 void cs5536_disable_internal_uart(void);
 void cs5536_setup_onchipuart(void);
+void cs5536_setup_onchipuart2(void);
 void cs5536_stage1(void);

#endif /* SOUTHBRIDGE_AMD_CS5536_CS5536_H */

Modified: coreboot-v3/southbridge/amd/cs5536/dts
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/dts	2008-03-06 23:18:13 UTC (rev 635)
+++ coreboot-v3/southbridge/amd/cs5536/dts	2008-03-06 23:33:59 UTC (rev 636)
@@ -56,4 +56,12 @@
    com2_enable = "0";
    com2_address = "0x2f8";
    com2_irq = "3";
+
+	/* enable/disable power button. On systems with no power switch, 
+	 * one usually does not want the button enabled. Example: 
+	 * Alix1C, dbe62, dbe61. If you enable this, and the power is 
+	 * hard-wired, the board will turn off after 4 seconds, which is 
+	 * probably not what you want. 
+	 */
+	power_button = "0";
 };

Modified: coreboot-v3/southbridge/amd/cs5536/stage1.c
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/stage1.c	2008-03-06 23:18:13 UTC (rev 635)
+++ coreboot-v3/southbridge/amd/cs5536/stage1.c	2008-03-06 23:33:59 UTC (rev 636)
@@ -113,23 +113,6 @@
 }

/**
- * Power button setup.
- *
- * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which
- * controls all voltage rails except Vstandby & Vmem. We need to enable
- * OUT_AUX1 and OUTPUT_ENABLE in this order.
- *
- * If GPIO24 is not enabled then soft-off will not work.
- */
-static void cs5536_setup_power_button(void)
-{
-	/* TODO: Should be a #define? */
-	outl(0x40020000, PMS_IO_BASE + 0x40);
-	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
-	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
-}
-
-/**
  * Set the various GPIOs.
  *
  * An unknown question at this point is how general this is to all mainboards.
@@ -239,6 +222,40 @@
    wrmsr(MDD_UART1_CONF, msr);
 }

+void cs5536_setup_onchipuart2(void)
+{
+	struct msr msr;
+
+	/* GPIO4 - UART2_TX */
+	/* Set: Output Enable  (0x4) */
+	outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
+	/* Set: OUTAUX1 Select (0x10) */
+	outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
+	/* GPIO4 - UART2_RX */
+	/* Set: Input Enable   (0x20) */
+	outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
+	/* Set: INAUX1 Select  (0x34) */
+	outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
+
+	/* Set: GPIO 3 + 3 Pull Up  (0x18) */
+	outl(GPIOL_3_SET | GPIOL_4_SET, GPIO_IO_BASE + GPIOL_PULLUP_ENABLE);
+
+	/* set address to 3F8 */
+	msr = rdmsr(MDD_LEG_IO);
+	msr.lo |= 0x7 << 20;
+	wrmsr(MDD_LEG_IO, msr);
+
+	/* Bit 1 = DEVEN (device enable)
+	 * Bit 4 = EN_BANKS (allow access to the upper banks
+	 */
+	msr.lo = (1 << 4) | (1 << 1);
+	msr.hi = 0;
+
+	/* enable COM2 */
+	wrmsr(MDD_UART2_CONF, msr);
+}
+
+
 /**
  * Board setup.
  *
@@ -279,5 +296,4 @@
    cs5536_setup_iobase();
    cs5536_setup_smbus_gpio();
    /* cs5536_enable_smbus(); -- Leave this out for now. */
-	cs5536_setup_power_button();
 }