coreboot December 2008

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add atomic ops
by ron minnich 09 Dec '08

09 Dec '08

2 1

[PATCH] v2: 440BX: Multiple DIMM support, part 1
by Uwe Hermann 09 Dec '08

09 Dec '08

See patch. Works fine on hardware, but some settings are still hardcoded for a specific setup (will be fixed in an upcoming follow-up patch). Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

r3807 - trunk/coreboot-v2/src/northbridge/intel/i440bx
by svn＠coreboot.org 09 Dec '08

09 Dec '08

Author: uwe Date: 2008-12-09 17:36:12 +0100 (Tue, 09 Dec 2008) New Revision: 3807 Modified: trunk/coreboot-v2/src/northbridge/intel/i440bx/raminit.c Log: Add (parts of the) support for multiple DIMMs on the Intel 440BX chipset. This is tested on hardware with four 128MB DIMMs and works ok, _iff_ you also fix additional registers (e.g. DRB, RPS, ...) for your setup. This requirement will be eliminated in another upcoming patch (i.e. all of the required settings will be auto-detected). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Joseph Smith <joe(a)settoplinux.org> Modified: trunk/coreboot-v2/src/northbridge/intel/i440bx/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i440bx/raminit.c 2008-12-08 23:51:45 UTC (rev 3806) +++ trunk/coreboot-v2/src/northbridge/intel/i440bx/raminit.c 2008-12-09 16:36:12 UTC (rev 3807) @@ -352,34 +352,66 @@ /** * Send the specified RAM command to all DIMMs. * - * @param TODO - * @param TODO + * @param command The RAM command to send to the DIMM(s). */ -static void do_ram_command(uint32_t command, uint32_t addr_offset) +static void do_ram_command(u32 command) { - int i; - uint16_t reg; + int i, caslatency; + u8 dimm_start, dimm_end; + u16 reg16; + u32 addr, addr_offset; - /* TODO: Support for multiple DIMMs. */ - /* Configure the RAM command. */ - reg = pci_read_config16(NB, SDRAMC); - reg &= 0xff1f; /* Clear bits 7-5. */ - reg |= (uint16_t) (command << 5); - pci_write_config16(NB, SDRAMC, reg); + reg16 = pci_read_config16(NB, SDRAMC); + reg16 &= 0xff1f; /* Clear bits 7-5. */ + reg16 |= (u16) (command << 5); /* Write command into bits 7-5. */ + pci_write_config16(NB, SDRAMC, reg16); - /* RAM_COMMAND_NORMAL affects only the memory controller and - doesn't need to be "sent" to the DIMMs. */ - /* if (command == RAM_COMMAND_NORMAL) return; */ + /* + * RAM_COMMAND_NORMAL affects only the memory controller and + * doesn't need to be "sent" to the DIMMs. + */ + if (command == RAM_COMMAND_NORMAL) + return; - PRINT_DEBUG(" Sending RAM command 0x"); - PRINT_DEBUG_HEX16(reg); - PRINT_DEBUG(" to 0x"); - PRINT_DEBUG_HEX32(0 + addr_offset); // FIXME - PRINT_DEBUG("\r\n"); + /* Send the RAM command to each row of memory. */ + dimm_start = 0; + for (i = 0; i < (DIMM_SOCKETS * 2); i++) { + addr_offset = 0; + caslatency = 3; /* TODO: Dynamically get CAS latency later. */ + if (command == RAM_COMMAND_MRS) { + /* + * MAA[12:11,9:0] must be inverted when sent to DIMM + * 2 or 3 (no inversion if sent to DIMM 0 or 1). + */ + if ((i >= 0 && i <= 3) && caslatency == 3) + addr_offset = 0x1d0; + if ((i >= 4 && i <= 7) && caslatency == 3) + addr_offset = 0x1e28; + if ((i >= 0 && i <= 3) && caslatency == 2) + addr_offset = 0x150; + if ((i >= 4 && i <= 7) && caslatency == 2) + addr_offset = 0x1ea8; + } - /* Read from (DIMM start address + addr_offset). */ - read32(0 + addr_offset); // FIXME + dimm_end = pci_read_config8(NB, DRB + i); + + addr = (dimm_start * 8 * 1024 * 1024) + addr_offset; + if (dimm_end > dimm_start) { +#if 0 + PRINT_DEBUG(" Sending RAM command 0x"); + PRINT_DEBUG_HEX16(reg16); + PRINT_DEBUG(" to 0x"); + PRINT_DEBUG_HEX32(addr); + PRINT_DEBUG("\r\n"); +#endif + + read32(addr); + } + + /* Set the start of the next DIMM. */ + dimm_start = dimm_end; + } } /*----------------------------------------------------------------------------- @@ -469,12 +501,11 @@ /* TODO: Set DRAMC. Don't enable refresh for now. */ pci_write_config8(NB, DRAMC, 0x08); - /* TODO: Set RPS. */ + /* TODO: Set RPS. Needs to be fixed for multiple DIMM support. */ pci_write_config16(NB, RPS, 0x0001); /* TODO: Set SDRAMC. */ - // pci_write_config16(NB, SDRAMC, 0x010f); // FIXME? - pci_write_config16(NB, SDRAMC, 0x0003); // FIXME? + pci_write_config16(NB, SDRAMC, 0x0010); /* SDRAMPWR=1: 4 DIMM config */ /* TODO: Set PGPOL. */ // pci_write_config16(NB, PGPOL, 0x0107); @@ -504,29 +535,29 @@ /* 1. Apply NOP. Wait 200 clock cycles (200us should do). */ PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); - do_ram_command(RAM_COMMAND_NOP, 0); + do_ram_command(RAM_COMMAND_NOP); udelay(200); /* 2. Precharge all. Wait tRP. */ PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); - do_ram_command(RAM_COMMAND_PRECHARGE, 0); + do_ram_command(RAM_COMMAND_PRECHARGE); udelay(1); /* 3. Perform 8 refresh cycles. Wait tRC each time. */ PRINT_DEBUG("RAM Enable 3: CBR\r\n"); for (i = 0; i < 8; i++) { - do_ram_command(RAM_COMMAND_CBR, 0); + do_ram_command(RAM_COMMAND_CBR); udelay(1); } /* 4. Mode register set. Wait two memory cycles. */ PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); - do_ram_command(RAM_COMMAND_MRS, 0x1d0); + do_ram_command(RAM_COMMAND_MRS); udelay(2); /* 5. Normal operation. */ PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); - do_ram_command(RAM_COMMAND_NORMAL, 0); + do_ram_command(RAM_COMMAND_NORMAL); udelay(1); /* 6. Finally enable refresh. */

1 0

[PATCH] flashrom: Group probe function together with associated IDs
by Carl-Daniel Hailfinger 09 Dec '08

09 Dec '08

The flash probe function and the IDs for that specific probe function belong together. Group them together on a single line. We already have chips with multiple probe functions and multiple IDs. This patch is the first step in consolidating the present way of creating a new chip definition for each ID of a given chip into multiple IDs per chip definition. Attached for Gmail users. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-reorderfields/flash.h =================================================================== --- flashrom-reorderfields/flash.h (Revision 3805) +++ flashrom-reorderfields/flash.h (Arbeitskopie) @@ -60,6 +60,7 @@ struct flashchip { const char *vendor; const char *name; + /* * With 32bit manufacture_id and model_id we can cover IDs up to * (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's @@ -67,6 +68,7 @@ */ uint32_t manufacture_id; uint32_t model_id; + int (*probe) (struct flashchip *flash); int total_size; int page_size; @@ -77,7 +79,6 @@ */ uint32_t tested; - int (*probe) (struct flashchip *flash); int (*erase) (struct flashchip *flash); int (*write) (struct flashchip *flash, uint8_t *buf); int (*read) (struct flashchip *flash, uint8_t *buf); Index: flashrom-reorderfields/flashchips.c =================================================================== --- flashrom-reorderfields/flashchips.c (Revision 3805) +++ flashrom-reorderfields/flashchips.c (Arbeitskopie) @@ -30,942 +30,1097 @@ */ struct flashchip flashchips[] = { - /* Vendor, Chip, Vendor ID, Chip ID, + /* Vendor, Chip, + * Vendor ID, Chip ID, Probe function, * Total size (kB), Page size (B), * Test status, - * Probe function, Erase function, Write function, Read function + * Erase function, Write function, Read function */ - {"AMD", "Am29F002(N)BB", AMD_ID, AM_29F002BB, + {"AMD", "Am29F002(N)BB", + AMD_ID, AM_29F002BB, probe_jedec, 256, 256, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_en29f002a + erase_chip_jedec, write_en29f002a }, - {"AMD", "Am29F002(N)BT", AMD_ID, AM_29F002BT, + {"AMD", "Am29F002(N)BT", + AMD_ID, AM_29F002BT, probe_jedec, 256, 256, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_en29f002a + erase_chip_jedec, write_en29f002a }, - {"AMD", "Am29F016D", AMD_ID, AM_29F016D, + {"AMD", "Am29F016D", + AMD_ID, AM_29F016D, probe_29f040b, 2048, 64 * 1024, TEST_UNTESTED, - probe_29f040b, erase_29f040b, write_29f040b + erase_29f040b, write_29f040b }, - {"AMD", "Am29F040B", AMD_ID, AM_29F040B, + {"AMD", "Am29F040B", + AMD_ID, AM_29F040B, probe_29f040b, 512, 64 * 1024, TEST_OK_PREW, - probe_29f040b, erase_29f040b, write_29f040b + erase_29f040b, write_29f040b }, - {"AMD", "Am29LV040B", AMD_ID, AM_29LV040B, + {"AMD", "Am29LV040B", + AMD_ID, AM_29LV040B, probe_29f040b, 512, 64 * 1024, TEST_UNTESTED, - probe_29f040b, erase_29f040b, write_29f040b + erase_29f040b, write_29f040b }, - {"ASD", "AE49F2008", ASD_ID, ASD_AE49F2008, + {"ASD", "AE49F2008", + ASD_ID, ASD_AE49F2008, probe_jedec, 256, 128, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_jedec + erase_chip_jedec, write_jedec }, - {"Atmel", "AT25DF021", ATMEL_ID, AT_25DF021, + {"Atmel", "AT25DF021", + ATMEL_ID, AT_25DF021, probe_spi_rdid, 256, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL, spi_chip_read + NULL, NULL, spi_chip_read }, - {"Atmel", "AT25DF041A", ATMEL_ID, AT_25DF041A, + {"Atmel", "AT25DF041A", + ATMEL_ID, AT_25DF041A, probe_spi_rdid, 512, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL, spi_chip_read + NULL, NULL, spi_chip_read }, - {"Atmel", "AT25DF081", ATMEL_ID, AT_25DF081, + {"Atmel", "AT25DF081", + ATMEL_ID, AT_25DF081, probe_spi_rdid, 1024, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL, spi_chip_read + NULL, NULL, spi_chip_read }, - {"Atmel", "AT25DF161", ATMEL_ID, AT_25DF161, + {"Atmel", "AT25DF161", + ATMEL_ID, AT_25DF161, probe_spi_rdid, 2048, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL, spi_chip_read + NULL, NULL, spi_chip_read }, - {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, + {"Atmel", "AT25DF321", + ATMEL_ID, AT_25DF321, probe_spi_rdid, 4096, 256, TEST_OK_PREW, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"Atmel", "AT25DF321A", ATMEL_ID, AT_25DF321A, + {"Atmel", "AT25DF321A", + ATMEL_ID, AT_25DF321A, probe_spi_rdid, 4096, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL, spi_chip_read + NULL, NULL, spi_chip_read }, - {"Atmel", "AT25DF641", ATMEL_ID, AT_25DF641, + {"Atmel", "AT25DF641", + ATMEL_ID, AT_25DF641, probe_spi_rdid, 8192, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL, spi_chip_read + NULL, NULL, spi_chip_read }, - {"Atmel", "AT25F512B", ATMEL_ID, AT_25F512B, + {"Atmel", "AT25F512B", + ATMEL_ID, AT_25F512B, probe_spi_rdid, 64, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL, spi_chip_read + NULL, NULL, spi_chip_read }, - {"Atmel", "AT25FS010", ATMEL_ID, AT_25FS010, + {"Atmel", "AT25FS010", + ATMEL_ID, AT_25FS010, probe_spi_rdid, 128, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL, spi_chip_read + NULL, NULL, spi_chip_read }, - {"Atmel", "AT25FS040", ATMEL_ID, AT_25FS040, + {"Atmel", "AT25FS040", + ATMEL_ID, AT_25FS040, probe_spi_rdid, 512, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL, spi_chip_read + NULL, NULL, spi_chip_read }, - {"Atmel", "AT26DF041", ATMEL_ID, AT_26DF041, + {"Atmel", "AT26DF041", + ATMEL_ID, AT_26DF041, probe_spi_rdid, 512, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL /* Incompatible Page write */,spi_chip_read + NULL, NULL /* Incompatible Page write */,spi_chip_read }, - {"Atmel", "AT26DF081A", ATMEL_ID, AT_26DF081A, + {"Atmel", "AT26DF081A", + ATMEL_ID, AT_26DF081A, probe_spi_rdid, 1024, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL, spi_chip_read + NULL, NULL, spi_chip_read }, - {"Atmel", "AT26DF161", ATMEL_ID, AT_26DF161, + {"Atmel", "AT26DF161", + ATMEL_ID, AT_26DF161, probe_spi_rdid, 2048, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL, spi_chip_read + NULL, NULL, spi_chip_read }, - {"Atmel", "AT26DF161A", ATMEL_ID, AT_26DF161A, + {"Atmel", "AT26DF161A", + ATMEL_ID, AT_26DF161A, probe_spi_rdid, 2048, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL, spi_chip_read + NULL, NULL, spi_chip_read }, /*The AT26DF321 has the same ID as the AT25DF321. */ - /*{"Atmel", "AT26DF321", ATMEL_ID, AT_26DF321, - 4096, 256, - TEST_UNTESTED, - probe_spi_rdid, NULL, NULL, spi_chip_read - }, - */ + /*{"Atmel", "AT26DF321", + ATMEL_ID, AT_26DF321, probe_spi_rdid, + 4096, 256, + TEST_UNTESTED, + NULL, NULL, spi_chip_read + }, */ - {"Atmel", "AT26F004", ATMEL_ID, AT_26F004, + {"Atmel", "AT26F004", + ATMEL_ID, AT_26F004, probe_spi_rdid, 512, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL /* Incompatible Page write */,spi_chip_read + NULL, NULL /* Incompatible Page write */,spi_chip_read }, - {"Atmel", "AT29C020", ATMEL_ID, AT_29C020, + {"Atmel", "AT29C020", + ATMEL_ID, AT_29C020, probe_jedec, 256, 256, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_jedec + erase_chip_jedec, write_jedec }, - {"Atmel", "AT29C040A", ATMEL_ID, AT_29C040A, + {"Atmel", "AT29C040A", + ATMEL_ID, AT_29C040A, probe_jedec, 512, 256, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_jedec + erase_chip_jedec, write_jedec }, - {"Atmel", "AT45CS1282", ATMEL_ID, AT_45CS1282, + {"Atmel", "AT45CS1282", + ATMEL_ID, AT_45CS1282, probe_spi_rdid, 16896/*!*/, 1056/*!*/, TEST_BAD_READ, - probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL /* Incompatible read */ + NULL, NULL /* Incompatible Page write */, NULL /* Incompatible read */ }, /* No power of two sizes */ - {"Atmel", "AT45DB011D", ATMEL_ID, AT_45DB011D, + {"Atmel", "AT45DB011D", + ATMEL_ID, AT_45DB011D, probe_spi_rdid, 128/*!*/, 256/*!*/, TEST_BAD_READ, - probe_spi_rdid, NULL, NULL, NULL + NULL, NULL, NULL }, /* Size can only be determined from status register */ - {"Atmel", "AT45DB021D", ATMEL_ID, AT_45DB021D, + {"Atmel", "AT45DB021D", + ATMEL_ID, AT_45DB021D, probe_spi_rdid, 256/*!*/, 256/*!*/, TEST_BAD_READ, - probe_spi_rdid, NULL, NULL, NULL + NULL, NULL, NULL }, /* Size can only be determined from status register */ - {"Atmel", "AT45DB041D", ATMEL_ID, AT_45DB041D, + {"Atmel", "AT45DB041D", + ATMEL_ID, AT_45DB041D, probe_spi_rdid, 512/*!*/, 256/*!*/, TEST_BAD_READ, - probe_spi_rdid, NULL, NULL, NULL + NULL, NULL, NULL }, /* Size can only be determined from status register */ - {"Atmel", "AT45DB081D", ATMEL_ID, AT_45DB081D, + {"Atmel", "AT45DB081D", + ATMEL_ID, AT_45DB081D, probe_spi_rdid, 1024/*!*/, 256/*!*/, TEST_BAD_READ, - probe_spi_rdid, NULL, NULL, NULL + NULL, NULL, NULL }, /* Size can only be determined from status register */ - {"Atmel", "AT45DB161D", ATMEL_ID, AT_45DB161D, + {"Atmel", "AT45DB161D", + ATMEL_ID, AT_45DB161D, probe_spi_rdid, 2048/*!*/, 512/*!*/, TEST_BAD_READ, - probe_spi_rdid, NULL, NULL, NULL + NULL, NULL, NULL }, /* Size can only be determined from status register */ - {"Atmel", "AT45DB321C", ATMEL_ID, AT_45DB321C, + {"Atmel", "AT45DB321C", + ATMEL_ID, AT_45DB321C, probe_spi_rdid, 4224/*!*/, 528/*!*/, TEST_BAD_READ, - probe_spi_rdid, NULL, NULL, NULL /* Incompatible read */ + NULL, NULL, NULL /* Incompatible read */ }, /* No power of two sizes */ - {"Atmel", "AT45DB321D", ATMEL_ID, AT_45DB321D, + {"Atmel", "AT45DB321D", + ATMEL_ID, AT_45DB321D, probe_spi_rdid, 4096/*!*/, 512/*!*/, TEST_BAD_READ, - probe_spi_rdid, NULL, NULL, NULL + NULL, NULL, NULL }, /* Size can only be determined from status register */ - {"Atmel", "AT45DB642D", ATMEL_ID, AT_45DB642D, + {"Atmel", "AT45DB642D", + ATMEL_ID, AT_45DB642D, probe_spi_rdid, 8192/*!*/, 1024/*!*/, TEST_BAD_READ, - probe_spi_rdid, NULL, NULL, NULL + NULL, NULL, NULL }, /* Size can only be determined from status register */ - {"Atmel", "AT49F002(N)", ATMEL_ID, AT_49F002N, + {"Atmel", "AT49F002(N)", + ATMEL_ID, AT_49F002N, probe_jedec, 256, 256, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_49f002 + erase_chip_jedec, write_49f002 }, - {"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT, + {"Atmel", "AT49F002(N)T", + ATMEL_ID, AT_49F002NT, probe_jedec, 256, 256, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_49f002 + erase_chip_jedec, write_49f002 }, - {"AMIC", "A25L40P", AMIC_ID, AMIC_A25L40P, + {"AMIC", "A25L40P", + AMIC_ID, AMIC_A25L40P, probe_spi_rdid4, 512, 256, TEST_OK_PREW, - probe_spi_rdid4, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"AMIC", "A29002B", AMIC_ID_NOPREFIX, AMIC_A29002B, + {"AMIC", "A29002B", + AMIC_ID_NOPREFIX, AMIC_A29002B, probe_29f002, 256, 64 * 1024, TEST_UNTESTED, - probe_29f002, erase_29f002, write_29f002 + erase_29f002, write_29f002 }, - {"AMIC", "A29002T", AMIC_ID_NOPREFIX, AMIC_A29002T, + {"AMIC", "A29002T", + AMIC_ID_NOPREFIX, AMIC_A29002T, probe_29f002, 256, 64 * 1024, TEST_OK_PREW, - probe_29f002, erase_29f002, write_29f002 + erase_29f002, write_29f002 }, - {"AMIC", "A29040B", AMIC_ID_NOPREFIX, AMIC_A29040B, + {"AMIC", "A29040B", + AMIC_ID_NOPREFIX, AMIC_A29040B, probe_29f040b, 512, 64 * 1024, TEST_OK_PR, - probe_29f040b, erase_29f040b, write_29f040b + erase_29f040b, write_29f040b }, - {"AMIC", "A49LF040A", AMIC_ID_NOPREFIX, AMIC_A49LF040A, + {"AMIC", "A49LF040A", + AMIC_ID_NOPREFIX, AMIC_A49LF040A, probe_49fl00x, 512, 64 * 1024, TEST_OK_PREW, - probe_49fl00x, erase_49fl00x, write_49fl00x + erase_49fl00x, write_49fl00x }, - {"EMST", "F49B002UA", EMST_ID, EMST_F49B002UA, + {"EMST", "F49B002UA", + EMST_ID, EMST_F49B002UA, probe_jedec, 256, 4096, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_49f002 + erase_chip_jedec, write_49f002 }, - {"EON", "EN29F002(A)(N)B", EON_ID, EN_29F002B, + {"EON", "EN29F002(A)(N)B", + EON_ID, EN_29F002B, probe_jedec, 256, 256, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_en29f002a + erase_chip_jedec, write_en29f002a }, - {"EON", "EN29F002(A)(N)T", EON_ID, EN_29F002T, + {"EON", "EN29F002(A)(N)T", + EON_ID, EN_29F002T, probe_jedec, 256, 256, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_en29f002a + erase_chip_jedec, write_en29f002a }, - {"Fujitsu", "MBM29F004BC", FUJITSU_ID, MBM29F004BC, + {"Fujitsu", "MBM29F004BC", + FUJITSU_ID, MBM29F004BC, probe_jedec, 512, 64 * 1024, TEST_UNTESTED, - probe_jedec, NULL, NULL + NULL, NULL }, - {"Fujitsu", "MBM29F004TC", FUJITSU_ID, MBM29F004TC, + {"Fujitsu", "MBM29F004TC", + FUJITSU_ID, MBM29F004TC, probe_jedec, 512, 64 * 1024, TEST_UNTESTED, - probe_jedec, NULL, NULL + NULL, NULL }, - {"Fujitsu", "MBM29F400BC", FUJITSU_ID, MBM29F400BC, + {"Fujitsu", "MBM29F400BC", + FUJITSU_ID, MBM29F400BC, probe_m29f400bt, 512, 64 * 1024, TEST_UNTESTED, - probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt + erase_m29f400bt, write_coreboot_m29f400bt }, - {"Fujitsu", "MBM29F400TC", FUJITSU_ID, MBM29F400TC, + {"Fujitsu", "MBM29F400TC", + FUJITSU_ID, MBM29F400TC, probe_m29f400bt, 512, 64 * 1024, TEST_UNTESTED, - probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt + erase_m29f400bt, write_coreboot_m29f400bt }, - {"Intel", "82802AB", INTEL_ID, 173, + {"Intel", "82802AB", + INTEL_ID, 173, probe_82802ab, 512, 64 * 1024, TEST_OK_PREW, - probe_82802ab, erase_82802ab, write_82802ab + erase_82802ab, write_82802ab }, - {"Intel", "82802AC", INTEL_ID, 172, + {"Intel", "82802AC", + INTEL_ID, 172, probe_82802ab, 1024, 64 * 1024, TEST_OK_PREW, - probe_82802ab, erase_82802ab, write_82802ab + erase_82802ab, write_82802ab }, - {"Macronix", "MX25L512", MX_ID, MX_25L512, + {"Macronix", "MX25L512", + MX_ID, MX_25L512, probe_spi_rdid, 64, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"Macronix", "MX25L1005", MX_ID, MX_25L1005, + {"Macronix", "MX25L1005", + MX_ID, MX_25L1005, probe_spi_rdid, 128, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"Macronix", "MX25L2005", MX_ID, MX_25L2005, + {"Macronix", "MX25L2005", + MX_ID, MX_25L2005, probe_spi_rdid, 256, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"Macronix", "MX25L4005", MX_ID, MX_25L4005, + {"Macronix", "MX25L4005", + MX_ID, MX_25L4005, probe_spi_rdid, 512, 256, TEST_OK_PREW, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"Macronix", "MX25L8005", MX_ID, MX_25L8005, + {"Macronix", "MX25L8005", + MX_ID, MX_25L8005, probe_spi_rdid, 1024, 256, TEST_OK_PREW, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"Macronix", "MX25L1605", MX_ID, MX_25L1605, + {"Macronix", "MX25L1605", + MX_ID, MX_25L1605, probe_spi_rdid, 2048, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"Macronix", "MX25L3205", MX_ID, MX_25L3205, + {"Macronix", "MX25L3205", + MX_ID, MX_25L3205, probe_spi_rdid, 4096, 256, TEST_OK_PREW, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"Macronix", "MX25L6405", MX_ID, MX_25L6405, + {"Macronix", "MX25L6405", + MX_ID, MX_25L6405, probe_spi_rdid, 8192, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"Macronix", "MX29F002B", MX_ID, MX_29F002B, + {"Macronix", "MX29F002B", + MX_ID, MX_29F002B, probe_29f002, 256, 64 * 1024, TEST_UNTESTED, - probe_29f002, erase_29f002, write_29f002 + erase_29f002, write_29f002 }, - {"Macronix", "MX29F002T", MX_ID, MX_29F002T, + {"Macronix", "MX29F002T", + MX_ID, MX_29F002T, probe_29f002, 256, 64 * 1024, TEST_UNTESTED, - probe_29f002, erase_29f002, write_29f002 + erase_29f002, write_29f002 }, - {"Numonyx", "M25PE10", ST_ID, 0x8011, + {"Numonyx", "M25PE10", + ST_ID, 0x8011, probe_spi_rdid, 128, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read + spi_chip_erase_d8, spi_chip_write, spi_chip_read }, - {"Numonyx", "M25PE20", ST_ID, 0x8012, + {"Numonyx", "M25PE20", + ST_ID, 0x8012, probe_spi_rdid, 256, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read + spi_chip_erase_d8, spi_chip_write, spi_chip_read }, - {"Numonyx", "M25PE40", ST_ID, 0x8013, + {"Numonyx", "M25PE40", + ST_ID, 0x8013, probe_spi_rdid, 256, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read + spi_chip_erase_d8, spi_chip_write, spi_chip_read }, - {"Numonyx", "M25PE80", ST_ID, 0x8014, + {"Numonyx", "M25PE80", + ST_ID, 0x8014, probe_spi_rdid, 1024, 256, TEST_OK_PREW, - probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read + spi_chip_erase_d8, spi_chip_write, spi_chip_read }, - {"Numonyx", "M25PE16", ST_ID, 0x8015, + {"Numonyx", "M25PE16", + ST_ID, 0x8015, probe_spi_rdid, 2048, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read + spi_chip_erase_d8, spi_chip_write, spi_chip_read }, - {"PMC", "Pm25LV010", PMC_ID, PMC_25LV010, + {"PMC", "Pm25LV010", + PMC_ID, PMC_25LV010, probe_spi_rdid, 128, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"PMC", "Pm25LV016B", PMC_ID, PMC_25LV016B, + {"PMC", "Pm25LV016B", + PMC_ID, PMC_25LV016B, probe_spi_rdid, 2048, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"PMC", "Pm25LV020", PMC_ID, PMC_25LV020, + {"PMC", "Pm25LV020", + PMC_ID, PMC_25LV020, probe_spi_rdid, 256, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"PMC", "Pm25LV040", PMC_ID, PMC_25LV040, + {"PMC", "Pm25LV040", + PMC_ID, PMC_25LV040, probe_spi_rdid, 512, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"PMC", "Pm25LV080B", PMC_ID, PMC_25LV080B, + {"PMC", "Pm25LV080B", + PMC_ID, PMC_25LV080B, probe_spi_rdid, 1024, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"PMC", "Pm25LV512", PMC_ID, PMC_25LV512, + {"PMC", "Pm25LV512", + PMC_ID, PMC_25LV512, probe_spi_rdid, 64, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"PMC", "Pm49FL002", PMC_ID_NOPREFIX, PMC_49FL002, + {"PMC", "Pm49FL002", + PMC_ID_NOPREFIX, PMC_49FL002, probe_49fl00x, 256, 16 * 1024, TEST_OK_PREW, - probe_49fl00x, erase_49fl00x, write_49fl00x + erase_49fl00x, write_49fl00x }, - {"PMC", "Pm49FL004", PMC_ID_NOPREFIX,PMC_49FL004, + {"PMC", "Pm49FL004", + PMC_ID_NOPREFIX,PMC_49FL004, probe_49fl00x, 512, 64 * 1024, TEST_OK_PREW, - probe_49fl00x, erase_49fl00x, write_49fl00x + erase_49fl00x, write_49fl00x }, - {"Sharp", "LHF00L04", SHARP_ID, SHARP_LHF00L04, + {"Sharp", "LHF00L04", + SHARP_ID, SHARP_LHF00L04, probe_lhf00l04, 1024, 64 * 1024, TEST_UNTESTED, - probe_lhf00l04, erase_lhf00l04, write_lhf00l04 + erase_lhf00l04, write_lhf00l04 }, - {"Spansion", "S25FL016A", SPANSION_ID, SPANSION_S25FL016A, + {"Spansion", "S25FL016A", + SPANSION_ID, SPANSION_S25FL016A, probe_spi_rdid, 2048, 256, TEST_OK_PREW, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"SST", "SST25VF016B", SST_ID, SST_25VF016B, + {"SST", "SST25VF016B", + SST_ID, SST_25VF016B, probe_spi_rdid, 2048, 256, TEST_OK_PREW, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"SST", "SST25VF032B", SST_ID, SST_25VF032B, + {"SST", "SST25VF032B", + SST_ID, SST_25VF032B, probe_spi_rdid, 4096, 256, TEST_OK_PREW, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"SST", "SST25VF040B", SST_ID, SST_25VF040B, + {"SST", "SST25VF040B", + SST_ID, SST_25VF040B, probe_spi_rdid, 512, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"SST", "SST25VF080B", SST_ID, SST_25VF080B, + {"SST", "SST25VF080B", + SST_ID, SST_25VF080B, probe_spi_rdid, 1024, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_60_c7, spi_chip_write, spi_chip_read + spi_chip_erase_60_c7, spi_chip_write, spi_chip_read }, - {"SST", "SST28SF040A", SST_ID, SST_28SF040, + {"SST", "SST28SF040A", + SST_ID, SST_28SF040, probe_28sf040, 512, 256, TEST_UNTESTED, - probe_28sf040, erase_28sf040, write_28sf040 + erase_28sf040, write_28sf040 }, - {"SST", "SST29EE010", SST_ID, SST_29EE010, + {"SST", "SST29EE010", + SST_ID, SST_29EE010, probe_jedec, 128, 128, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_jedec + erase_chip_jedec, write_jedec }, - {"SST", "SST29LE010", SST_ID, SST_29LE010, + {"SST", "SST29LE010", + SST_ID, SST_29LE010, probe_jedec, 128, 128, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_jedec + erase_chip_jedec, write_jedec }, - {"SST", "SST29EE020A", SST_ID, SST_29EE020A, + {"SST", "SST29EE020A", + SST_ID, SST_29EE020A, probe_jedec, 256, 128, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_jedec + erase_chip_jedec, write_jedec }, - {"SST", "SST29LE020", SST_ID, SST_29LE020, + {"SST", "SST29LE020", + SST_ID, SST_29LE020, probe_jedec, 256, 128, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_jedec + erase_chip_jedec, write_jedec }, - {"SST", "SST39SF010A", SST_ID, SST_39SF010, + {"SST", "SST39SF010A", + SST_ID, SST_39SF010, probe_jedec, 128, 4096, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_39sf020 + erase_chip_jedec, write_39sf020 }, - {"SST", "SST39SF020A", SST_ID, SST_39SF020, + {"SST", "SST39SF020A", + SST_ID, SST_39SF020, probe_jedec, 256, 4096, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_39sf020 + erase_chip_jedec, write_39sf020 }, - {"SST", "SST39SF040", SST_ID, SST_39SF040, + {"SST", "SST39SF040", + SST_ID, SST_39SF040, probe_jedec, 512, 4096, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_39sf020 + erase_chip_jedec, write_39sf020 }, - {"SST", "SST39VF512", SST_ID, SST_39VF512, + {"SST", "SST39VF512", + SST_ID, SST_39VF512, probe_jedec, 64, 4096, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_39sf020 + erase_chip_jedec, write_39sf020 }, - {"SST", "SST39VF010", SST_ID, SST_39VF010, + {"SST", "SST39VF010", + SST_ID, SST_39VF010, probe_jedec, 128, 4096, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_39sf020 + erase_chip_jedec, write_39sf020 }, - {"SST", "SST39VF020", SST_ID, SST_39VF020, + {"SST", "SST39VF020", + SST_ID, SST_39VF020, probe_jedec, 256, 4096, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_39sf020 + erase_chip_jedec, write_39sf020 }, - {"SST", "SST39VF040", SST_ID, SST_39VF040, + {"SST", "SST39VF040", + SST_ID, SST_39VF040, probe_jedec, 512, 4096, TEST_OK_PROBE, - probe_jedec, erase_chip_jedec, write_39sf020 - }, /* assume similar to 004B, ignoring data sheet */ + erase_chip_jedec, write_39sf020 + }, - {"SST", "SST49LF002A/B", SST_ID, SST_49LF002A, + {"SST", "SST49LF002A/B", + SST_ID, SST_49LF002A, probe_sst_fwhub, 256, 16 * 1024, TEST_OK_PREW, - probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub + erase_sst_fwhub, write_sst_fwhub }, - {"SST", "SST49LF003A/B", SST_ID, SST_49LF003A, + {"SST", "SST49LF003A/B", + SST_ID, SST_49LF003A, probe_sst_fwhub, 384, 64 * 1024, TEST_UNTESTED, - probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub + erase_sst_fwhub, write_sst_fwhub }, - {"SST", "SST49LF004A/B", SST_ID, SST_49LF004A, + {"SST", "SST49LF004A/B", + SST_ID, SST_49LF004A, probe_sst_fwhub, 512, 64 * 1024, TEST_OK_PREW, - probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub + erase_sst_fwhub, write_sst_fwhub }, - {"SST", "SST49LF004C", SST_ID, SST_49LF004C, + {"SST", "SST49LF004C", + SST_ID, SST_49LF004C, probe_49lfxxxc, 512, 4 * 1024, TEST_UNTESTED, - probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc + erase_49lfxxxc, write_49lfxxxc }, - {"SST", "SST49LF008A", SST_ID, SST_49LF008A, + {"SST", "SST49LF008A", + SST_ID, SST_49LF008A, probe_sst_fwhub, 1024, 64 * 1024, TEST_OK_PREW, - probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub + erase_sst_fwhub, write_sst_fwhub }, - {"SST", "SST49LF008C", SST_ID, SST_49LF008C, + {"SST", "SST49LF008C", + SST_ID, SST_49LF008C, probe_49lfxxxc, 1024, 4 * 1024, TEST_UNTESTED, - probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc + erase_49lfxxxc, write_49lfxxxc }, - {"SST", "SST49LF016C", SST_ID, SST_49LF016C, + {"SST", "SST49LF016C", + SST_ID, SST_49LF016C, probe_49lfxxxc, 2048, 4 * 1024, TEST_OK_PREW, - probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc + erase_49lfxxxc, write_49lfxxxc }, - {"SST", "SST49LF020A", SST_ID, SST_49LF020A, + {"SST", "SST49LF020A", + SST_ID, SST_49LF020A, probe_jedec, 256, 16 * 1024, TEST_UNTESTED, - probe_jedec, erase_49lf040, write_49lf040 + erase_49lf040, write_49lf040 }, - {"SST", "SST49LF040", SST_ID, SST_49LF040, + {"SST", "SST49LF040", + SST_ID, SST_49LF040, probe_jedec, 512, 4096, TEST_OK_PREW, - probe_jedec, erase_49lf040, write_49lf040 + erase_49lf040, write_49lf040 }, - {"SST", "SST49LF040B", SST_ID, SST_49LF040B, + {"SST", "SST49LF040B", + SST_ID, SST_49LF040B, probe_sst_fwhub, 512, 64 * 1024, TEST_OK_PREW, - probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub + erase_sst_fwhub, write_sst_fwhub }, - {"SST", "SST49LF080A", SST_ID, SST_49LF080A, + {"SST", "SST49LF080A", + SST_ID, SST_49LF080A, probe_jedec, 1024, 4096, TEST_OK_PREW, - probe_jedec, erase_49lf040, write_49lf040 + erase_49lf040, write_49lf040 }, - {"SST", "SST49LF160C", SST_ID, SST_49LF160C, + {"SST", "SST49LF160C", + SST_ID, SST_49LF160C, probe_49lfxxxc, 2048, 4 * 1024, TEST_OK_PREW, - probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc + erase_49lfxxxc, write_49lfxxxc }, - {"ST", "M25P05-A", ST_ID, ST_M25P05A, + {"ST", "M25P05-A", + ST_ID, ST_M25P05A, probe_spi_rdid, 64, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"ST", "M25P10-A", ST_ID, ST_M25P10A, + {"ST", "M25P10-A", + ST_ID, ST_M25P10A, probe_spi_rdid, 128, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"ST", "M25P20", ST_ID, ST_M25P20, + {"ST", "M25P20", + ST_ID, ST_M25P20, probe_spi_rdid, 256, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"ST", "M25P40", ST_ID, ST_M25P40, + {"ST", "M25P40", + ST_ID, ST_M25P40, probe_spi_rdid, 512, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"ST", "M25P40-old", ST_ID, ST_M25P40_RES, + {"ST", "M25P40-old", + ST_ID, ST_M25P40_RES, probe_spi_res, 512, 256, TEST_UNTESTED, - probe_spi_res, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"ST", "M25P80", ST_ID, ST_M25P80, + {"ST", "M25P80", + ST_ID, ST_M25P80, probe_spi_rdid, 1024, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"ST", "M25P16", ST_ID, ST_M25P16, + {"ST", "M25P16", + ST_ID, ST_M25P16, probe_spi_rdid, 2048, 256, TEST_OK_PREW, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"ST", "M25P32", ST_ID, ST_M25P32, + {"ST", "M25P32", + ST_ID, ST_M25P32, probe_spi_rdid, 4096, 256, TEST_OK_PREW, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"ST", "M25P64", ST_ID, ST_M25P64, + {"ST", "M25P64", + ST_ID, ST_M25P64, probe_spi_rdid, 8192, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"ST", "M25P128", ST_ID, ST_M25P128, + {"ST", "M25P128", + ST_ID, ST_M25P128, probe_spi_rdid, 16384, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"ST", "M29F002B", ST_ID, ST_M29F002B, + {"ST", "M29F002B", + ST_ID, ST_M29F002B, probe_jedec, 256, 64 * 1024, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_jedec + erase_chip_jedec, write_jedec }, - {"ST", "M29F002T/NT", ST_ID, ST_M29F002T, + {"ST", "M29F002T/NT", + ST_ID, ST_M29F002T, probe_jedec, 256, 64 * 1024, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_jedec + erase_chip_jedec, write_jedec }, - {"ST", "M29F040B", ST_ID, ST_M29F040B, + {"ST", "M29F040B", + ST_ID, ST_M29F040B, probe_29f040b, 512, 64 * 1024, TEST_OK_PREW, - probe_29f040b, erase_29f040b, write_29f040b + erase_29f040b, write_29f040b }, - {"ST", "M29F400BT", ST_ID, ST_M29F400BT, + {"ST", "M29F400BT", + ST_ID, ST_M29F400BT, probe_m29f400bt, 512, 64 * 1024, TEST_UNTESTED, - probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt + erase_m29f400bt, write_coreboot_m29f400bt }, - {"ST", "M29W010B", ST_ID, ST_M29W010B, + {"ST", "M29W010B", + ST_ID, ST_M29W010B, probe_jedec, 128, 16 * 1024, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_jedec + erase_chip_jedec, write_jedec }, - {"ST", "M29W040B", ST_ID, ST_M29W040B, + {"ST", "M29W040B", + ST_ID, ST_M29W040B, probe_jedec, 512, 64 * 1024, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_jedec + erase_chip_jedec, write_jedec }, - {"ST", "M50FLW040A", ST_ID, ST_M50FLW040A, + {"ST", "M50FLW040A", + ST_ID, ST_M50FLW040A, probe_stm50flw0x0x, 512, 64 * 1024, TEST_UNTESTED, - probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x + erase_stm50flw0x0x, write_stm50flw0x0x }, - {"ST", "M50FLW040B", ST_ID, ST_M50FLW040B, + {"ST", "M50FLW040B", + ST_ID, ST_M50FLW040B, probe_stm50flw0x0x, 512, 64 * 1024, TEST_UNTESTED, - probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x + erase_stm50flw0x0x, write_stm50flw0x0x }, - {"ST", "M50FLW080A", ST_ID, ST_M50FLW080A, + {"ST", "M50FLW080A", + ST_ID, ST_M50FLW080A, probe_stm50flw0x0x, 1024, 64 * 1024, TEST_OK_PREW, - probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x + erase_stm50flw0x0x, write_stm50flw0x0x }, - {"ST", "M50FLW080B", ST_ID, ST_M50FLW080B, + {"ST", "M50FLW080B", + ST_ID, ST_M50FLW080B, probe_stm50flw0x0x, 1024, 64 * 1024, TEST_UNTESTED, - probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x + erase_stm50flw0x0x, write_stm50flw0x0x }, - {"ST", "M50FW002", ST_ID, ST_M50FW002, + {"ST", "M50FW002", + ST_ID, ST_M50FW002, probe_49lfxxxc, 256, 64 * 1024, TEST_UNTESTED, - probe_49lfxxxc, NULL, NULL + NULL, NULL }, - {"ST", "M50FW016", ST_ID, ST_M50FW016, + {"ST", "M50FW016", + ST_ID, ST_M50FW016, probe_82802ab, 2048, 64 * 1024, TEST_UNTESTED, - probe_82802ab, erase_82802ab, write_82802ab + erase_82802ab, write_82802ab }, - {"ST", "M50FW040", ST_ID, ST_M50FW040, + {"ST", "M50FW040", + ST_ID, ST_M50FW040, probe_82802ab, 512, 64 * 1024, TEST_OK_PREW, - probe_82802ab, erase_82802ab, write_82802ab + erase_82802ab, write_82802ab }, - {"ST", "M50FW080", ST_ID, ST_M50FW080, + {"ST", "M50FW080", + ST_ID, ST_M50FW080, probe_82802ab, 1024, 64 * 1024, TEST_UNTESTED, - probe_82802ab, erase_82802ab, write_82802ab + erase_82802ab, write_82802ab }, - {"ST", "M50LPW116", ST_ID, ST_M50LPW116, + {"ST", "M50LPW116", + ST_ID, ST_M50LPW116, probe_jedec, 2048, 64 * 1024, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_jedec + erase_chip_jedec, write_jedec }, - {"SyncMOS", "S29C31004T", SYNCMOS_ID, S29C31004T, + {"SyncMOS", "S29C31004T", + SYNCMOS_ID, S29C31004T, probe_jedec, 512, 128, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_49f002 + erase_chip_jedec, write_49f002 }, - {"SyncMOS", "S29C51001T", SYNCMOS_ID, S29C51001T, + {"SyncMOS", "S29C51001T", + SYNCMOS_ID, S29C51001T, probe_jedec, 128, 128, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_49f002 + erase_chip_jedec, write_49f002 }, - {"SyncMOS", "S29C51002T", SYNCMOS_ID, S29C51002T, + {"SyncMOS", "S29C51002T", + SYNCMOS_ID, S29C51002T, probe_jedec, 256, 128, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_49f002 + erase_chip_jedec, write_49f002 }, - {"SyncMOS", "S29C51004T", SYNCMOS_ID, S29C51004T, + {"SyncMOS", "S29C51004T", + SYNCMOS_ID, S29C51004T, probe_jedec, 512, 128, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_49f002 + erase_chip_jedec, write_49f002 }, - {"Winbond", "W25x10", WINBOND_NEX_ID, W_25X10, + {"Winbond", "W25x10", + WINBOND_NEX_ID, W_25X10, probe_spi_rdid, 128, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"Winbond", "W25x20", WINBOND_NEX_ID, W_25X20, + {"Winbond", "W25x20", + WINBOND_NEX_ID, W_25X20, probe_spi_rdid, 256, 256, TEST_UNTESTED, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"Winbond", "W25x40", WINBOND_NEX_ID, W_25X40, + {"Winbond", "W25x40", + WINBOND_NEX_ID, W_25X40, probe_spi_rdid, 512, 256, TEST_OK_PREW, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"Winbond", "W25x80", WINBOND_NEX_ID, W_25X80, + {"Winbond", "W25x80", + WINBOND_NEX_ID, W_25X80, probe_spi_rdid, 1024, 256, TEST_OK_PREW, - probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read + spi_chip_erase_c7, spi_chip_write, spi_chip_read }, - {"Winbond", "W29C011", WINBOND_ID, W_29C011, + {"Winbond", "W29C011", + WINBOND_ID, W_29C011, probe_jedec, 128, 128, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_jedec + erase_chip_jedec, write_jedec }, - {"Winbond", "W29C020C", WINBOND_ID, W_29C020C, + {"Winbond", "W29C020C", + WINBOND_ID, W_29C020C, probe_jedec, 256, 128, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_jedec + erase_chip_jedec, write_jedec }, - {"Winbond", "W29C040P", WINBOND_ID, W_29C040P, + {"Winbond", "W29C040P", + WINBOND_ID, W_29C040P, probe_jedec, 512, 256, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_jedec + erase_chip_jedec, write_jedec }, - {"Winbond", "W29EE011", WINBOND_ID, W_29C011, + {"Winbond", "W29EE011", + WINBOND_ID, W_29C011, probe_w29ee011, 128, 128, TEST_OK_PREW, - probe_w29ee011, erase_chip_jedec, write_jedec + erase_chip_jedec, write_jedec }, - {"Winbond", "W39V040A", WINBOND_ID, W_39V040A, + {"Winbond", "W39V040A", + WINBOND_ID, W_39V040A, probe_jedec, 512, 64*1024, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_39sf020 + erase_chip_jedec, write_39sf020 }, - {"Winbond", "W39V040B", WINBOND_ID, W_39V040B, + {"Winbond", "W39V040B", + WINBOND_ID, W_39V040B, probe_jedec, 512, 64*1024, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_39sf020 + erase_chip_jedec, write_39sf020 }, - {"Winbond", "W39V040C", WINBOND_ID, 0x50, + {"Winbond", "W39V040C", + WINBOND_ID, 0x50, probe_w39v040c, 512, 64*1024, TEST_OK_PREW, - probe_w39v040c, erase_w39v040c, write_w39v040c + erase_w39v040c, write_w39v040c }, - {"Winbond", "W39V040FA", WINBOND_ID, W_39V040FA, + {"Winbond", "W39V040FA", + WINBOND_ID, W_39V040FA, probe_jedec, 512, 64*1024, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_39sf020 + erase_chip_jedec, write_39sf020 }, - {"Winbond", "W39V080A", WINBOND_ID, W_39V080A, + {"Winbond", "W39V080A", + WINBOND_ID, W_39V080A, probe_jedec, 1024, 64*1024, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_39sf020 + erase_chip_jedec, write_39sf020 }, - {"Winbond", "W49F002U", WINBOND_ID, W_49F002U, + {"Winbond", "W49F002U", + WINBOND_ID, W_49F002U, probe_jedec, 256, 128, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_49f002 + erase_chip_jedec, write_49f002 }, - {"Winbond", "W49V002A", WINBOND_ID, W_49V002A, + {"Winbond", "W49V002A", + WINBOND_ID, W_49V002A, probe_jedec, 256, 128, TEST_OK_PREW, - probe_jedec, erase_chip_jedec, write_49f002 + erase_chip_jedec, write_49f002 }, - {"Winbond", "W49V002FA", WINBOND_ID, W_49V002FA, + {"Winbond", "W49V002FA", + WINBOND_ID, W_49V002FA, probe_jedec, 256, 128, TEST_UNTESTED, - probe_jedec, erase_chip_jedec, write_49f002 + erase_chip_jedec, write_49f002 }, - {"Winbond", "W39V080FA", WINBOND_ID, W_39V080FA, + {"Winbond", "W39V080FA", + WINBOND_ID, W_39V080FA, probe_winbond_fwhub, 1024, 64*1024, TEST_OK_PREW, - probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub + erase_winbond_fwhub, write_winbond_fwhub }, - {"Winbond", "W39V080FA (dual mode)", WINBOND_ID, W_39V080FA_DM, + {"Winbond", "W39V080FA (dual mode)", + WINBOND_ID, W_39V080FA_DM, probe_winbond_fwhub, 512, 64*1024, TEST_UNTESTED, - probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub + erase_winbond_fwhub, write_winbond_fwhub }, - {"Atmel", "unknown Atmel SPI chip", ATMEL_ID, GENERIC_DEVICE_ID, + {"Atmel", "unknown Atmel SPI chip", + ATMEL_ID, GENERIC_DEVICE_ID, probe_spi_rdid, 0, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL + NULL, NULL }, - {"EON", "unknown EON SPI chip", EON_ID_NOPREFIX, GENERIC_DEVICE_ID, + {"EON", "unknown EON SPI chip", + EON_ID_NOPREFIX, GENERIC_DEVICE_ID, probe_spi_rdid, 0, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL + NULL, NULL }, - {"Macronix", "unknown Macronix SPI chip", MX_ID, GENERIC_DEVICE_ID, + {"Macronix", "unknown Macronix SPI chip", + MX_ID, GENERIC_DEVICE_ID, probe_spi_rdid, 0, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL + NULL, NULL }, - {"PMC", "unknown PMC SPI chip", PMC_ID, GENERIC_DEVICE_ID, + {"PMC", "unknown PMC SPI chip", + PMC_ID, GENERIC_DEVICE_ID, probe_spi_rdid, 0, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL + NULL, NULL }, - {"SST", "unknown SST SPI chip", SST_ID, GENERIC_DEVICE_ID, + {"SST", "unknown SST SPI chip", + SST_ID, GENERIC_DEVICE_ID, probe_spi_rdid, 0, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL + NULL, NULL }, - {"ST", "unknown ST SPI chip", ST_ID, GENERIC_DEVICE_ID, + {"ST", "unknown ST SPI chip", + ST_ID, GENERIC_DEVICE_ID, probe_spi_rdid, 0, 256, TEST_UNTESTED, - probe_spi_rdid, NULL, NULL + NULL, NULL }, {NULL,} -- http://www.hailfinger.org/

4 5

option roms in SeaBIOS and Coreboot
by Rudolf Marek 09 Dec '08

09 Dec '08

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, I obtained some SAS PCIe card. I have some good and bad news ;) 1) it does not work at all, PCI ROM signature wrong. 2) it does work with some help glitch 3) it does not work as expected I solved 1) with a simple hack patch (attached) The PCI ROM BARs should not be relocated. The K8 processor has some PCI hole resource and imho there is a problem that even the PCI hole starts at TOPMEM, it still hits RAM because of video framebuffer for integrated VGA. I fixed this isssue by not touching PCI ROM base, check the patch. 2) It does work! PCI option rom get executed. This particular ROM has "press space to skip" option, and if I do that I get to grub/linux whatever. 3) If I do not press space, the PCI option rom is supposed to init the HW. it just freezes somewhere inside, but keyboard IRQ still delivered. With original BIOS, some other screen is printed with another screen mode, but it freezes too ;))) Some remark to the end. I'm not sure if next_rom pointer should be adjusted before the rom is copied. In my case VGA has someting like 36KB and with 2K align it gets to 0xCA000 for next ROM. I tried with ALIGN of 64KB but it does not help that particular silly option rom :) Maybe the align should be handled also depending on actual rom size. I mean "allow spaces for aligns between roms". Rudolf Here are some debug messages: Attempting to find coreboot table Copying ACPI RSDP from 1bff0000 to 000ff330 init SMBIOS tables Found 1 cpu(s) SMBIOS table addr=0x000ff350 ram_size=0x1bff0000 Scan for VGA option rom Attempting to init PCI bdf 00000100 Copying option rom from fff80000 (ROM) to 000c0000 (RAM) Running option rom at 0000c000:00000003 fail handle_155fXX:47(00000086): a=00005f18 b=000002e4 c=00000000 d=000003c3 si=00000000 di=0000e261 ds=00000000 es=0000f000 ip=00008c26 cs=0000c000 f=00000006 r=00007926 Turning on vga console Starting SeaBIOS ... ... Attempting to map option rom on dev 000000c3 Option rom sizing returned 00000000 00000000 Attempting to init PCI bdf 00000200 Attempting to map option rom on dev 00000200 Option rom sizing returned f1100000 fffc0000 Card 00000200 option rom mapped at f1100000 Copying option rom from f1100000 (ROM) to 000d0000 (RAM) Running option rom at 0000d000:00000003 Changing serial settings was 00000003/00000002 now 00000003/00000000 Attempting to init PCI bdf 00000408 Attempting to map option rom on dev 00000408 Option rom sizing returned 00000000 00000000 Press F12 for boot menu. Some example of PCI/MEMORY resources, from another computer via the k8resdump (check Coreboot util) DRAM map: #0 0x0000000000 - 0x003fffffff Access: R/W IntlvEN:0x0 IntlvSEL:0x0 Dstnode:0 DRAM map: #1 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0 Dstnode:1 DRAM map: #2 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0 Dstnode:2 DRAM map: #3 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0 Dstnode:3 DRAM map: #4 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0 Dstnode:4 DRAM map: #5 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0 Dstnode:5 DRAM map: #6 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0 Dstnode:6 DRAM map: #7 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0 Dstnode:7 MMIO map: #0 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0 MMIO map: #1 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0 MMIO map: #2 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0 MMIO map: #3 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0 MMIO map: #4 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0 MMIO map: #5 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0 MMIO map: #6 0x00000a0000 - 0x00000bffff Access: R/W Dstnode:0 DstLink 0 MMIO map: #7 0x0040000000 - 0x00ff70ffff Access: R/W Dstnode:0 DstLink 0 IO map: #0 0x000000 - 0x000fff Access: / Dstnode:0 DstLink 0 IO map: #1 0x001000 - 0x0fffff Access: R/W VGA Dstnode:0 DstLink 0 IO map: #2 0x000000 - 0x000fff Access: / Dstnode:0 DstLink 0 IO map: #3 0x000000 - 0x000fff Access: / Dstnode:0 DstLink 0 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkkrNaEACgkQ3J9wPJqZRNWa6gCeLV7DszkrcuNR0vGzzZs9GW7H ALQAmgKV18+HnsAGgmRNiKM3enmYT6Xe =PXog -----END PGP SIGNATURE-----

7 17

r3806 - trunk/util/flashrom
by svn＠coreboot.org 09 Dec '08

09 Dec '08

Author: hailfinger Date: 2008-12-09 00:51:45 +0100 (Tue, 09 Dec 2008) New Revision: 3806 Modified: trunk/util/flashrom/flashchips.c Log: Kill obsolete and misplaced comment. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-12-08 18:16:58 UTC (rev 3805) +++ trunk/util/flashrom/flashchips.c 2008-12-08 23:51:45 UTC (rev 3806) @@ -576,7 +576,7 @@ 512, 4096, TEST_OK_PROBE, probe_jedec, erase_chip_jedec, write_39sf020 - }, /* assume similar to 004B, ignoring data sheet */ + }, {"SST", "SST49LF002A/B", SST_ID, SST_49LF002A, 256, 16 * 1024,

1 0

Windows XP and Coreboot + SeaBIOS
by Rudolf Marek 09 Dec '08

09 Dec '08

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, I started to hack to make SeaBIOS boot Windows XP and of course its installer. The patch attached fixes some stuff already noticed by Kevin (FACP align, wrong total size). And it adds some dynamic _CRS calculation in AML code. It uses SSDT table with IO resources. For some reason this does not work, but resource hack allows to boot Windows ACPI hal installer. I won't have much time to continue with this week or so (maybe more...). The idea is to let the PCI CRS resource to be calculated dynamically. The CRS resource for host bridge is needed for Windows. Some ideas are described here: http://www.acpi.info/acpi_faq.htm How is it done? Coreboot amd-acpi.c reads all IO resource registers and put them into SSDT table. The AML code in amdk8_util.asl should construct the IO resource containers which will be returned concatenated with BUF0. As I stated above, it ends with 0xA5 STOP. There is some problem somewhere, but once it is fixed, windows should work ;) Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkk9r0IACgkQ3J9wPJqZRNXzTgCg11Rkkstc67oU/nTQ8etErQ3R hX0AoNlArO4D1FabBBUXFfAM5pVw7V0P =Kd54 -----END PGP SIGNATURE-----

1 0

PNP fixes
by Myles Watson 08 Dec '08

08 Dec '08

This fixes the fintek superIO by adding a placeholder so that array indexing works. Besides that it - Changes the struct definition in include/device/pnp.h so that it is more like v2 for porting ease. - Fixes some bugs I introduced in device/pnp_device.c - Sets up the default values of the superios based on v2 boards. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 4

r1066 - in coreboot-v3: device include/device superio/fintek/f71805f superio/ite/it8712f superio/ite/it8716f superio/winbond/w83627hf superio/winbond/w83627thg
by svn＠coreboot.org 08 Dec '08

08 Dec '08

Author: myles Date: 2008-12-08 21:40:02 +0100 (Mon, 08 Dec 2008) New Revision: 1066 Modified: coreboot-v3/device/pnp_device.c coreboot-v3/include/device/pnp.h coreboot-v3/superio/fintek/f71805f/superio.c coreboot-v3/superio/ite/it8712f/superio.c coreboot-v3/superio/ite/it8716f/superio.c coreboot-v3/superio/winbond/w83627hf/superio.c coreboot-v3/superio/winbond/w83627thg/dts coreboot-v3/superio/winbond/w83627thg/superio.c Log: This patch makes all the SuperIOs build again, and reverts some breakage that I introduced earlier. It adds a placeholder in the fintek SuperIO so the array indexing works. It moves the enable to make the struct more compatible with v2. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/device/pnp_device.c =================================================================== --- coreboot-v3/device/pnp_device.c 2008-12-06 03:59:24 UTC (rev 1065) +++ coreboot-v3/device/pnp_device.c 2008-12-08 20:40:02 UTC (rev 1066) @@ -57,7 +57,7 @@ int pnp_read_enable(struct device *dev) { - return !!pnp_read_config(dev, 0x30); + return (pnp_read_config(dev, 0x30) ? 0x1 : 0x0); } void pnp_set_iobase(struct device *dev, unsigned int index, unsigned int iobase) @@ -110,7 +110,7 @@ } resource->flags |= IORESOURCE_STORED; - report_resource_stored(dev, resource, ""); + report_resource_stored(dev, resource, __func__); } void pnp_set_resources(struct device *dev) @@ -192,7 +192,7 @@ resource->limit = info->mask | (step - 1); resource->size = 1 << gran; resource->base = info->val; - resource->flags |= IORESOURCE_FIXED || IORESOURCE_ASSIGNED; + resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED; } static void get_resources(struct device *dev, struct pnp_info *info) @@ -215,29 +215,29 @@ resource = new_resource(dev, PNP_IDX_IRQ0); resource->size = 1; resource->flags |= IORESOURCE_IRQ; - resource->base = info->irq0.val; - resource->flags |= IORESOURCE_FIXED || IORESOURCE_ASSIGNED; + resource->base = info->irq0; + resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED; } if (info->flags & PNP_IRQ1) { resource = new_resource(dev, PNP_IDX_IRQ1); resource->size = 1; resource->flags |= IORESOURCE_IRQ; - resource->base = info->irq1.val; - resource->flags |= IORESOURCE_FIXED || IORESOURCE_ASSIGNED; + resource->base = info->irq1; + resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED; } if (info->flags & PNP_DRQ0) { resource = new_resource(dev, PNP_IDX_DRQ0); resource->size = 1; resource->flags |= IORESOURCE_DRQ; - resource->base = info->drq0.val; - resource->flags |= IORESOURCE_FIXED || IORESOURCE_ASSIGNED; + resource->base = info->drq0; + resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED; } if (info->flags & PNP_DRQ1) { resource = new_resource(dev, PNP_IDX_DRQ1); resource->size = 1; resource->flags |= IORESOURCE_DRQ; - resource->base = info->drq0.val; - resource->flags |= IORESOURCE_FIXED || IORESOURCE_ASSIGNED; + resource->base = info->drq0; + resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED; } } @@ -254,6 +254,7 @@ /* Setup the ops and resources on the newly allocated devices. */ for (i = 0; i < functions; i++) { + path.pnp.device = info[i].function; dev = find_dev_path(&base_dev->link[0], &path); @@ -263,7 +264,7 @@ __func__, dev->dtsname, dev_path(dev)); continue; } - + dev = alloc_dev(&base_dev->link[0], &path, &id); if (!dev) @@ -310,12 +311,12 @@ { int i, idx; u16 port = dev->path.pnp.port; - + /* Determine Super I/O config port. */ idx = (port == 0x3f0) ? 0 : ((port == 0x3bd) ? 1 : 2); for (i = 0; i < 4; i++) outb(init[idx][i], ISA_PNP_ADDR); - + /* Sequentially write the 32 MB PnP init values. */ for (i = 0; i < 32; i++) outb(initkey_mbpnp[i], port); Modified: coreboot-v3/include/device/pnp.h =================================================================== --- coreboot-v3/include/device/pnp.h 2008-12-06 03:59:24 UTC (rev 1065) +++ coreboot-v3/include/device/pnp.h 2008-12-08 20:40:02 UTC (rev 1066) @@ -59,7 +59,6 @@ struct pnp_info { struct device_operations *ops; unsigned function; - unsigned enable; unsigned flags; #define PNP_IO0 0x01 #define PNP_IO1 0x02 @@ -69,11 +68,15 @@ #define PNP_IRQ1 0x20 #define PNP_DRQ0 0x40 #define PNP_DRQ1 0x80 - struct io_info io0, io1, io2, io3, irq0, irq1, drq0, drq1; + struct io_info io0, io1, io2, io3; + unsigned irq0, irq1, drq0, drq1; + unsigned enable; }; + struct resource *pnp_get_resource(struct device * dev, unsigned index); + void pnp_enable_devices(struct device *dev, struct device_operations *ops, - unsigned functions, struct pnp_info *info); + unsigned functions, struct pnp_info *info); #define PNP_IDX_IO0 0x60 #define PNP_IDX_IO1 0x62 Modified: coreboot-v3/superio/fintek/f71805f/superio.c =================================================================== --- coreboot-v3/superio/fintek/f71805f/superio.c 2008-12-06 03:59:24 UTC (rev 1065) +++ coreboot-v3/superio/fintek/f71805f/superio.c 2008-12-08 20:40:02 UTC (rev 1066) @@ -93,6 +93,8 @@ }; static struct pnp_info pnp_dev_info[] = { + /* Ops, function #, All resources needed by dev, io_info */ + { NULL, F71805F_FDC, }, /* Place holder. */ { &f71805f_ops, F71805F_COM1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &f71805f_ops, F71805F_COM2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, /* TODO: Everything else */ @@ -106,12 +108,12 @@ /* COM1 */ pnp_dev_info[F71805F_COM1].enable = conf->com1enable; pnp_dev_info[F71805F_COM1].io0.val = conf->com1io; - pnp_dev_info[F71805F_COM1].irq0.val = conf->com1irq; + pnp_dev_info[F71805F_COM1].irq0 = conf->com1irq; /* COM2 */ pnp_dev_info[F71805F_COM2].enable = conf->com2enable; pnp_dev_info[F71805F_COM2].io0.val = conf->com2io; - pnp_dev_info[F71805F_COM2].irq0.val = conf->com2irq; + pnp_dev_info[F71805F_COM2].irq0 = conf->com2irq; /* Initialize SuperIO for PNP children. */ if (!dev->links) { Modified: coreboot-v3/superio/ite/it8712f/superio.c =================================================================== --- coreboot-v3/superio/ite/it8712f/superio.c 2008-12-06 03:59:24 UTC (rev 1065) +++ coreboot-v3/superio/ite/it8712f/superio.c 2008-12-08 20:40:02 UTC (rev 1066) @@ -95,18 +95,18 @@ }; static struct pnp_info pnp_dev_info[] = { - /* Enable, All resources need by dev, io_info_structs */ - {&it8712f_ops, IT8712F_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xff8, 0},}, - {&it8712f_ops, IT8712F_SP1, 0, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, - {&it8712f_ops, IT8712F_SP2, 0, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, - {&it8712f_ops, IT8712F_PP, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xffc, 0},}, - {&it8712f_ops, IT8712F_EC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xff8, 0}, {0xff8, 4},}, - {&it8712f_ops, IT8712F_KBCK, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfff, 0}, {0xfff, 4},}, - {&it8712f_ops, IT8712F_KBCM, 0, PNP_IRQ0,}, - {&it8712f_ops, IT8712F_GPIO, 0, }, - {&it8712f_ops, IT8712F_MIDI, 0, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, - {&it8712f_ops, IT8712F_GAME, 0, PNP_IO0, {0xfff, 0},}, - {&it8712f_ops, IT8712F_IR, 0, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, + /* All resources needed by dev, io_info_structs */ + {&it8712f_ops, IT8712F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xff8, 0},}, + {&it8712f_ops, IT8712F_SP1, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, + {&it8712f_ops, IT8712F_SP2, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, + {&it8712f_ops, IT8712F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xffc, 0},}, + {&it8712f_ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xff8, 0}, {0xff8, 4},}, + {&it8712f_ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfff, 0}, {0xfff, 4},}, + {&it8712f_ops, IT8712F_KBCM, PNP_IRQ0,}, + {&it8712f_ops, IT8712F_GPIO, }, + {&it8712f_ops, IT8712F_MIDI, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, + {&it8712f_ops, IT8712F_GAME, PNP_IO0, {0xfff, 0},}, + {&it8712f_ops, IT8712F_IR, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, }; static void it8712f_setup_scan_bus(struct device *dev) @@ -116,38 +116,38 @@ /* Floppy */ pnp_dev_info[IT8712F_FDC].enable = conf->floppyenable; pnp_dev_info[IT8712F_FDC].io0.val = conf->floppyio; - pnp_dev_info[IT8712F_FDC].irq0.val = conf->floppyirq; - pnp_dev_info[IT8712F_FDC].drq0.val = conf->floppydrq; + pnp_dev_info[IT8712F_FDC].irq0 = conf->floppyirq; + pnp_dev_info[IT8712F_FDC].drq0 = conf->floppydrq; /* COM1 */ pnp_dev_info[IT8712F_SP1].enable = conf->com1enable; pnp_dev_info[IT8712F_SP1].io0.val = conf->com1io; - pnp_dev_info[IT8712F_SP1].irq0.val = conf->com1irq; + pnp_dev_info[IT8712F_SP1].irq0 = conf->com1irq; /* COM2 */ pnp_dev_info[IT8712F_SP2].enable = conf->com2enable; pnp_dev_info[IT8712F_SP2].io0.val = conf->com2io; - pnp_dev_info[IT8712F_SP2].irq0.val = conf->com2irq; + pnp_dev_info[IT8712F_SP2].irq0 = conf->com2irq; /* Parallel port */ pnp_dev_info[IT8712F_PP].enable = conf->ppenable; pnp_dev_info[IT8712F_PP].io0.val = conf->ppio; - pnp_dev_info[IT8712F_PP].irq0.val = conf->ppirq; + pnp_dev_info[IT8712F_PP].irq0 = conf->ppirq; /* Environment controller */ pnp_dev_info[IT8712F_EC].enable = conf->ecenable; pnp_dev_info[IT8712F_EC].io0.val = conf->ecio; - pnp_dev_info[IT8712F_EC].irq0.val = conf->ecirq; + pnp_dev_info[IT8712F_EC].irq0 = conf->ecirq; /* Keyboard */ pnp_dev_info[IT8712F_KBCK].enable = conf->kbenable; pnp_dev_info[IT8712F_KBCK].io0.val = conf->kbio; pnp_dev_info[IT8712F_KBCK].io1.val = conf->kbio2; - pnp_dev_info[IT8712F_KBCK].irq0.val = conf->kbirq; + pnp_dev_info[IT8712F_KBCK].irq0 = conf->kbirq; /* PS/2 mouse */ pnp_dev_info[IT8712F_KBCM].enable = conf->mouseenable; - pnp_dev_info[IT8712F_KBCM].irq0.val = conf->mouseirq; + pnp_dev_info[IT8712F_KBCM].irq0 = conf->mouseirq; /* GPIO */ pnp_dev_info[IT8712F_GPIO].enable = conf->gpioenable; @@ -155,7 +155,7 @@ /* MIDI port */ pnp_dev_info[IT8712F_MIDI].enable = conf->midienable; pnp_dev_info[IT8712F_MIDI].io0.val = conf->midiio; - pnp_dev_info[IT8712F_MIDI].irq0.val = conf->midiirq; + pnp_dev_info[IT8712F_MIDI].irq0 = conf->midiirq; /* Game port */ pnp_dev_info[IT8712F_GAME].enable = conf->gameenable; @@ -164,7 +164,7 @@ /* Consumer IR */ pnp_dev_info[IT8712F_IR].enable = conf->cirenable; pnp_dev_info[IT8712F_IR].io0.val = conf->cirio; - pnp_dev_info[IT8712F_IR].irq0.val = conf->cirirq; + pnp_dev_info[IT8712F_IR].irq0 = conf->cirirq; /* Initialize SuperIO for PNP children. */ if (!dev->links) { Modified: coreboot-v3/superio/ite/it8716f/superio.c =================================================================== --- coreboot-v3/superio/ite/it8716f/superio.c 2008-12-06 03:59:24 UTC (rev 1065) +++ coreboot-v3/superio/ite/it8716f/superio.c 2008-12-08 20:40:02 UTC (rev 1066) @@ -133,20 +133,20 @@ }; static struct pnp_info pnp_dev_info[] = { - /* Enable, All resources need by dev, io_info_structs */ - {&it8716f_ops, IT8716F_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, - {&it8716f_ops, IT8716F_SP1, 0, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, - {&it8716f_ops, IT8716F_SP2, 0, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, - {&it8716f_ops, IT8716F_PP, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, - {&it8716f_ops, IT8716F_EC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, + /* All resources needed by dev, io_info_structs */ + {&it8716f_ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, + {&it8716f_ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, + {&it8716f_ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, + {&it8716f_ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, + {&it8716f_ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, {0x7f8, 0x4},}, - {&it8716f_ops, IT8716F_KBCK, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0}, + {&it8716f_ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0}, {0x7ff, 0x4},}, - {&it8716f_ops, IT8716F_KBCM, 0, PNP_IRQ0,}, - {&it8716f_ops, IT8716F_GPIO, 0, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},}, - {&it8716f_ops, IT8716F_MIDI, 0, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},}, - {&it8716f_ops, IT8716F_GAME, 0, PNP_IO0, {0x7ff, 0},}, - {&it8716f_ops, IT8716F_IR, 0,}, + {&it8716f_ops, IT8716F_KBCM, PNP_IRQ0,}, + {&it8716f_ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},}, + {&it8716f_ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},}, + {&it8716f_ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},}, + {&it8716f_ops, IT8716F_IR, }, }; static void it8716f_setup_scan_bus(struct device *dev) @@ -156,38 +156,38 @@ /* Floppy */ pnp_dev_info[IT8716F_FDC].enable = conf->floppyenable; pnp_dev_info[IT8716F_FDC].io0.val = conf->floppyio; - pnp_dev_info[IT8716F_FDC].irq0.val = conf->floppyirq; - pnp_dev_info[IT8716F_FDC].drq0.val = conf->floppydrq; + pnp_dev_info[IT8716F_FDC].irq0 = conf->floppyirq; + pnp_dev_info[IT8716F_FDC].drq0 = conf->floppydrq; /* COM1 */ pnp_dev_info[IT8716F_SP1].enable = conf->com1enable; pnp_dev_info[IT8716F_SP1].io0.val = conf->com1io; - pnp_dev_info[IT8716F_SP1].irq0.val = conf->com1irq; + pnp_dev_info[IT8716F_SP1].irq0 = conf->com1irq; /* COM2 */ pnp_dev_info[IT8716F_SP2].enable = conf->com2enable; pnp_dev_info[IT8716F_SP2].io0.val = conf->com2io; - pnp_dev_info[IT8716F_SP2].irq0.val = conf->com2irq; + pnp_dev_info[IT8716F_SP2].irq0 = conf->com2irq; /* Parallel port */ pnp_dev_info[IT8716F_PP].enable = conf->ppenable; pnp_dev_info[IT8716F_PP].io0.val = conf->ppio; - pnp_dev_info[IT8716F_PP].irq0.val = conf->ppirq; + pnp_dev_info[IT8716F_PP].irq0 = conf->ppirq; /* Environment controller */ pnp_dev_info[IT8716F_EC].enable = conf->ecenable; pnp_dev_info[IT8716F_EC].io0.val = conf->ecio; - pnp_dev_info[IT8716F_EC].irq0.val = conf->ecirq; + pnp_dev_info[IT8716F_EC].irq0 = conf->ecirq; /* Keyboard */ pnp_dev_info[IT8716F_KBCK].enable = conf->kbenable; pnp_dev_info[IT8716F_KBCK].io0.val = conf->kbio; pnp_dev_info[IT8716F_KBCK].io1.val = conf->kbio2; - pnp_dev_info[IT8716F_KBCK].irq0.val = conf->kbirq; + pnp_dev_info[IT8716F_KBCK].irq0 = conf->kbirq; /* PS/2 mouse */ pnp_dev_info[IT8716F_KBCM].enable = conf->mouseenable; - pnp_dev_info[IT8716F_KBCM].irq0.val = conf->mouseirq; + pnp_dev_info[IT8716F_KBCM].irq0 = conf->mouseirq; /* GPIO */ pnp_dev_info[IT8716F_GPIO].enable = conf->gpioenable; @@ -195,7 +195,7 @@ /* MIDI port */ pnp_dev_info[IT8716F_MIDI].enable = conf->midienable; pnp_dev_info[IT8716F_MIDI].io0.val = conf->midiio; - pnp_dev_info[IT8716F_MIDI].irq0.val = conf->midiirq; + pnp_dev_info[IT8716F_MIDI].irq0 = conf->midiirq; /* Game port */ pnp_dev_info[IT8716F_GAME].enable = conf->gameenable; @@ -204,7 +204,7 @@ /* Consumer IR */ pnp_dev_info[IT8716F_IR].enable = conf->cirenable; pnp_dev_info[IT8716F_IR].io0.val = conf->cirio; - pnp_dev_info[IT8716F_IR].irq0.val = conf->cirirq; + pnp_dev_info[IT8716F_IR].irq0 = conf->cirirq; /* Initialize SuperIO for PNP children. */ if (!dev->links) { Modified: coreboot-v3/superio/winbond/w83627hf/superio.c =================================================================== --- coreboot-v3/superio/winbond/w83627hf/superio.c 2008-12-06 03:59:24 UTC (rev 1065) +++ coreboot-v3/superio/winbond/w83627hf/superio.c 2008-12-08 20:40:02 UTC (rev 1066) @@ -195,22 +195,21 @@ }; static struct pnp_info pnp_dev_info[] = { - /* Enable, All resources need by dev, io_info_structs */ - { &w83627hf_ops, W83627HF_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &w83627hf_ops, W83627HF_PP, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &w83627hf_ops, W83627HF_SP1, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &w83627hf_ops, W83627HF_SP2, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { 0,}, - { &w83627hf_ops, W83627HF_KBC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &w83627hf_ops, W83627HF_CIR, 0,PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, 0,PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, }, - { &w83627hf_ops, W83627HF_GPIO2, 0 }, - { &w83627hf_ops, W83627HF_GPIO3, 0 }, - { &w83627hf_ops, W83627HF_ACPI, 0 }, - { &w83627hf_ops, W83627HF_HWM, 0, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, + /* Ops, function #, All resources needed by dev, io_info_structs */ + { &w83627hf_ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &w83627hf_ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &w83627hf_ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &w83627hf_ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { 0, }, /* No function 4. */ + { &w83627hf_ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &w83627hf_ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, }, + { &w83627hf_ops, W83627HF_GPIO2, }, + { &w83627hf_ops, W83627HF_GPIO3, }, + { &w83627hf_ops, W83627HF_ACPI, }, + { &w83627hf_ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, }; - static void phase3_chip_setup_dev(struct device *dev) { /* Get dts values and populate pnp_dev_info. */ @@ -219,30 +218,30 @@ /* Floppy */ pnp_dev_info[W83627HF_FDC].enable = conf->floppyenable; pnp_dev_info[W83627HF_FDC].io0.val = conf->floppyio; - pnp_dev_info[W83627HF_FDC].irq0.val = conf->floppyirq; - pnp_dev_info[W83627HF_FDC].drq0.val = conf->floppydrq; + pnp_dev_info[W83627HF_FDC].irq0 = conf->floppyirq; + pnp_dev_info[W83627HF_FDC].drq0 = conf->floppydrq; /* Parallel port */ pnp_dev_info[W83627HF_PP].enable = conf->ppenable; pnp_dev_info[W83627HF_PP].io0.val = conf->ppio; - pnp_dev_info[W83627HF_PP].irq0.val = conf->ppirq; + pnp_dev_info[W83627HF_PP].irq0 = conf->ppirq; /* COM1 */ pnp_dev_info[W83627HF_SP1].enable = conf->com1enable; pnp_dev_info[W83627HF_SP1].io0.val = conf->com1io; - pnp_dev_info[W83627HF_SP1].irq0.val = conf->com1irq; + pnp_dev_info[W83627HF_SP1].irq0 = conf->com1irq; /* COM2 */ pnp_dev_info[W83627HF_SP2].enable = conf->com2enable; pnp_dev_info[W83627HF_SP2].io0.val = conf->com2io; - pnp_dev_info[W83627HF_SP2].irq0.val = conf->com2irq; + pnp_dev_info[W83627HF_SP2].irq0 = conf->com2irq; /* Keyboard */ pnp_dev_info[W83627HF_KBC].enable = conf->kbenable; pnp_dev_info[W83627HF_KBC].io0.val = conf->kbio; pnp_dev_info[W83627HF_KBC].io1.val = conf->kbio2; - pnp_dev_info[W83627HF_KBC].irq0.val = conf->kbirq; - pnp_dev_info[W83627HF_KBC].irq1.val = conf->kbirq2; + pnp_dev_info[W83627HF_KBC].irq0 = conf->kbirq; + pnp_dev_info[W83627HF_KBC].irq1 = conf->kbirq2; /* Consumer IR */ pnp_dev_info[W83627HF_CIR].enable = conf->cirenable; @@ -251,7 +250,7 @@ pnp_dev_info[W83627HF_GAME_MIDI_GPIO1].enable = conf->gameenable; pnp_dev_info[W83627HF_GAME_MIDI_GPIO1].io0.val = conf->gameio; pnp_dev_info[W83627HF_GAME_MIDI_GPIO1].io1.val = conf->gameio2; - pnp_dev_info[W83627HF_GAME_MIDI_GPIO1].irq0.val = conf->gameirq; + pnp_dev_info[W83627HF_GAME_MIDI_GPIO1].irq0 = conf->gameirq; /* GPIO2 */ pnp_dev_info[W83627HF_GPIO2].enable = conf->gpio2enable; @@ -265,7 +264,7 @@ /* Hardware Monitor */ pnp_dev_info[W83627HF_HWM].enable = conf->hwmenable; pnp_dev_info[W83627HF_HWM].io0.val = conf->hwmio; - pnp_dev_info[W83627HF_HWM].irq0.val = conf->hwmirq; + pnp_dev_info[W83627HF_HWM].irq0 = conf->hwmirq; /* Initialize SuperIO for PNP children. */ if (!dev->links) { @@ -275,7 +274,6 @@ dev->link[0].link = 0; } - /* Call init with updated tables to create children. */ + /* Call init with updated tables to create and enable children. */ pnp_enable_devices(dev, &w83627hf_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } - Modified: coreboot-v3/superio/winbond/w83627thg/dts =================================================================== --- coreboot-v3/superio/winbond/w83627thg/dts 2008-12-06 03:59:24 UTC (rev 1065) +++ coreboot-v3/superio/winbond/w83627thg/dts 2008-12-08 20:40:02 UTC (rev 1066) @@ -24,33 +24,28 @@ /* To override any of these, put the over-ride in mainboard dts. */ /* Floppy */ - floppydev = "0"; floppyenable = "0"; floppyio = "0x3f0"; floppyirq = "6"; floppydrq = "2"; /* Parallel port */ - ppdev = "1"; ppenable = "0"; ppio = "0x378"; ppirq = "7"; ppdrq = "4"; /* COM1 */ - com1dev = "2"; com1enable = "0"; com1io = "0x3f8"; com1irq = "4"; /* COM2 */ - com2dev = "3"; com2enable = "0"; com2io = "0x2f8"; com2irq = "3"; /* PS/2 keyboard + PS/2 mouse */ - kbdev = "5"; kbenable = "0"; kbio = "0x60"; kbio2 = "0x64"; @@ -58,26 +53,21 @@ kbirq2 = "12"; /* Game port, MIDI port, GPIO1, GPIO5 */ - gamedev = "7"; gameenable = "0"; gameio = "0x201"; gameio2 = "0x330"; gameirq = "9"; /* GPIO2 */ - gpio2dev = "8"; gpio2enable = "0"; /* GPIO3, GPIO4 */ - gpio34dev = "9"; gpio34enable = "0"; /* ACPI */ - acpidev = "10"; acpienable = "0"; /* Hardware Monitor */ - hwmdev = "11"; hwmenable = "0"; hwmio = "0x290"; hwmirq = "5"; Modified: coreboot-v3/superio/winbond/w83627thg/superio.c =================================================================== --- coreboot-v3/superio/winbond/w83627thg/superio.c 2008-12-06 03:59:24 UTC (rev 1065) +++ coreboot-v3/superio/winbond/w83627thg/superio.c 2008-12-08 20:40:02 UTC (rev 1066) @@ -1,9 +1,9 @@ /* * This file is part of the coreboot project. * - * Copyright 2000 AG Electronics Ltd. + * Copyright 2000 AG Electronics Ltd. * Copyright 2003-2004 Linux Networx - * Copyright 2004 Tyan + * Copyright 2004 Tyan * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -25,10 +25,8 @@ #include <device/pnp.h> #include <console.h> #include <string.h> -//#include <bitops.h> #include <uart8250.h> #include <keyboard.h> -// #include <pc80/mc146818rtc.h> #include <statictree.h> #include "w83627thg.h" @@ -93,17 +91,19 @@ /* TODO: this device is not at all filled out. Just copied from v2. */ static struct pnp_info pnp_dev_info[] = { - { &w83627thg_ops, W83627THG_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &w83627thg_ops, W83627THG_PP, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &w83627thg_ops, W83627THG_SP1, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &w83627thg_ops, W83627THG_SP2, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - // No 4 { 0,}, - { &w83627thg_ops, W83627THG_KBC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &w83627thg_ops, W83627THG_GAME_MIDI_GPIO1, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} }, - { &w83627thg_ops, W83627THG_GPIO2,}, - { &w83627thg_ops, W83627THG_GPIO3,}, - { &w83627thg_ops, W83627THG_ACPI, 0, PNP_IRQ0, }, - { &w83627thg_ops, W83627THG_HWM, 0, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } }, + /* Ops, function #, All resources needed by dev, io_info_structs */ + { &w83627thg_ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &w83627thg_ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &w83627thg_ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &w83627thg_ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { 0, }, /* No function 4. */ + { &w83627thg_ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { 0, }, /* No function 6. */ + { &w83627thg_ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, }, + { &w83627thg_ops, W83627THG_GPIO2, }, + { &w83627thg_ops, W83627THG_GPIO3, }, + { &w83627thg_ops, W83627THG_ACPI, }, + { &w83627thg_ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, }; static void phase3_chip_setup_dev(struct device *dev) @@ -111,33 +111,45 @@ /* Get dts values and populate pnp_dev_info. */ const struct superio_winbond_w83627thg_dts_config * const conf = dev->device_configuration; -#if 0 -These are not set up at all v2. Ignore for now. */ /* Floppy */ pnp_dev_info[W83627THG_FDC].enable = conf->floppyenable; pnp_dev_info[W83627THG_FDC].io0.val = conf->floppyio; - pnp_dev_info[W83627THG_FDC].irq0.val = conf->floppyirq; - pnp_dev_info[W83627THG_FDC].drq0.val = conf->floppydrq; + pnp_dev_info[W83627THG_FDC].irq0 = conf->floppyirq; + pnp_dev_info[W83627THG_FDC].drq0 = conf->floppydrq; /* Parallel port */ pnp_dev_info[W83627THG_PP].enable = conf->ppenable; pnp_dev_info[W83627THG_PP].io0.val = conf->ppio; - pnp_dev_info[W83627THG_PP].irq0.val = conf->ppirq; + pnp_dev_info[W83627THG_PP].irq0 = conf->ppirq; - /* Consumer IR */ - pnp_dev_info[W83627THG_CIR].enable = conf->cirenable; + /* COM1 */ + pnp_dev_info[W83627THG_SP1].enable = conf->com1enable; + pnp_dev_info[W83627THG_SP1].io0.val = conf->com1io; + pnp_dev_info[W83627THG_SP1].irq0 = conf->com1irq; + /* COM2 */ + pnp_dev_info[W83627THG_SP2].enable = conf->com2enable; + pnp_dev_info[W83627THG_SP2].io0.val = conf->com2io; + pnp_dev_info[W83627THG_SP2].irq0 = conf->com2irq; + + /* Keyboard */ + pnp_dev_info[W83627THG_KBC].enable = conf->kbenable; + pnp_dev_info[W83627THG_KBC].io0.val = conf->kbio; + pnp_dev_info[W83627THG_KBC].io1.val = conf->kbio2; + pnp_dev_info[W83627THG_KBC].irq0 = conf->kbirq; + pnp_dev_info[W83627THG_KBC].irq1 = conf->kbirq2; + /* Game port */ pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].enable = conf->gameenable; pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].io0.val = conf->gameio; pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].io1.val = conf->gameio2; - pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].irq0.val = conf->gameirq; + pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].irq0 = conf->gameirq; /* GPIO2 */ pnp_dev_info[W83627THG_GPIO2].enable = conf->gpio2enable; - /* GPIO3 */ - pnp_dev_info[W83627THG_GPIO3].enable = conf->gpio3enable; + /* GPIO3, GPIO4 */ + pnp_dev_info[W83627THG_GPIO3].enable = conf->gpio34enable; /* ACPI */ pnp_dev_info[W83627THG_ACPI].enable = conf->acpienable; @@ -145,27 +157,8 @@ /* Hardware Monitor */ pnp_dev_info[W83627THG_HWM].enable = conf->hwmenable; pnp_dev_info[W83627THG_HWM].io0.val = conf->hwmio; - pnp_dev_info[W83627THG_HWM].irq0.val = conf->hwmirq; + pnp_dev_info[W83627THG_HWM].irq0 = conf->hwmirq; -#endif - - /* COM1 */ - pnp_dev_info[W83627THG_SP1].enable = conf->com1enable; - pnp_dev_info[W83627THG_SP1].io0.val = conf->com1io; - pnp_dev_info[W83627THG_SP1].irq0.val = conf->com1irq; - - /* COM2 */ - pnp_dev_info[W83627THG_SP2].enable = conf->com2enable; - pnp_dev_info[W83627THG_SP2].io0.val = conf->com2io; - pnp_dev_info[W83627THG_SP2].irq0.val = conf->com2irq; - - /* Keyboard */ - pnp_dev_info[W83627THG_KBC].enable = conf->kbenable; - pnp_dev_info[W83627THG_KBC].io0.val = conf->kbio; - pnp_dev_info[W83627THG_KBC].io1.val = conf->kbio2; - pnp_dev_info[W83627THG_KBC].irq0.val = conf->kbirq; - pnp_dev_info[W83627THG_KBC].irq1.val = conf->kbirq2; - /* Initialize SuperIO for PNP children. */ if (!dev->links) { dev->links = 1; @@ -174,6 +167,6 @@ dev->link[0].link = 0; } - /* Call init with updated tables to create children. */ + /* Call init with updated tables to create and enable children. */ pnp_enable_devices(dev, &w83627thg_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); }

1 0

r3805 - trunk/util/flashrom
by svn＠coreboot.org 08 Dec '08

08 Dec '08

Author: stepan Date: 2008-12-08 19:16:58 +0100 (Mon, 08 Dec 2008) New Revision: 3805 Modified: trunk/util/flashrom/chipset_enable.c trunk/util/flashrom/flash.h trunk/util/flashrom/ichspi.c Log: Generates OPCODES struct from the ICH7/ICH9/VIA chipset if its SPI configuration is locked down. Signed-off-by: FENG yu ning <fengyuning1984(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2008-12-08 18:15:10 UTC (rev 3804) +++ trunk/util/flashrom/chipset_enable.c 2008-12-08 18:16:58 UTC (rev 3805) @@ -47,6 +47,8 @@ flashbus_t flashbus = BUS_TYPE_LPC; void *spibar = NULL; +extern int ichspi_lock; + static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) { uint8_t tmp; @@ -335,6 +337,7 @@ printf_debug("\n"); if ((*(uint16_t *) spibar) & (1 << 15)) { printf("WARNING: SPI Configuration Lockdown activated.\n"); + ichspi_lock = 1; } break; case BUS_TYPE_ICH9_SPI: Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-12-08 18:15:10 UTC (rev 3804) +++ trunk/util/flashrom/flash.h 2008-12-08 18:16:58 UTC (rev 3805) @@ -51,6 +51,12 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) +/* for pairing opcodes with their required preop */ +struct preop_opcode_pair { + uint8_t preop; + uint8_t opcode; +}; + struct flashchip { const char *vendor; const char *name; @@ -76,6 +82,8 @@ int (*write) (struct flashchip *flash, uint8_t *buf); int (*read) (struct flashchip *flash, uint8_t *buf); + struct preop_opcode_pair *preop_opcode_pairs; + /* Some flash devices have an additional register space. */ volatile uint8_t *virtual_memory; volatile uint8_t *virtual_registers; Modified: trunk/util/flashrom/ichspi.c =================================================================== --- trunk/util/flashrom/ichspi.c 2008-12-08 18:15:10 UTC (rev 3804) +++ trunk/util/flashrom/ichspi.c 2008-12-08 18:16:58 UTC (rev 3805) @@ -101,6 +101,9 @@ #define ICH7_REG_OPTYPE 0x56 /* 16 Bits */ #define ICH7_REG_OPMENU 0x58 /* 64 Bits */ +/* ICH SPI configuration lock-down. May be set during chipset enabling. */ +int ichspi_lock = 0; + typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode uint8_t spi_type; //This commands spi type @@ -147,7 +150,11 @@ #define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)spibar+X)=Y) /* Common SPI functions */ +static inline int find_opcode(OPCODES *op, uint8_t opcode); +static inline int find_preop(OPCODES *op, uint8_t preop); +static int generate_opcodes(struct flashchip * flash, OPCODES * op); static int program_opcodes(OPCODES * op); +int ich_check_opcodes(struct flashchip * flash); static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, @@ -171,6 +178,98 @@ } }; +OPCODES O_EXISTING = {}; + +static inline int find_opcode(OPCODES *op, uint8_t opcode) +{ + int a; + + for (a = 0; a < 8; a++) { + if (op->opcode[a].opcode == opcode) + return a; + } + + return -1; +} + +static inline int find_preop(OPCODES *op, uint8_t preop) +{ + int a; + + for (a = 0; a < 2; a++) { + if (op->preop[a] == preop) + return a; + } + + return -1; +} + +static int generate_opcodes(struct flashchip * flash, OPCODES * op) +{ + int a, b, i; + uint16_t preop, optype; + uint32_t opmenu[2]; + struct preop_opcode_pair *pair; + + if (op == NULL) { + printf_debug("\n%s: null OPCODES pointer!\n", __FUNCTION__); + return -1; + } + + switch (flashbus) { + case BUS_TYPE_ICH7_SPI: + case BUS_TYPE_VIA_SPI: + preop = REGREAD16(ICH7_REG_PREOP); + optype = REGREAD16(ICH7_REG_OPTYPE); + opmenu[0] = REGREAD32(ICH7_REG_OPMENU); + opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4); + break; + case BUS_TYPE_ICH9_SPI: + preop = REGREAD16(ICH9_REG_PREOP); + optype = REGREAD16(ICH9_REG_OPTYPE); + opmenu[0] = REGREAD32(ICH9_REG_OPMENU); + opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4); + break; + default: + printf_debug("%s: unsupported chipset\n", __FUNCTION__); + return -1; + } + + op->preop[0] = (uint8_t) preop; + op->preop[1] = (uint8_t) (preop >> 8); + + for (a = 0; a < 8; a++) { + op->opcode[a].spi_type = (uint8_t) (optype & 0x3); + optype >>= 2; + } + + for (a = 0; a < 4; a++) { + op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff); + opmenu[0] >>= 8; + } + + for (a = 4; a < 8; a++) { + op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff); + opmenu[1] >>= 8; + } + + /* atomic (link opcode with required pre-op) */ + for (a = 4; a < 8; a++) + op->opcode[a].atomic = 0; + + pair = flash->preop_opcode_pairs; + if (pair) { + for (i = 0; pair[i].opcode; i++) { + a = find_opcode(op, pair[i].opcode); + b = find_preop(op, pair[i].preop); + if ((a != -1) && (b != -1)) + op->opcode[a].atomic = (uint8_t) ++b; + } + } + + return 0; +} + int program_opcodes(OPCODES * op) { uint8_t a; @@ -224,6 +323,41 @@ return 0; } +/* This function generates OPCODES from or programs OPCODES to the chipset + * according to its SPI configuration lock. + * + * It should be called in the ICH7/ICH9/VIA part of each operation driver(i.e. + * probe, read, erase, write, etc.) before any command is sent. + */ +int ich_check_opcodes(struct flashchip * flash) +{ + int rc = 0; + OPCODES *curopcodes_done; + + if (curopcodes) + return 0; + + if (ichspi_lock) { + printf_debug("Generating OPCODES... "); + curopcodes_done = &O_EXISTING; + rc = generate_opcodes(flash, curopcodes_done); + } else { + printf_debug("Programming OPCODES... "); + curopcodes_done = &O_ST_M25P; + rc = program_opcodes(curopcodes_done); + } + + if (rc) { + curopcodes = NULL; + printf_debug("failed\n"); + return 1; + } else { + curopcodes = curopcodes_done; + printf_debug("done\n"); + return 0; + } +} + static int ich7_run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data, int maxdata) {

1 0

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2003

2002

coreboot December 2008