coreboot December 2008

coreboot@coreboot.org

77 participants
330 discussions

Resource Allocation discussion
by Myles Watson 05 Dec '08

05 Dec '08

The resource patches I submitted work fairly well, but still need a little help. I haven't touched subtractively decoded resources, and that's where the breakage is right now. Questions: - Who should have a resource that moves all other IO resources above 0x400 or 0x1000? - Is one needed if subtractive resources are implemented correctly? - Who is responsible for setting the top of the address range? - From an earlier thread with Carl-Daniel it sounded like there are fixed locations for APICs that need to be avoided. Where should these be avoided? Thanks, Myles

6 27

r255 - in buildrom-devel/packages: coreboot-v2 coreboot-v3 coreinfo filo geodevsa grub2 libpayload nrv2b ofw openbios
by svn＠coreboot.org 05 Dec '08

05 Dec '08

Author: ward Date: 2008-12-05 20:45:09 +0100 (Fri, 05 Dec 2008) New Revision: 255 Modified: buildrom-devel/packages/coreboot-v2/coreboot.inc buildrom-devel/packages/coreboot-v3/coreboot-v3.mk buildrom-devel/packages/coreinfo/coreinfo.mk buildrom-devel/packages/filo/filo.mk buildrom-devel/packages/geodevsa/openvsa.inc buildrom-devel/packages/grub2/grub2.mk buildrom-devel/packages/libpayload/libpayload.mk buildrom-devel/packages/nrv2b/nrv2b.mk buildrom-devel/packages/ofw/ofw.mk buildrom-devel/packages/openbios/openbios.mk Log: Small makefile fixes: 1. filo's extract target depended on $(FILO_STAMP_DIR)/.patched, which we don't have anymore. Replaced with a dependency on $(FILO_STAMP_DIR)/.unpacked 2. add dependency on the relevant LOG_DIR in the TARBALL target for a lot of packages, to avoid errors when that log directory has not been created yet. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: buildrom-devel/packages/coreboot-v2/coreboot.inc =================================================================== --- buildrom-devel/packages/coreboot-v2/coreboot.inc 2008-11-26 21:21:30 UTC (rev 254) +++ buildrom-devel/packages/coreboot-v2/coreboot.inc 2008-12-05 19:45:09 UTC (rev 255) @@ -144,7 +144,7 @@ @ svn status > $(OUTPUT_DIR)/config/svn/svn.status endif -$(SOURCE_DIR)/$(CBV2_TARBALL): +$(SOURCE_DIR)/$(CBV2_TARBALL): | $(CBV2_LOG_DIR) @ echo "Fetching the coreboot rev $(CBV2_TAG) code..." @ mkdir -p $(SOURCE_DIR)/coreboot @ $(BIN_DIR)/fetchsvn.sh $(CBV2_URL) $(SOURCE_DIR)/coreboot \ Modified: buildrom-devel/packages/coreboot-v3/coreboot-v3.mk =================================================================== --- buildrom-devel/packages/coreboot-v3/coreboot-v3.mk 2008-11-26 21:21:30 UTC (rev 254) +++ buildrom-devel/packages/coreboot-v3/coreboot-v3.mk 2008-12-05 19:45:09 UTC (rev 255) @@ -48,7 +48,7 @@ CBV3_PATCHES ?= -$(SOURCE_DIR)/$(CBV3_TARBALL): +$(SOURCE_DIR)/$(CBV3_TARBALL): | $(CBV3_LOG_DIR) @ mkdir -p $(SOURCE_DIR)/coreboot-v3 @ $(BIN_DIR)/fetchsvn.sh $(CBV3_URL) \ $(SOURCE_DIR)/coreboot-v3 $(CBV3_TAG) \ Modified: buildrom-devel/packages/coreinfo/coreinfo.mk =================================================================== --- buildrom-devel/packages/coreinfo/coreinfo.mk 2008-11-26 21:21:30 UTC (rev 254) +++ buildrom-devel/packages/coreinfo/coreinfo.mk 2008-12-05 19:45:09 UTC (rev 255) @@ -22,7 +22,7 @@ COREINFO_TARBALL=coreinfo-svn-$(COREINFO_TAG).tar.gz -$(SOURCE_DIR)/$(COREINFO_TARBALL): +$(SOURCE_DIR)/$(COREINFO_TARBALL): | $(COREINFO_LOG_DIR) @ mkdir -p $(SOURCE_DIR)/coreinfo @ $(BIN_DIR)/fetchsvn.sh $(COREINFO_URL) $(SOURCE_DIR)/coreinfo \ $(COREINFO_TAG) $(SOURCE_DIR)/$(COREINFO_TARBALL) \ Modified: buildrom-devel/packages/filo/filo.mk =================================================================== --- buildrom-devel/packages/filo/filo.mk 2008-11-26 21:21:30 UTC (rev 254) +++ buildrom-devel/packages/filo/filo.mk 2008-12-05 19:45:09 UTC (rev 255) @@ -24,7 +24,7 @@ FILO_CONFIG = $(FILO_SRC_DIR)/configs/defconfig endif -$(SOURCE_DIR)/$(FILO_TARBALL): +$(SOURCE_DIR)/$(FILO_TARBALL): | $(FILO_LOG_DIR) @ mkdir -p $(SOURCE_DIR)/filo @ $(BIN_DIR)/fetchsvn.sh $(FILO_URL) $(SOURCE_DIR)/filo \ $(FILO_TAG) $(SOURCE_DIR)/$(FILO_TARBALL) \ @@ -75,7 +75,7 @@ filo-distclean: @ rm -rf $(FILO_DIR)/* -filo-extract: $(FILO_STAMP_DIR)/.patched +filo-extract: | $(FILO_STAMP_DIR)/.unpacked filo-config: | $(FILO_STAMP_DIR)/.configured ifeq ($(shell if [ -f $(PACKAGE_DIR)/filo/conf/customconfig--$(PAYLOAD)--$(COREBOOT_VENDOR)-$(COREBOOT_BOARD) ]; then echo 1; fi),1) Modified: buildrom-devel/packages/geodevsa/openvsa.inc =================================================================== --- buildrom-devel/packages/geodevsa/openvsa.inc 2008-11-26 21:21:30 UTC (rev 254) +++ buildrom-devel/packages/geodevsa/openvsa.inc 2008-12-05 19:45:09 UTC (rev 255) @@ -17,7 +17,7 @@ OPENVSA_FETCH_LOG=$(OPENVSA_LOG_DIR)/fetch.log endif -$(SOURCE_DIR)/$(OPENVSA_TARBALL): +$(SOURCE_DIR)/$(OPENVSA_TARBALL): | $(OPENVSA_LOG_DIR) @ mkdir -p $(SOURCE_DIR)/openvsa @ mkdir -p $(OPENVSA_LOG_DIR) @ echo "Fetching openvsa..." Modified: buildrom-devel/packages/grub2/grub2.mk =================================================================== --- buildrom-devel/packages/grub2/grub2.mk 2008-11-26 21:21:30 UTC (rev 254) +++ buildrom-devel/packages/grub2/grub2.mk 2008-12-05 19:45:09 UTC (rev 255) @@ -29,7 +29,7 @@ GRUB2_CONFIG = $(GRUB2_SRC_DIR)/configs/defconfig endif -$(SOURCE_DIR)/$(GRUB2_TARBALL): +$(SOURCE_DIR)/$(GRUB2_TARBALL): | $(GRUB2_LOG_DIR) @ mkdir -p $(SOURCE_DIR)/grub2 @ $(BIN_DIR)/fetchsvn.sh $(GRUB2_URL) $(SOURCE_DIR)/grub2 \ $(GRUB2_TAG) $(SOURCE_DIR)/$(GRUB2_TARBALL) \ Modified: buildrom-devel/packages/libpayload/libpayload.mk =================================================================== --- buildrom-devel/packages/libpayload/libpayload.mk 2008-11-26 21:21:30 UTC (rev 254) +++ buildrom-devel/packages/libpayload/libpayload.mk 2008-12-05 19:45:09 UTC (rev 255) @@ -28,7 +28,7 @@ LIBPAYLOAD_TARBALL=libpayload-svn-$(LIBPAYLOAD_TAG).tar.gz -$(SOURCE_DIR)/$(LIBPAYLOAD_TARBALL): +$(SOURCE_DIR)/$(LIBPAYLOAD_TARBALL): | $(LIBPAYLOAD_LOG_DIR) @ mkdir -p $(SOURCE_DIR)/libpayload @ $(BIN_DIR)/fetchsvn.sh $(LIBPAYLOAD_URL) $(SOURCE_DIR)/libpayload \ $(LIBPAYLOAD_TAG) $(SOURCE_DIR)/$(LIBPAYLOAD_TARBALL) \ Modified: buildrom-devel/packages/nrv2b/nrv2b.mk =================================================================== --- buildrom-devel/packages/nrv2b/nrv2b.mk 2008-11-26 21:21:30 UTC (rev 254) +++ buildrom-devel/packages/nrv2b/nrv2b.mk 2008-12-05 19:45:09 UTC (rev 255) @@ -15,7 +15,7 @@ NRV2B_FETCH_LOG=$(NRV2B_LOG_DIR)/fetch.log endif -$(SOURCE_DIR)/$(NRV2B_TARBALL): +$(SOURCE_DIR)/$(NRV2B_TARBALL): | $(NRV2B_LOG_DIR) @ mkdir -p $(SOURCE_DIR)/nrv2b @ $(BIN_DIR)/fetchsvn.sh $(NRV2B_URL) $(SOURCE_DIR)/nrv2b \ $(NRV2B_TAG) $@ > $(NRV2B_FETCH_LOG) 2>&1 Modified: buildrom-devel/packages/ofw/ofw.mk =================================================================== --- buildrom-devel/packages/ofw/ofw.mk 2008-11-26 21:21:30 UTC (rev 254) +++ buildrom-devel/packages/ofw/ofw.mk 2008-12-05 19:45:09 UTC (rev 255) @@ -26,7 +26,7 @@ # NOTE - this should be replaced by the GIT fetch or tarball fetch # as appropriate -$(SOURCE_DIR)/$(OFW_TARBALL): +$(SOURCE_DIR)/$(OFW_TARBALL): | $(OFW_LOG_DIR) @ echo "Fetching OpenFirmware..." @ echo "SVN Checkout rev $(OFW_SVN_TAG)" @ $(BIN_DIR)/fetchsvn.sh $(OFW_SVN_URL) $(SOURCE_DIR)/ofw \ Modified: buildrom-devel/packages/openbios/openbios.mk =================================================================== --- buildrom-devel/packages/openbios/openbios.mk 2008-11-26 21:21:30 UTC (rev 254) +++ buildrom-devel/packages/openbios/openbios.mk 2008-12-05 19:45:09 UTC (rev 255) @@ -31,7 +31,7 @@ $(error To build OpenBIOS, you need to install 'fcode-utils') endif -$(SOURCE_DIR)/$(OPENBIOS_TARBALL): +$(SOURCE_DIR)/$(OPENBIOS_TARBALL): | $(OPENBIOS_LOG_DIR) @ echo "Fetching OpenBIOS..." @ echo "SVN Checkout rev $(OPENBIOS_SVN_TAG)" @ $(BIN_DIR)/fetchsvn.sh $(OPENBIOS_SVN_URL) $(SOURCE_DIR)/openbios \

1 0

Resources and links
by Myles Watson 05 Dec '08

05 Dec '08

I've been thinking about getting rid of the links in v3, or changing their meaning. I can't see anywhere that they're being used right now. The problem is how to deal with k8. It has "multiple links", but not in the same sense as v3. In v3, multiple links means logical connections to multiple devices. K8 has multiple physical connections, but only one logical connection. This is a problem for resource allocation (the current implementation as well as my patch.) The idea is that for every bridge resource gets all matching resources from the sub-tree packed into it. The problem is that for k8 there can be multiple bridge resources of the same type, and to know which resources to pack into it, you have to know which physical link they are connected to. At the same time, all the children are logically connected to the same PCI. This could be solved in several ways, but I'm hoping that there's an elegant way that I haven't thought of yet. Here are a couple I was thinking of: 1. Let links have resources, and make all bridge resources live there. I don't like this one because links aren't needed anywhere else, and this just makes links larger. 2. Give bridges a function which returns the children under a resource. It's an extra function for all bridges, but most would just return all children. I'm sure there are myriad other ways. I'm looking for one that will be easy to explain and implement correctly. Thanks, Myles

2 1

IRQ problems under qemu
by Tomas Carnecky 05 Dec '08

05 Dec '08

When I tried to run coreboot under qemu, I was at first positively surprised how well the things worked. The BIOS + linux kernel payload booted in no time! But when I then tried to set up networking, I couldn't get that to work. Somehow the linux kernel couldn't locate the interrupts of the NIC. After some digging I found out that coreboot doesn't provide ACPI tables and instead uses PCI IRQ table (I had to extract this table from a running qemu system using the getpir utility and then copy it to coreboot, if you want that patch, I can send that too). Coreboot copies this table at runtime into memory at 0xf0000. Apparently 0xf0000-0xfffff is part of the ISA BIOS, and qemu marks this range as read-only. The attached patch for qemu fixes that and also cleans up some of the memory initialization. Instead of marking the ISA BIOS as read-only, it copies that part from the BIOS image into the appropriate place (at 0xf0000-0xfffff) and leaves the memory as read-write. tom

2 1

Patches for ACPI support on dbm690t (reset TALERT of ADT7461)
by Bao, Zheng 05 Dec '08

05 Dec '08

The TALERT of ADT7461 should be pull back high if the temperature is within the limit. It is done by reading the register whose device address is 0xC. It is not trivial as it looks. Signed-off-by: Maggie Li <maggie.li(a)amd.com> Reviewed-by: Joe Bao <zheng.bao(a)amd.com>

3 2

r3801 - trunk/coreboot-v2/src/mainboard/amd/dbm690t
by svn＠coreboot.org 05 Dec '08

05 Dec '08

Author: mjones Date: 2008-12-05 19:38:57 +0100 (Fri, 05 Dec 2008) New Revision: 3801 Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c Log: The TALERT of ADT7461 should be pull back high if the temperature is within the limit. It is done by reading the register whose device address is 0xC. It is not trivial as it looks. Signed-off-by: Maggie Li <maggie.li(a)amd.com> Reviewed-by: Joe Bao <zheng.bao(a)amd.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2008-12-05 14:15:17 UTC (rev 3800) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2008-12-05 18:38:57 UTC (rev 3801) @@ -28,6 +28,7 @@ #include "chip.h" #define ADT7461_ADDRESS 0x4C +#define ARA_ADDRESS 0x0C /* Alert Response Address */ #define SMBUS_IO_BASE 0x1000 extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); @@ -35,6 +36,8 @@ u8 val); #define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) +#define ARA_read_byte(address) \ + do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address) #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) @@ -132,6 +135,7 @@ ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */ byte = ADT7461_read_byte(0x02); /* read status register to clear it */ + ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ printk_info("Init adt7461 end , status 0x02 %02x\n", byte); /* sb600 settings for thermal config */

1 0

Re: [coreboot] Coreboot on an Acer Aspire 3680?
by Daniel Levine 05 Dec '08

05 Dec '08

Peter Stuge wrote: >No help I'm afraid. > >There may be a hardware signal disabling writes to the flash chip, in >which case I think you'll have to bring out the soldering iron. > >Could you take the system apart and identify the flash chip visually? Unfortunately no... Thanks for the help anyway.

1 0

Re: [coreboot] Flashrom problem on VIA EPIA CN13000G
by bari 05 Dec '08

05 Dec '08

Sunggekun wrote: > Hi Bari, > > i have Flashrom problem on VIA EPIA CN13000G, > and saw this tutorial http://www.coreboot.org/VIA_EPIA-CN , > it says: > Flashrom OK SST 512KB, 1MB, 2MB, PMC 512KB > > while trying to flash SST49LF0008A (1MB),i got this result: > # ./flashrom > Calibrating delay loop... ok > No LinuxBIOS table found. > Found chipset "VT8237": Enabling flash write... OK. > Found board "VIA EPIA-CN": Enabling flash write... OK. > No EEPROM/flash device found > > Can SST49LF0008A work on VIA EPIA CN13000G? i missed to setup something? > and how did you flash SST 1MB roms? > > > > Sunggekun > > SST49LF080A-33-4C-NHE works great! We also use the 49LF016C-33-4C-NH in the same VIA Epia boards without any problems. -Bari

1 0

[PATCH] v2: Support for the NEC PowerMate 2000 board
by Uwe Hermann 05 Dec '08

05 Dec '08

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

r3800 - in trunk/coreboot-v2: src/mainboard src/mainboard/nec src/mainboard/nec/powermate2000 targets targets/nec targets/nec/powermate2000
by svn＠coreboot.org 05 Dec '08

05 Dec '08

Author: uwe Date: 2008-12-05 15:15:17 +0100 (Fri, 05 Dec 2008) New Revision: 3800 Added: trunk/coreboot-v2/src/mainboard/nec/ trunk/coreboot-v2/src/mainboard/nec/powermate2000/ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Config.lb trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb trunk/coreboot-v2/src/mainboard/nec/powermate2000/auto.c trunk/coreboot-v2/src/mainboard/nec/powermate2000/chip.h trunk/coreboot-v2/src/mainboard/nec/powermate2000/irq_tables.c trunk/coreboot-v2/src/mainboard/nec/powermate2000/mainboard.c trunk/coreboot-v2/targets/nec/ trunk/coreboot-v2/targets/nec/powermate2000/ trunk/coreboot-v2/targets/nec/powermate2000/Config.lb Log: Add initial support for the NEC PowerMate 2000 board. See details at: http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/ Thanks to Quentin RAMEAU <quentin.rameau(a)gmail.com> for providing the required information and for testing the patch. This boots into a Linux console just fine. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Added: trunk/coreboot-v2/src/mainboard/nec/powermate2000/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/Config.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Config.lb 2008-12-05 14:15:17 UTC (rev 3800) @@ -0,0 +1,135 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE object irq_tables.o end +# object reset.o +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(MAINBOARD)/auto.c ../romcc" + action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(MAINBOARD)/auto.c ../romcc" + action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc +dir /pc80 +config chip.h + +chip northbridge/intel/i82810 # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/socket_PGA370 # CPU + device apic 0 on end # APIC + end + end + device pci_domain 0 on + device pci 0.0 on end # Host bridge + device pci 1.0 off # Onboard video + # chip drivers/pci/onboard + # device pci 1.0 on end + # register "rom_address" = "0xfff80000" + # end + end + chip southbridge/intel/i82801xx # Southbridge + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # ISA/LPC bridge + chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47B27x) + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off end # Com2 (N/A) + device pnp 2e.7 on # PS/2 keyboard + irq 0x70 = 1 + irq 0x72 = 0 + end + device pnp 2e.9 off end # Game port (N/A) + device pnp 2e.a on # Power-management events (PME) + io 0x60 = 0x800 + end + device pnp 2e.b on # MIDI port + io 0x60 = 0x330 + irq 0x70 = 5 + end + end + end + device pci 1f.1 on end # IDE + device pci 1f.2 on end # USB + device pci 1f.3 on end # SMBus + device pci 1f.5 on end # AC'97 audio + device pci 1f.6 off end # AC'97 modem (N/A) + end + end +end + Added: trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb 2008-12-05 14:15:17 UTC (rev 3800) @@ -0,0 +1,98 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses COREBOOT_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_PRECOMPRESSED_PAYLOAD +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN + +default ROM_SIZE = 512 * 1024 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default HAVE_OPTION_TABLE = 0 +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 9 +default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default CONFIG_CONSOLE_VGA = 1 +default CONFIG_PCI_ROM_RUN = 1 + +end Added: trunk/coreboot-v2/src/mainboard/nec/powermate2000/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/auto.c 2008-12-05 14:15:17 UTC (rev 3800) @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include <stdlib.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" +#include "northbridge/intel/i82810/raminit.h" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "pc80/udelay_io.c" +#include "northbridge/intel/i82810/raminit.c" + +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) + +static void main(unsigned long bist) +{ + if (bist == 0) + early_mtrr_init(); + + smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + enable_smbus(); + + report_bist_failure(bist); + + /* dump_spd_registers(); */ + sdram_set_registers(); + sdram_set_spd_registers(); + sdram_enable(); + /* ram_check(0, 640 * 1024); */ +} Added: trunk/coreboot-v2/src/mainboard/nec/powermate2000/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/chip.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/chip.h 2008-12-05 14:15:17 UTC (rev 3800) @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_nec_powermate2000_ops; + +struct mainboard_nec_powermate2000_config { +}; Added: trunk/coreboot-v2/src/mainboard/nec/powermate2000/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/irq_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/irq_tables.c 2008-12-05 14:15:17 UTC (rev 3800) @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router device */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x6e, /* Checksum */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x1e << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0}, + {0x01, (0x03 << 3) | 0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, + {0x01, (0x04 << 3) | 0x0, {{0x62, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, + {0x00, (0x1f << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0}, + {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/coreboot-v2/src/mainboard/nec/powermate2000/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/mainboard.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/mainboard.c 2008-12-05 14:15:17 UTC (rev 3800) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_nec_powermate2000_ops = { + CHIP_NAME("NEC PowerMate 2000 Mainboard") +}; Added: trunk/coreboot-v2/targets/nec/powermate2000/Config.lb =================================================================== --- trunk/coreboot-v2/targets/nec/powermate2000/Config.lb (rev 0) +++ trunk/coreboot-v2/targets/nec/powermate2000/Config.lb 2008-12-05 14:15:17 UTC (rev 3800) @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target powermate2000 +mainboard nec/powermate2000 + +option ROM_SIZE = 512 * 1024 + +option MAINBOARD_VENDOR = "NEC" +option MAINBOARD_PART_NUMBER = "PowerMate 2000" + +option IRQ_SLOT_COUNT = 5 + +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 + +option CONFIG_CONSOLE_VGA = 1 +option CONFIG_PCI_ROM_RUN = 1 + +romimage "normal" + option USE_FALLBACK_IMAGE = 0 + option COREBOOT_EXTRA_VERSION = ".0Normal" + payload ../payload.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option COREBOOT_EXTRA_VERSION = ".0Fallback" + payload ../payload.elf +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"

1 0

← Newer
1
...
24
25
26
27
28
29
30
...
33
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot December 2008