coreboot December 2008

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330 discussions

[PATCH] flashrom: Add SB700 support
by Niels Ole Salscheider 05 Dec '08

05 Dec '08

This patch adds SB700 support to flashrom and fixes a small compilation error for GCC 4.3.2. The code for enabling the flash rom is the same as for SB600. It was tested (read, write, verify) with an ASUS M3A-H/HDMI which contains a Macronix MX25L8005. Signed-off-by: Niels Ole Salscheider <niels_ole(a)salscheider-online.de> ---

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r3799 - trunk/util/flashrom
by svn＠coreboot.org 05 Dec '08

05 Dec '08

Author: stuge Date: 2008-12-05 12:58:43 +0100 (Fri, 05 Dec 2008) New Revision: 3799 Modified: trunk/util/flashrom/chipset_enable.c Log: flashrom: Add AMD SB700 flash enable This patch adds SB700 support to flashrom. The code for enabling the flash rom is the same as for SB600. It was tested (read, write, verify) with an ASUS M3A-H/HDMI which contains a Macronix MX25L8005. Signed-off-by: Niels Ole Salscheider <niels_ole(a)salscheider-online.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2008-12-05 11:56:57 UTC (rev 3798) +++ trunk/util/flashrom/chipset_enable.c 2008-12-05 11:58:43 UTC (rev 3799) @@ -910,6 +910,7 @@ {0x1022, 0x2080, "AMD CS5536", enable_flash_cs5536}, {0x1022, 0x7468, "AMD8111", enable_flash_amd8111}, {0x1002, 0x438D, "ATI(AMD) SB600", enable_flash_sb600}, + {0x1002, 0x439d, "ATI(AMD) SB700", enable_flash_sb600}, {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533}, {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */ {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */

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r3798 - trunk/util/flashrom
by svn＠coreboot.org 05 Dec '08

05 Dec '08

Author: stuge Date: 2008-12-05 12:56:57 +0100 (Fri, 05 Dec 2008) New Revision: 3798 Modified: trunk/util/flashrom/flashrom.c Log: flashrom: Fix compilation of r3797 with gcc-4.3.2 Thanks to Niels Ole Salscheider for the problem report. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flashrom.c =================================================================== --- trunk/util/flashrom/flashrom.c 2008-12-05 02:22:30 UTC (rev 3797) +++ trunk/util/flashrom/flashrom.c 2008-12-05 11:56:57 UTC (rev 3798) @@ -250,7 +250,7 @@ { uint8_t *buf; unsigned long size; - size_t erasedbytes; + uint32_t erasedbytes; FILE *image; /* Probe for up to three flash chips. */ struct flashchip *flash, *flashes[3];

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Flashrom problems on VIA EPIA CN13000G
by 劉正強 05 Dec '08

05 Dec '08

Hi all ! I have an VIA EPIA CN13000G board , and bought five SST49LF008A chips from internet. Now Trying to flash these chips, but i got this result: # ./flashrom Calibrating delay loop... ok No LinuxBIOS table found. Found chipset "VT8237": Enabling flash write... OK. Found board "VIA EPIA-CN": Enabling flash write... OK. No EEPROM/flash device found. Also i tried to flash original BIOS rom (SST49LF004B), it work fine (read/write). So what did i miss? Could someone tell me what to do ?

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Re: [coreboot] Coreboot on Tyan S2892
by Myles Watson 05 Dec '08

05 Dec '08

On Thu, Dec 4, 2008 at 3:25 PM, Anose, Bijoy K (N-Aerotek) < bijoy.k.anose(a)lmco.com> wrote: > That seemed to be the case, but it is not exactly correct. The LAB > kernel (and kernels I've built) consistently are only seeing > part of the drives. The two drives in my setup each have 1 partition that > is outside any swraid, and several partitions that are > in a raid1 between the two drives. > I wish I knew more about swraid. Hopefully someone else on the list will know more. > Each time I boot and kexec my target kernel from LAB, creation of the > swraid is failing. It complains that it can't find /dev/sda2 > (part of the swraid). However, I can manually mount /dev/sda1 without > issues. > > The whole boot process (including the swraid assembly, etc) has always been > successful when booting with legacy BIOS. > To be clear, we do not use the onboard RAID controller at all. > > It appears to me that coreboot is maybe not fully/correctly initializing > the SATA controller as the BIOS is. > This is very possible. Are there any illuminating error messages when the drive fails to mount? Have you compared a very verbose lspci of the SATA controller? lspci -vvxxx > Also, I'm curious what other cards, if any, you had in your machine when > you were able to boot successfully? Eventually, I > need to be able to boot with some multi-port serial cards and a multi-port > NIC (a Broadcom card that Stepan and others have > seen issues with). Right now, with coreboot I get no VGA or serial console > output whatsoever when those are present, so I've > been doing all my experimenting with those cards removed. > I've never used any cards in the machine. Just a HyperTransport module. Thanks, Myles ------------------------------ *From:* Myles Watson [mailto:mylesgw@gmail.com] *Sent:* Thursday, November 20, 2008 11:47 AM *To:* Anose, Bijoy K (N-Aerotek) *Cc:* Ward Vandewege; Coreboot *Subject:* Re: [coreboot] Coreboot on Tyan S2892 On Thu, Nov 20, 2008 at 10:24 AM, Anose, Bijoy K (N-Aerotek) < bijoy.k.anose(a)lmco.com> wrote: > Yes, it is busybox-based, and yes, the final kernel is definitely getting > run, as evidenced by 'uname -a' output at the busybox > prompt. The file '/dev/sda' does exist.. I don't remember the major/minor > numbers, etc. > > My .config file is attached. I am not modifying the skeleton/* files. > > -Bijoy > All right. The only differences I see are that you are building on a 32-bit machine and you're building a 32-bit LAB image. CONFIG_TARGET_64BIT CONFIG_CHOOSE_64BIT Since your kernel gets loaded, I don't see why either of those should matter. It seems like there's a difference between the way your LAB kernel and your regular kernel are handling the SATA drive. Since the LAB kernel finds and reads it, but yours doesn't... I hope that helps. Thanks, Myles > ------------------------------ > *From:* Myles Watson [mailto:mylesgw@gmail.com] > *Sent:* Wednesday, November 19, 2008 3:24 PM > *To:* Anose, Bijoy K (N-Aerotek) > *Cc:* Ward Vandewege; Coreboot > *Subject:* Re: [coreboot] Coreboot on Tyan S2892 > > > > On Wed, Nov 19, 2008 at 2:12 PM, Anose, Bijoy K (N-Aerotek) < > bijoy.k.anose(a)lmco.com> wrote: > >> I enabled the busybox option and used the default value of "5 second >> pause to allow access to busybox" but it doesn't >> pause anywhere, as far as I can tell. Coreboot starts, LAB starts, LAB >> kexecs the kernel/initrd on the SATA disk, and >> then at that busybox prompt, I get no output when I issue "fdisk -l >> /dev/sda". >> > > So your kernel/initrd is busybox-based as well? Is the new kernel really > getting run? > > I'd start with ls -l /dev/sda or something simple like that. > > >> Could you send me a tarball of your buildrom-devel? >> > Since it's old I don't think that would be really helpful. Are you > changing the .config files? Are you changing the skeleton/ files? > > >> Something must be different in our config. Also your lab.conf and >> the kernel/initrd that is on your SATA disk, if that would ok. >> > I don't have that machine up right now, so it would take a while. I think > there's a shorter path to the answer than that. > > >> I built my own static kexec and xfer'd it to the SATA drive. >> > Great. > > >> Multiple drives shouldn't make any difference -- if the controller can >> see one drive, it can see them all (if it is actually >> working properly). >> > > You're right. If they don't all work it's a bug. Maybe it's been fixed. > If you're only using two drives, though, it's probably not that. > > >> My system may have 2 drives or 8, depending on its function. The one >> I'm currently experimenting >> > with has only 2 installed. >> > >> -Bijoy >> >> (sorry again for top-posting, Outlook is acting differently over >> VPN/rdesktop for some reason) >> >> ------------------------------ >> *From:* Myles Watson [mailto:mylesgw@gmail.com] >> *Sent:* Wednesday, November 19, 2008 11:19 AM >> *To:* Anose, Bijoy K (N-Aerotek) >> *Cc:* Ward Vandewege; Coreboot >> *Subject:* Re: [coreboot] Coreboot on Tyan S2892 >> >> >> >> On Wed, Nov 19, 2008 at 9:40 AM, Anose, Bijoy K (N-Aerotek) < >> bijoy.k.anose(a)lmco.com> wrote: >> >>> > From: Ward Vandewege [mailto:ward@gnu.org] >>> > Sent: Thursday, November 13, 2008 6:56 PM >>> > To: Anose, Bijoy K (N-Aerotek) >>> > Cc: Myles Watson; Marc Jones; Coreboot >>> > Subject: Re: [coreboot] Coreboot on Tyan S2892 >>> > >>> > On Thu, Nov 13, 2008 at 07:04:49PM -0500, Anose, Bijoy K >>> > (N-Aerotek) wrote: >>> > > > So far it's just me seeing that, on one specific board >>> > (s2891). So >>> > > > don't worry about that too much just yet. >>> > > >>> > > True, I'll cross that bridge when I get there. >>> > > >>> > > First I'll need to be able to boot, period. So far, what >>> > I've done is >>> > > this: >>> > > >>> > > 1. Subversion checkout of latest buildrom 2. make menuconfig, >>> > > specifying Tyan S2892, 32-bit LAB 3. make >>> > > >>> > > Do I need to do further configuration (Config.lb etc)? I >>> > thought that >>> > > the menuconfig took care of everything. Maybe that was wishful >>> > > thinking.. >>> > >>> > It's not. The only other thing you need to do is *pre*pend >>> > the vga image to the generated image, which will generate an >>> > image that is exactly 1024KB large, and which you can flash, >>> > and which *should* just boot your system. >>> > >>> >>> I finally got coreboot+LAB to boot my target kernel/initrd on the SATA >>> disks (many thanks to Ward)! >>> >>> However, once the init script in the initrd attempts to assembly the >>> software >>> RAID, it fails because it can't see the SATA disks. >> >> How many do you have? Ward has seen a problem with some disk controllers >> not functioning on the ck804. I've never used more than one. >> >> >>> My guess is that coreboot is originally doing some low level block reads >>> from >>> the disk to load the kernel/initrd but when the final kernel attempts to >>> do a >>> SATA read from the disk, the controller has not been fully/properly >>> initialized, >>> and it fails. >> >> >> Have you tried configure the busybox shell to not load automatically, and >> looked at the SATA drives from there? >> >> I assume that whatever modifications that Myles made to successfully >>> boot from >>> SATA devices with coreboot+LAB on S2892 have trickled down to buildrom.. >> >> I used buildrom. I think the multiple drives may be getting you, though. >> >> Thanks, >> Myles >> >> >

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Re: [coreboot] Coreboot on an Acer Aspire 3680?
by Daniel Levine 05 Dec '08

05 Dec '08

Stefan: flashrom -r gives me this: Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically.

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#117: flashrom: Check if erase succeeds and exit with error on failure
by coreboot 05 Dec '08

05 Dec '08

#117: flashrom: Check if erase succeeds and exit with error on failure ----------------------------------------------+----------------------------- Reporter: stuge | Owner: stuge Type: defect | Status: new Priority: blocker | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: erase error | Dependencies: Patchstatus: patch is ready to be committed | ----------------------------------------------+----------------------------- -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/117> coreboot <http://www.coreboot.org/>

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r3797 - trunk/util/flashrom
by svn＠coreboot.org 05 Dec '08

05 Dec '08

Author: stuge Date: 2008-12-05 03:22:30 +0100 (Fri, 05 Dec 2008) New Revision: 3797 Modified: trunk/util/flashrom/flashrom.c Log: flashrom: Check if erase succeeds and exit with error on failure. flashrom used to exit 0 even if erase failed. Not anymore. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/flashrom.c =================================================================== --- trunk/util/flashrom/flashrom.c 2008-12-04 23:42:36 UTC (rev 3796) +++ trunk/util/flashrom/flashrom.c 2008-12-05 02:22:30 UTC (rev 3797) @@ -250,6 +250,7 @@ { uint8_t *buf; unsigned long size; + size_t erasedbytes; FILE *image; /* Probe for up to three flash chips. */ struct flashchip *flash, *flashes[3]; @@ -533,13 +534,25 @@ if (erase_it) { printf("Erasing flash chip... "); - if (!flash->erase) { - fprintf(stderr, "Error: flashrom has no erase function for this flash chip.\n"); + if (NULL == flash->erase) { + printf("FAILED!\n"); + fprintf(stderr, "ERROR: flashrom has no erase function for this flash chip.\n"); return 1; } flash->erase(flash); - printf("done.\n"); - exit(0); + if (NULL == flash->read) + memcpy(buf, (const char *)flash->virtual_memory, size); + else + flash->read(flash, buf); + for (erasedbytes = 0; erasedbytes <= size; erasedbytes++) + if (0xff != buf[erasedbytes]) { + printf("FAILED!\n"); + fprintf(stderr, "ERROR at 0x%08x: Expected=0xff, Read=0x%02x\n", + erasedbytes, buf[erasedbytes]); + return 1; + } + printf("SUCCESS.\n"); + return 0; } else if (read_it) { if ((image = fopen(filename, "w")) == NULL) { perror(filename);

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Coreboot on an Acer Aspire 3680?
by Daniel Levine 05 Dec '08

05 Dec '08

My Aspire 3680 has a bad BIOS, is no longer under warranty, and is already leaning towards obsolescence a year and a half after its purchase; I'm wondering if Coreboot might work on it. The output of lspci follows: 00:00.0 Host bridge: Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and 945GT Express Memory Controller Hub (rev 03) 00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller (rev 03) 00:02.1 Display controller: Intel Corporation Mobile 945GM/GMS/GME, 943/940GML Express Integrated Graphics Controller (rev 03) 00:1b.0 Audio device: Intel Corporation 82801G (ICH7 Family) High Definition Audio Controller (rev 02) 00:1c.0 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 1 (rev 02) 00:1c.1 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 2 (rev 02) 00:1c.2 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 3 (rev 02) 00:1d.0 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #1 (rev 02) 00:1d.1 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #2 (rev 02) 00:1d.2 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #3 (rev 02) 00:1d.3 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #4 (rev 02) 00:1d.7 USB Controller: Intel Corporation 82801G (ICH7 Family) USB2 EHCI Controller (rev 02) 00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev e2) 00:1f.0 ISA bridge: Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge (rev 02) 00:1f.2 IDE interface: Intel Corporation 82801GBM/GHM (ICH7 Family) SATA IDE Controller (rev 02) 00:1f.3 SMBus: Intel Corporation 82801G (ICH7 Family) SMBus Controller (rev 02) 02:00.0 Ethernet controller: Marvell Technology Group Ltd. 88E8038 PCI-E Fast Ethernet Controller (rev 14) 03:00.0 Ethernet controller: Atheros Communications Inc. AR242x 802.11abg Wireless PCI Express Adapter (rev 01) 0a:09.0 CardBus bridge: Texas Instruments PCIxx12 Cardbus Controller 0a:09.2 Mass storage controller: Texas Instruments 5-in-1 Multimedia Card Reader (SD/MMC/MS/MS PRO/xD) How well are 945GM and 82801G supported? Could I actually have Coreboot working on this machine, or would I only succeed in bricking it? Would I need custom code for the laptop? Also, for whatever it's worth - can Coreboot load GNU GRUB (or FreeBSD's BTX bootloader) instead of a Linux kernel?

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NEC PowerMate2000(Celeron) info
by Quentin RAMEAU 05 Dec '08

05 Dec '08

lspci -tvnn ------------------------------------------------------------------------------------------------------------------------------------------------------- -[0000:00]-+-00.0 Intel Corporation 82810 GMCH (Graphics Memory Controller Hub) [8086:7120] +-01.0 Intel Corporation 82810 (CGC) Chipset Graphics Controller [8086:7121] +-1e.0-[0000:01-09]--+-03.0 Texas Instruments PCI1420 PC card Cardbus Controller [104c:ac51] | +-03.1 Texas Instruments PCI1420 PC card Cardbus Controller [104c:ac51] | \-04.0 Intel Corporation 82557/8/9/0/1 Ethernet Pro 100 [8086:1229] +-1f.0 Intel Corporation 82801AB ISA Bridge (LPC) [8086:2420] +-1f.1 Intel Corporation 82801AB IDE Controller [8086:2421] +-1f.2 Intel Corporation 82801AB USB Controller [8086:2422] +-1f.3 Intel Corporation 82801AB SMBus Controller [8086:2423] \-1f.5 Intel Corporation 82801AB AC'97 Audio Controller [8086:2425] superiotool -dV ------------------------------------------------------------------------------------------------------------------------------------------------------- superiotool r3784 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0x0000, rev=0x00 Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x5101, rev=0x9 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0x5101, rev=0x9 Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0x5101, rev=0x9 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x5101, rev=0x9 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Found SMSC LPC47B27x (id=0x51, rev=0x01) at 0x2e Register dump: idx 03 20 21 22 23 24 26 27 28 2a 2b 2c 2d 2e 2f val 00 51 01 19 19 44 2e 00 00 00 00 00 00 00 00 def RR 51 NA 00 00 04 MM MM RR NA NA NA NA NA NA LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 01 03 f0 06 02 0e 00 ff 08 08 def 00 03 f0 06 02 0e 00 ff 00 00 LDN 0x03 (Parallel port) idx 30 60 61 70 74 f0 f1 val 01 03 78 07 04 38 00 def 00 00 00 00 04 3c 00 LDN 0x04 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 00 00 00 00 00 LDN 0x05 (COM2) idx 30 60 61 62 63 70 74 f0 f1 f2 val 00 00 00 00 00 00 04 00 02 03 def NA 00 00 00 00 00 04 00 02 03 LDN 0x07 (Keyboard) idx 30 70 72 f0 val 01 01 00 04 def 00 00 00 00 LDN 0x09 (Game port) idx 30 60 61 val 00 00 00 def 00 00 00 LDN 0x0a (Power-management events (PME)) idx 30 60 61 f0 f1 val 01 08 00 00 00 def 00 00 00 NA NA LDN 0x0b (MIDI port (MPU-401)) idx 30 60 61 70 val 00 03 30 05 def 00 03 30 05 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0x00/0x00, rev=0x00 Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0x00/0x00, rev=0x00 Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0x00/0x00, rev=0x00 Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0x00/0x00, rev=0x00 Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff irq_tables.c ------------------------------------------------------------------------------------------------------------------------------------------------------- /* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * * Contains the IRQ Routing Table dumped directly from your * memory, which BIOS sets up. * * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx */ #ifdef GETPIR #include "pirq_routing.h" #else #include <arch/pirq_routing.h> #endif const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32+16*5, /* There can be total 5 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x122e, /* Device */ 0, /* Miniport */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x6e, /* u8 checksum. This has to be set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x1e<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0}, {0x01,(0x03<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, {0x01,(0x04<<3)|0x0, {{0x62, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, {0x00,(0x1f<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0}, {0x00,(0x01<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, } }; unsigned long write_pirq_routing_table(unsigned long addr) { return copy_pirq_routing_table(addr); } mptable -grope ------------------------------------------------------------------------------------------------------------------------------------------------------- /* generated by MPTable, version 2.0.15*/ /* as modified by RGM for coreboot */ #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <string.h> #include <stdint.h> void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "LNXI "; static const char productid[12] = "P4DPE "; struct mp_config_table *mc; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); MP default config type: 115 future type future type /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); } unsigned long write_smp_table(unsigned long addr) { void *v; v = smp_write_floating_table(addr); return (unsigned long)smp_write_config_table(v); }

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coreboot December 2008