coreboot December 2008

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r3796 - trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se
by svn＠coreboot.org 05 Dec '08

05 Dec '08

Author: ruik Date: 2008-12-05 00:42:36 +0100 (Fri, 05 Dec 2008) New Revision: 3796 Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c Log: This belongs to changeset 3795. The patch changes the LDTSTOP length as well mostly default content of 0xec, 0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong. Furthermore this fix for powernow may not work on CPUs hit by errata #181. Workaround should be implemented. The powernow may not work on pre-A2 revisions of VT8237S silicon, revision reg is unknown. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2008-12-04 23:37:12 UTC (rev 3795) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2008-12-04 23:42:36 UTC (rev 3796) @@ -92,6 +92,8 @@ #define K8_4RANK_DIMM_SUPPORT 1 + + #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -102,6 +104,21 @@ #include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" + +#define SB_VFSMAF 0 + +/* this function might fail on some K8 CPUs with errata #181 */ +static void ldtstop_sb(void) +{ + print_debug("toggle LDTSTP#\r\n"); + u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c); + reg = reg ^ (1 << 0); + outb(reg, VT8237R_ACPI_IO_BASE + 0x5c); + reg = inb(VT8237R_ACPI_IO_BASE + 0x15); + print_debug("done\r\n"); +} + + #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/resourcemap.c"

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r3795 - in trunk/coreboot-v2/src: mainboard/asus/m2v-mx_se southbridge/via/vt8237r
by svn＠coreboot.org 05 Dec '08

05 Dec '08

Author: ruik Date: 2008-12-05 00:37:12 +0100 (Fri, 05 Dec 2008) New Revision: 3795 Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c Log: The patch changes the LDTSTOP length as well mostly default content of 0xec, 0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong. Furthermore this fix for powernow may not work on CPUs hit by errata #181. Workaround should be implemented. The powernow may not work on pre-A2 revisions of VT8237S silicon, revision reg is unknown. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2008-12-04 15:18:20 UTC (rev 3794) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2008-12-04 23:37:12 UTC (rev 3795) @@ -282,7 +282,7 @@ print_debug("after enable_fid_change\r\n"); /* FIXME does not work yet */ -// init_fidvid_bsp(bsp_apicid); + init_fidvid_bsp(bsp_apicid); /* Stop the APs so we can start them later in init. */ allow_all_aps_stop(bsp_apicid); Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c 2008-12-04 15:18:20 UTC (rev 3794) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c 2008-12-04 23:37:12 UTC (rev 3795) @@ -236,20 +236,10 @@ devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237_VLINK), 0); + if (devctl == PCI_DEV_INVALID) return; - /* TODO: Why is this an extra block? */ - { - u8 tmp; - tmp = pci_read_config8(devctl, 0xec); - print_debug("EC is "); - print_debug_hex8(tmp); - print_debug(" E5 is "); - tmp = pci_read_config8(dev, 0xe5); - print_debug_hex8(tmp); - } - /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); @@ -261,47 +251,15 @@ * Will work for C3 and for FID/VID change. */ - /* FIXME */ - outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); /* Maybe unneeded? */ -// outb(0x4, VT8237R_ACPI_IO_BASE + 0x50); /* Maybe unneeded? */ + outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); - /* It seems for AMD LDTSTP is connected not to SLP anymore. */ - /* Enable 0: DPSLP# / DPRSTP# / VRDSLP */ - - /* - * Enable SATA LED, VR timer = 100us. - * Enable DPSLP# / DPRSTP# / VRDSLP - WARNING LDTSTP connetcs - * to some of those pins! (and not to SLP as on R ver). - */ - pci_write_config8(dev, 0xe5, 0x69); /* FIXME */ - - /* - * REQ5 as PCI request input - should be together with - * INTE-INTH. Fast VR timer disable - need for LDTSTP signal. - */ - pci_write_config8(dev, 0xe4, 0xa5); - /* Reduce further the STPCLK/LDTSTP signal to 5us. */ pci_write_config8(dev, 0xec, 0x4); - /* Host Bus Power Management Control, maybe not needed. */ - pci_write_config8(dev, 0x8c, 0x5); - /* So the chip knows we are on AMD. */ - pci_write_config8(devctl, 0x7c, 0x77); + pci_write_config8(devctl, 0x7c, 0x7f); - devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - 0x2336), 0); - if (devctl == PCI_DEV_INVALID) - return; - - /* - * Enable C2NOW delay to PSTATECTL VID / FID Change Delay - * to P-State Control. - */ - pci_write_config8(devctl, 0xa6, 0x83); - - // return; // FIXME: Fall through some revs have it old way. + return; } /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2008-12-04 15:18:20 UTC (rev 3794) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2008-12-04 23:37:12 UTC (rev 3795) @@ -264,14 +264,10 @@ pci_write_config32(dev, 0xbc, (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000)); - /* Enable SATA LED, VR timer = 100us, VR timer should be fixed. */ - pci_write_config8(dev, 0xe5, 0x69); - /* * REQ5 as PCI request input - should be together with INTE-INTH. - * Fast VR timer disable - need for LDTSTOP_L signal. */ - pci_write_config8(dev, 0xe4, 0xa5); + pci_write_config8(dev, 0xe4, 0x04); /* Reduce further the STPCLK/LDTSTP signal to 5us. */ pci_write_config8(dev, 0xec, 0x4);

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Re: [coreboot] qemu dts fixes
by Jordan Crouse 04 Dec '08

04 Dec '08

Myles Watson wrote: > On Mon, Dec 1, 2008 at 1:52 PM, Jordan Crouse <jordan(a)cosmicpenguin.net>wrote: > >> Myles Watson wrote: >> >>> This patch updates qemu. It takes out the bus construct from the dts, >>> adds >>> the dts for ide, isa, and acpi. It changes the default for ide to >>> enabled. >>> It makes it so that only the plugged in cards are dynamic. >>> >>> Since it's harder in emulation to tell if chips are cards or on the >>> mainboard, I may be wrong with the VGA card. Help? >>> >> Excuse my ignorance, but why does it matter? They are on the PCI bus >> regardless of where the logic lives, right? > > > It matters for the expansion ROM. If it's onboard, then coreboot has to > include it in the lar, otherwise it just reads the "card's" ROM. It also > changes the logic of whether or not we set subsytem IDs. So the defining criteria isn't "onboard or cards", its "need a ROM or not" - because not all onboard GPUs require an option ROM in the main system ROM - some can use an attached EEPROM (as do soldered down NICs and other such devices). Its not a huge deal, since I see where you are doing with it - but it might relieve some confusion if we called it "need_optionrom" instead of "on_mainboard". Jordan

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[PATCH] Avoid cross-device renames in build_opt_tbl
by Carl-Daniel Hailfinger 04 Dec '08

04 Dec '08

Aaron Lwe reported that v2 build fails if /tmp and the build directory are on different file systems. That's due to the rename being performed in build_opt_tbl. Renames can't be done across filesystems. I saw that problem in the original patch, but I didn't want to ruin the mood by complaining. Anyway, here is a patch to fix it. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-build_opt_tbl/util/options/build_opt_tbl.c =================================================================== --- LinuxBIOSv2-build_opt_tbl/util/options/build_opt_tbl.c (Revision 3788) +++ LinuxBIOSv2-build_opt_tbl/util/options/build_opt_tbl.c (Arbeitskopie) @@ -11,7 +11,7 @@ #define INPUT_LINE_MAX 256 #define MAX_VALUE_BYTE_LENGTH 64 -#define TMPFILE_TEMPLATE "/tmp/build_opt_tbl_XXXXXX" +#define TMPFILE_TEMPLATE ".XXXXXX" static unsigned char cmos_table[4096]; @@ -215,7 +215,7 @@ char *header=0; FILE *fp; int tmpfile; - char tmpfilename[32]; + char *tmpfilename; struct cmos_option_table *ct; struct cmos_entries *ce; struct cmos_enums *c_enums, *c_enums_start; @@ -485,7 +485,9 @@ /* See if we want to output a C source file */ if(option) { - strcpy(tmpfilename, TMPFILE_TEMPLATE); + tmpfilename = malloc(strlen(option) + strlen(TMPFILE_TEMPLATE) + 1); + strcpy(tmpfilename, option); + strcat(tmpfilename, TMPFILE_TEMPLATE); tmpfile = mkstemp(tmpfilename); if(tmpfile == -1) { perror("Error - Could not create temporary file"); @@ -535,7 +537,9 @@ struct cmos_option_table *hdr; struct lb_record *ptr, *end; - strcpy(tmpfilename, TMPFILE_TEMPLATE); + tmpfilename = malloc(strlen(header) + strlen(TMPFILE_TEMPLATE) + 1); + strcpy(tmpfilename, header); + strcat(tmpfilename, TMPFILE_TEMPLATE); tmpfile = mkstemp(tmpfilename); if(tmpfile == -1) { perror("Error - Could not create temporary file"); -- http://www.hailfinger.org/

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Re: [coreboot] r3789 - trunk/coreboot-v2/util/options
by Carl-Daniel Hailfinger 04 Dec '08

04 Dec '08

On 02.12.2008 13:26, svn(a)coreboot.org wrote: > Author: stepan > Date: 2008-12-02 13:26:17 +0100 (Tue, 02 Dec 2008) > New Revision: 3789 > > Modified: > trunk/coreboot-v2/util/options/build_opt_tbl.c > Log: > build_opt_tbl: > make sure the temporary files are created in the same directory as the > target files so they can be rename()d. This fixes a compilation issue on > machines with the build directory living on another partition than /tmp. > Pretty trivial. > > Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> > Acked-by: Stefan Reinauer <stepan(a)coresystems.de> > This will break if the path is longer than 234 bytes, whereas PATH_MAX on my Linux system is 4096. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 3

[RFC] Here we go... the SLOF biosemu for coreboot-v3
by Pattrick Hueper 04 Dec '08

04 Dec '08

Hi, as mailed earlier, i took the IBM SLOF biosemu code that i wrote for IBM and included it into coreboot-v3. The SLOF code is opensourced under a BSD license at http://www.ibm.com/developerworks/power/pa-slof/ Here is my git repository containing the code: git://patty-server2.hueper.net/coreboot-v3_biosemu This repository is actually a git svn clone of the coreboot svn, with the plain unmodified biosemu copied from SLOF and my integration patches for coreboot-v3 on top of it. (starting with a commit "add .gitignore") I know that the current state is neither very clean nor very nice from a patch point of view... i wanted to create a state where i could stay as close as possible to the original sources while showing the steps needed for coreboot-v3 integration. If i compile this coreboot-v3 code for qemu it initialises a plain unmodified cirrus card in qemu, which was my primary goal. I verified this with a buildrom build with coreinfo as payload, which can use the textmode to display its info. There are some changes to the original x86emu code (adding bswap opcodes, some debugging output, ...) which i needed for other PCI cards initializations (IDE/Ethernet) but i still think they make sense to be added to x86emu. I am not quite sure where i would like to go from here, the code obviously needs some cleanups, and as i said earlier i would love to try to get it working in qemu-ppc since the code is designed to be pretty much architecture independent (some basic functions are needed but should be easy to port... i already ported them to x86/coreboot from ppc/OF) If you would rather see a patch series, i can try to come up with a git format-patch created patch series. Comments very much welcome! Cheers, Patty

3 2

[PATCH] inteltool: i965, i975, ICH8M and Darwin support.
by Stefan Reinauer 04 Dec '08

04 Dec '08

See patch. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Patch to util/inteltool: * Add support for i965, i975, ICH8M * Add support for Darwin OS using DirectIO This does not include additional changes from Lu Zhihe yet, I'll integrate them in the next iteration. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: gpio.c =================================================================== --- gpio.c (revision 3783) +++ gpio.c (working copy) @@ -18,7 +18,6 @@ */ #include <stdio.h> -#include <sys/io.h> #include "inteltool.h" static const io_register_t ich0_gpio_registers[] = { @@ -78,6 +77,26 @@ { 0x3C, 4, "RESERVED" } }; +static const io_register_t ich8_gpio_registers[] = { + { 0x00, 4, "GPIO_USE_SEL" }, + { 0x04, 4, "GP_IO_SEL" }, + { 0x08, 4, "RESERVED" }, + { 0x0c, 4, "GP_LVL" }, + { 0x10, 4, "GPIO_USE_SEL Override (LOW)" }, + { 0x14, 4, "RESERVED" }, + { 0x18, 4, "GPO_BLINK" }, + { 0x1c, 4, "GP_SER_BLINK" }, + { 0x20, 4, "GP_SB_CMDSTS" }, + { 0x24, 4, "GP_SB_DATA" }, + { 0x28, 4, "RESERVED" }, + { 0x2c, 4, "GPI_INV" }, + { 0x30, 4, "GPIO_USE_SEL2" }, + { 0x34, 4, "GP_IO_SEL2" }, + { 0x38, 4, "GP_LVL2" }, + { 0x3C, 4, "GPIO_USE_SEL Override (HIGH)" } +}; + + int print_gpios(struct pci_dev *sb) { int i, size; @@ -87,6 +106,11 @@ printf("\n============= GPIOS =============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_ICH8M: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = ich8_gpio_registers; + size = ARRAY_SIZE(ich8_gpio_registers); + break; case PCI_DEVICE_ID_INTEL_ICH7: case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: Index: inteltool.h =================================================================== --- inteltool.h (revision 3783) +++ inteltool.h (working copy) @@ -18,6 +18,11 @@ */ #include <stdint.h> +#ifndef DARWIN +#include <sys/io.h> +#else +#include <DirectIO/darwinio.h> +#endif #include <pci/pci.h> #define INTELTOOL_VERSION "1.0" @@ -33,17 +38,23 @@ #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 #define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd +#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 #define PCI_DEVICE_ID_INTEL_82845 0x1a30 #define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 +#define PCI_DEVICE_ID_INTEL_PM965 0x2a00 +#define PCI_DEVICE_ID_INTEL_82975X 0x277c #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) +#ifndef DARWIN typedef struct { uint32_t hi, lo; } msr_t; +#endif typedef struct { uint16_t addr; int size; char *name; } io_register_t; -extern int fd_mem; +void *map_physical(unsigned long phys_addr, int len); +void unmap_physical(void *virt_addr, int len); unsigned int cpuid(unsigned int op); int print_intel_core_msrs(void); Index: pcie.c =================================================================== --- pcie.c (revision 3783) +++ pcie.c (working copy) @@ -19,8 +19,6 @@ #include <stdio.h> #include <stdlib.h> -#include <sys/mman.h> - #include "inteltool.h" /* @@ -30,15 +28,20 @@ { int i, size = (4 * 1024); volatile uint8_t *epbar; - uint32_t epbar_phys; + uint64_t epbar_phys; printf("\n============= EPBAR =============\n\n"); switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945P: + case PCI_DEVICE_ID_INTEL_82975X: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; break; + case PCI_DEVICE_ID_INTEL_PM965: + epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; + epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; + break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have EPBAR.\n"); return 1; @@ -47,21 +50,20 @@ return 1; } - epbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) epbar_phys); + epbar = map_physical(epbar_phys, size); - if (epbar == MAP_FAILED) { + if (epbar == NULL) { perror("Error mapping EPBAR"); exit(1); } - printf("EPBAR = 0x%08x (MEM)\n\n", epbar_phys); + printf("EPBAR = 0x%08llx (MEM)\n\n", epbar_phys); for (i = 0; i < size; i += 4) { if (*(uint32_t *)(epbar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i)); } - munmap((void *)epbar, size); + unmap_physical((void *)epbar, size); return 0; } @@ -72,15 +74,20 @@ { int i, size = (4 * 1024); volatile uint8_t *dmibar; - uint32_t dmibar_phys; + uint64_t dmibar_phys; printf("\n============= DMIBAR ============\n\n"); switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945P: + case PCI_DEVICE_ID_INTEL_82975X: dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; + case PCI_DEVICE_ID_INTEL_PM965: + dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; + dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; + break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have DMIBAR.\n"); return 1; @@ -89,21 +96,20 @@ return 1; } - dmibar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) dmibar_phys); + dmibar = map_physical(dmibar_phys, size); - if (dmibar == MAP_FAILED) { + if (dmibar == NULL) { perror("Error mapping DMIBAR"); exit(1); } - printf("DMIBAR = 0x%08x (MEM)\n\n", dmibar_phys); + printf("DMIBAR = 0x%08llx (MEM)\n\n", dmibar_phys); for (i = 0; i < size; i += 4) { if (*(uint32_t *)(dmibar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i)); } - munmap((void *)dmibar, size); + unmap_physical((void *)dmibar, size); return 0; } @@ -112,8 +118,8 @@ */ int print_pciexbar(struct pci_dev *nb) { - uint32_t pciexbar_reg; - uint32_t pciexbar_phys; + uint64_t pciexbar_reg; + uint64_t pciexbar_phys; volatile uint8_t *pciexbar; int max_busses, devbase, i; int bus, dev, fn; @@ -123,8 +129,13 @@ switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945P: + case PCI_DEVICE_ID_INTEL_82975X: pciexbar_reg = pci_read_long(nb, 0x48); break; + case PCI_DEVICE_ID_INTEL_PM965: + pciexbar_reg = pci_read_long(nb, 0x60); + pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; + break; case 0x1234: // Dummy for non-existent functionality printf("Error: This northbrigde does not have PCIEXBAR.\n"); return 1; @@ -140,15 +151,15 @@ switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB - pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + pciexbar_phys = pciexbar_reg & (0xff << 28); max_busses = 256; break; case 1: // 128M - pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + pciexbar_phys = pciexbar_reg & (0x1ff << 27); max_busses = 128; break; case 2: // 64M - pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + pciexbar_phys = pciexbar_reg & (0x3ff << 26); max_busses = 64; break; default: // RSVD @@ -156,12 +167,11 @@ return 1; } - printf("PCIEXBAR: 0x%08x\n", pciexbar_phys); + printf("PCIEXBAR: 0x%08llx\n", pciexbar_phys); - pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ, - MAP_SHARED, fd_mem, (off_t) pciexbar_phys); + pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024)); - if (pciexbar == MAP_FAILED) { + if (pciexbar == NULL) { perror("Error mapping PCIEXBAR"); exit(1); } @@ -194,7 +204,7 @@ } } - munmap((void *)pciexbar, (max_busses * 1024 * 1024)); + unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024)); return 0; } Index: powermgt.c =================================================================== --- powermgt.c (revision 3783) +++ powermgt.c (working copy) @@ -19,8 +19,6 @@ */ #include <stdio.h> -#include <sys/io.h> - #include "inteltool.h" int print_pmbase(struct pci_dev *sb) @@ -35,6 +33,7 @@ case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: + case PCI_DEVICE_ID_INTEL_ICH8M: pmbase = pci_read_word(sb, 0x40) & 0xfffc; break; case 0x1234: // Dummy for non-existent functionality @@ -48,6 +47,13 @@ printf("PMBASE = 0x%04x (IO)\n\n", pmbase); for (i = 0; i < size; i += 4) { +#ifdef DARWIN + if (i==0x14) { + /* Reading this register will hang a macbook pro */ + printf("pmbase+0x%04x: 0xXXXXXXXX\n", i); + continue; + } +#endif printf("pmbase+0x%04x: 0x%08x\n", i, inl(pmbase + i)); } Index: cpu.c =================================================================== --- cpu.c (revision 3783) +++ cpu.c (working copy) @@ -33,13 +33,18 @@ unsigned int ret; unsigned int dummy2, dummy3, dummy4; asm volatile ( - "cpuid" - : "=a" (ret), "=b" (dummy2), "=c" (dummy3), "=d" (dummy4) + "pushl %%ebx \n" + "cpuid \n" + "movl %%ebx, %1 \n" + "popl %%ebx \n" + : "=a" (ret), "=r" (dummy2), "=c" (dummy3), "=d" (dummy4) : "a" (op) + : "cc" ); return ret; } +#ifndef DARWIN int msr_readerror = 0; msr_t rdmsr(int addr) @@ -72,6 +77,7 @@ return msr; } +#endif int print_intel_core_msrs(void) { @@ -273,12 +279,14 @@ return -1; } +#ifndef DARWIN fd_msr = open("/dev/cpu/0/msr", O_RDWR); if (fd_msr < 0) { perror("Error while opening /dev/cpu/0/msr"); printf("Did you run 'modprobe msr'?\n"); return -1; } +#endif printf("\n===================== SHARED MSRs (All Cores) =====================\n"); @@ -292,6 +300,7 @@ close(fd_msr); for (core = 0; core < 8; core++) { +#ifndef DARWIN char msrfilename[64]; memset(msrfilename, 0, 64); sprintf(msrfilename, "/dev/cpu/%d/msr", core); @@ -303,7 +312,7 @@ */ if (fd_msr < 0) break; - +#endif printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core); for (i = 0; i < cpu->num_per_core_msrs; i++) { @@ -312,13 +321,15 @@ cpu->per_core_msrs[i].number, msr.hi, msr.lo, cpu->per_core_msrs[i].name); } - +#ifndef DARWIN close(fd_msr); +#endif } +#ifndef DARWIN if (msr_readerror) printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n"); - +#endif return 0; } Index: rootcmplx.c =================================================================== --- rootcmplx.c (revision 3783) +++ rootcmplx.c (working copy) @@ -18,18 +18,8 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include <errno.h> -#include <fcntl.h> -#include <unistd.h> #include <stdio.h> -#include <string.h> #include <stdlib.h> -#include <stdint.h> -#include <getopt.h> -#include <sys/mman.h> -#include <sys/io.h> -#include <pci/pci.h> - #include "inteltool.h" int print_rcba(struct pci_dev *sb) @@ -45,6 +35,7 @@ case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: + case PCI_DEVICE_ID_INTEL_ICH8M: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_ICH: @@ -58,10 +49,9 @@ return 1; } - rcba = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) rcba_phys); + rcba = map_physical(rcba_phys, size); - if (rcba == MAP_FAILED) { + if (rcba == NULL) { perror("Error mapping RCBA"); exit(1); } @@ -73,7 +63,7 @@ printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(rcba + i)); } - munmap((void *)rcba, size); + unmap_physical((void *)rcba, size); return 0; } Index: memory.c =================================================================== --- memory.c (revision 3783) +++ memory.c (working copy) @@ -20,8 +20,6 @@ #include <stdio.h> #include <stdlib.h> -#include <sys/mman.h> - #include "inteltool.h" /* @@ -31,15 +29,20 @@ { int i, size = (16 * 1024); volatile uint8_t *mchbar; - uint32_t mchbar_phys; + uint64_t mchbar_phys; printf("\n============= MCHBAR ============\n\n"); switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945P: + case PCI_DEVICE_ID_INTEL_82975X: mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; break; + case PCI_DEVICE_ID_INTEL_PM965: + mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have MCHBAR.\n"); return 1; @@ -48,22 +51,21 @@ return 1; } - mchbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) mchbar_phys); + mchbar = map_physical(mchbar_phys, size); - if (mchbar == MAP_FAILED) { + if (mchbar == NULL) { perror("Error mapping MCHBAR"); exit(1); } - printf("MCHBAR = 0x%08x (MEM)\n\n", mchbar_phys); + printf("MCHBAR = 0x%08llx (MEM)\n\n", mchbar_phys); for (i = 0; i < size; i += 4) { if (*(uint32_t *)(mchbar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i)); } - munmap((void *)mchbar, size); + unmap_physical((void *)mchbar, size); return 0; } Index: inteltool.c =================================================================== --- inteltool.c (revision 3783) +++ inteltool.c (working copy) @@ -21,9 +21,8 @@ #include <stdio.h> #include <stdlib.h> #include <getopt.h> -#include <sys/io.h> #include <fcntl.h> - +#include <sys/mman.h> #include "inteltool.h" static const struct { @@ -33,6 +32,9 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }, @@ -44,8 +46,30 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" } }; -int fd_mem; +#ifndef DARWIN +static int fd_mem; +void *map_physical(unsigned long phys_addr, int len) +{ + void *virt_addr; + + virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED, + fd_mem, (off_t) phys_addr); + + if (virt_addr == MAP_FAILED) { + printf("Error mapping physical memory 0x%08x[0x%x]\n", phys_addr, len); + return NULL; + } + + return virt_addr; +} + +void unmap_physical(void *virt_addr, int len) +{ + munmap((void *)rcba, size); +} +#endif + void print_version(void) { printf("inteltool v%s -- ", INTELTOOL_VERSION); @@ -164,10 +188,12 @@ exit(1); } +#ifndef DARWIN if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) { perror("Can not open /dev/mem"); exit(1); } +#endif pacc = pci_alloc(); pci_init(pacc); Index: Makefile =================================================================== --- Makefile (revision 3783) +++ Makefile (working copy) @@ -29,6 +29,13 @@ OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o +OS_ARCH = $(shell uname) +ifeq ($(OS_ARCH), Darwin) +CFLAGS += -DDARWIN -I/usr/local/include +LDFLAGS = -framework IOKit -framework DirectIO -L/usr/local/lib -lpci -lz +# OBJS += darwinio.o +endif + all: pciutils dep $(PROGRAM) $(PROGRAM): $(OBJS) @@ -41,10 +48,10 @@ rm -f .dependencies dep: - @$(CC) -MM *.c > .dependencies + @$(CC) $(CFLAGS) -MM *.c > .dependencies pciutils: - @echo; echo -n "Checking for pciutils and zlib... " + @echo; /bin/echo -n "Checking for pciutils and zlib... " @$(shell ( echo "#include <pci/pci.h>"; \ echo "struct pci_access *pacc;"; \ echo "int main(int argc, char **argv)"; \ @@ -54,12 +61,12 @@ echo "Please install pciutils-devel and zlib-devel."; \ echo "See README for more information."; echo; \ rm -f .test.c .test; exit 1) - @rm -f .test.c .test + @rm -rf .test.c .test .test.dSYM install: $(PROGRAM) - $(INSTALL) $(PROGRAM) $(PREFIX)/sbin - mkdir -p $(PREFIX)/share/man/man8 - $(INSTALL) $(PROGRAM).8 $(PREFIX)/share/man/man8 + $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin + mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8 + $(INSTALL) $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 .PHONY: all clean distclean dep pciutils

5 11

r3794 - trunk/util/inteltool
by svn＠coreboot.org 04 Dec '08

04 Dec '08

Author: stepan Date: 2008-12-04 16:18:20 +0100 (Thu, 04 Dec 2008) New Revision: 3794 Modified: trunk/util/inteltool/Makefile trunk/util/inteltool/cpu.c trunk/util/inteltool/gpio.c trunk/util/inteltool/inteltool.c trunk/util/inteltool/inteltool.h trunk/util/inteltool/memory.c trunk/util/inteltool/pcie.c trunk/util/inteltool/powermgt.c trunk/util/inteltool/rootcmplx.c Log: Patch to util/inteltool: * PMBASE dumping now knows the registers. * Add support for i965, i975, ICH8M * Add support for Darwin OS using DirectIO Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/inteltool/Makefile =================================================================== --- trunk/util/inteltool/Makefile 2008-12-04 00:58:10 UTC (rev 3793) +++ trunk/util/inteltool/Makefile 2008-12-04 15:18:20 UTC (rev 3794) @@ -29,6 +29,13 @@ OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o +OS_ARCH = $(shell uname) +ifeq ($(OS_ARCH), Darwin) +CFLAGS += -DDARWIN -I/usr/local/include +LDFLAGS = -framework IOKit -framework DirectIO -L/usr/local/lib -lpci -lz +# OBJS += darwinio.o +endif + all: pciutils dep $(PROGRAM) $(PROGRAM): $(OBJS) @@ -41,25 +48,25 @@ rm -f .dependencies dep: - @$(CC) -MM *.c > .dependencies + @$(CC) $(CFLAGS) -MM *.c > .dependencies pciutils: - @echo; echo -n "Checking for pciutils and zlib... " - @$(shell ( echo "#include <pci/pci.h>"; \ - echo "struct pci_access *pacc;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c ) - @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \ - echo "found." || ( echo "not found."; echo; \ - echo "Please install pciutils-devel and zlib-devel."; \ - echo "See README for more information."; echo; \ + @printf "\nChecking for pciutils and zlib... " + @$(shell ( printf "#include <pci/pci.h>\n"; \ + printf "struct pci_access *pacc;\n"; \ + printf "int main(int argc, char **argv)\n"; \ + printf "{ pacc = pci_alloc(); return 0; }\n"; ) > .test.c ) + @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \ + printf "found.\n" || ( printf "not found.\n\n"; \ + printf "Please install pciutils-devel and zlib-devel.\n"; \ + printf "See README for more information.\n\n"; \ rm -f .test.c .test; exit 1) - @rm -f .test.c .test + @rm -rf .test.c .test .test.dSYM install: $(PROGRAM) - $(INSTALL) $(PROGRAM) $(PREFIX)/sbin - mkdir -p $(PREFIX)/share/man/man8 - $(INSTALL) $(PROGRAM).8 $(PREFIX)/share/man/man8 + $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin + mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8 + $(INSTALL) $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 .PHONY: all clean distclean dep pciutils Modified: trunk/util/inteltool/cpu.c =================================================================== --- trunk/util/inteltool/cpu.c 2008-12-04 00:58:10 UTC (rev 3793) +++ trunk/util/inteltool/cpu.c 2008-12-04 15:18:20 UTC (rev 3794) @@ -33,13 +33,18 @@ unsigned int ret; unsigned int dummy2, dummy3, dummy4; asm volatile ( - "cpuid" - : "=a" (ret), "=b" (dummy2), "=c" (dummy3), "=d" (dummy4) + "pushl %%ebx \n" + "cpuid \n" + "movl %%ebx, %1 \n" + "popl %%ebx \n" + : "=a" (ret), "=r" (dummy2), "=c" (dummy3), "=d" (dummy4) : "a" (op) + : "cc" ); return ret; } +#ifndef DARWIN int msr_readerror = 0; msr_t rdmsr(int addr) @@ -72,6 +77,7 @@ return msr; } +#endif int print_intel_core_msrs(void) { @@ -273,12 +279,14 @@ return -1; } +#ifndef DARWIN fd_msr = open("/dev/cpu/0/msr", O_RDWR); if (fd_msr < 0) { perror("Error while opening /dev/cpu/0/msr"); printf("Did you run 'modprobe msr'?\n"); return -1; } +#endif printf("\n===================== SHARED MSRs (All Cores) =====================\n"); @@ -292,6 +300,7 @@ close(fd_msr); for (core = 0; core < 8; core++) { +#ifndef DARWIN char msrfilename[64]; memset(msrfilename, 0, 64); sprintf(msrfilename, "/dev/cpu/%d/msr", core); @@ -303,7 +312,7 @@ */ if (fd_msr < 0) break; - +#endif printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core); for (i = 0; i < cpu->num_per_core_msrs; i++) { @@ -312,13 +321,15 @@ cpu->per_core_msrs[i].number, msr.hi, msr.lo, cpu->per_core_msrs[i].name); } - +#ifndef DARWIN close(fd_msr); +#endif } +#ifndef DARWIN if (msr_readerror) printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n"); - +#endif return 0; } Modified: trunk/util/inteltool/gpio.c =================================================================== --- trunk/util/inteltool/gpio.c 2008-12-04 00:58:10 UTC (rev 3793) +++ trunk/util/inteltool/gpio.c 2008-12-04 15:18:20 UTC (rev 3794) @@ -18,7 +18,6 @@ */ #include <stdio.h> -#include <sys/io.h> #include "inteltool.h" static const io_register_t ich0_gpio_registers[] = { @@ -78,6 +77,26 @@ { 0x3C, 4, "RESERVED" } }; +static const io_register_t ich8_gpio_registers[] = { + { 0x00, 4, "GPIO_USE_SEL" }, + { 0x04, 4, "GP_IO_SEL" }, + { 0x08, 4, "RESERVED" }, + { 0x0c, 4, "GP_LVL" }, + { 0x10, 4, "GPIO_USE_SEL Override (LOW)" }, + { 0x14, 4, "RESERVED" }, + { 0x18, 4, "GPO_BLINK" }, + { 0x1c, 4, "GP_SER_BLINK" }, + { 0x20, 4, "GP_SB_CMDSTS" }, + { 0x24, 4, "GP_SB_DATA" }, + { 0x28, 4, "RESERVED" }, + { 0x2c, 4, "GPI_INV" }, + { 0x30, 4, "GPIO_USE_SEL2" }, + { 0x34, 4, "GP_IO_SEL2" }, + { 0x38, 4, "GP_LVL2" }, + { 0x3C, 4, "GPIO_USE_SEL Override (HIGH)" } +}; + + int print_gpios(struct pci_dev *sb) { int i, size; @@ -87,6 +106,11 @@ printf("\n============= GPIOS =============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_ICH8M: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = ich8_gpio_registers; + size = ARRAY_SIZE(ich8_gpio_registers); + break; case PCI_DEVICE_ID_INTEL_ICH7: case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: Modified: trunk/util/inteltool/inteltool.c =================================================================== --- trunk/util/inteltool/inteltool.c 2008-12-04 00:58:10 UTC (rev 3793) +++ trunk/util/inteltool/inteltool.c 2008-12-04 15:18:20 UTC (rev 3794) @@ -21,9 +21,8 @@ #include <stdio.h> #include <stdlib.h> #include <getopt.h> -#include <sys/io.h> #include <fcntl.h> - +#include <sys/mman.h> #include "inteltool.h" static const struct { @@ -33,6 +32,9 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }, @@ -44,8 +46,30 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" } }; -int fd_mem; +#ifndef DARWIN +static int fd_mem; +void *map_physical(unsigned long phys_addr, int len) +{ + void *virt_addr; + + virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED, + fd_mem, (off_t) phys_addr); + + if (virt_addr == MAP_FAILED) { + printf("Error mapping physical memory 0x%08x[0x%x]\n", phys_addr, len); + return NULL; + } + + return virt_addr; +} + +void unmap_physical(void *virt_addr, int len) +{ + munmap(virt_addr, len); +} +#endif + void print_version(void) { printf("inteltool v%s -- ", INTELTOOL_VERSION); @@ -164,10 +188,12 @@ exit(1); } +#ifndef DARWIN if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) { perror("Can not open /dev/mem"); exit(1); } +#endif pacc = pci_alloc(); pci_init(pacc); Modified: trunk/util/inteltool/inteltool.h =================================================================== --- trunk/util/inteltool/inteltool.h 2008-12-04 00:58:10 UTC (rev 3793) +++ trunk/util/inteltool/inteltool.h 2008-12-04 15:18:20 UTC (rev 3794) @@ -18,6 +18,14 @@ */ #include <stdint.h> +#ifndef DARWIN +#include <sys/io.h> +#else +/* DirectIO is available here: + * http://www.coresystems.de/en/directio + */ +#include <DirectIO/darwinio.h> +#endif #include <pci/pci.h> #define INTELTOOL_VERSION "1.0" @@ -33,17 +41,23 @@ #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 #define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd +#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 #define PCI_DEVICE_ID_INTEL_82845 0x1a30 #define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 +#define PCI_DEVICE_ID_INTEL_PM965 0x2a00 +#define PCI_DEVICE_ID_INTEL_82975X 0x277c #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) +#ifndef DARWIN typedef struct { uint32_t hi, lo; } msr_t; +#endif typedef struct { uint16_t addr; int size; char *name; } io_register_t; -extern int fd_mem; +void *map_physical(unsigned long phys_addr, int len); +void unmap_physical(void *virt_addr, int len); unsigned int cpuid(unsigned int op); int print_intel_core_msrs(void); Modified: trunk/util/inteltool/memory.c =================================================================== --- trunk/util/inteltool/memory.c 2008-12-04 00:58:10 UTC (rev 3793) +++ trunk/util/inteltool/memory.c 2008-12-04 15:18:20 UTC (rev 3794) @@ -20,8 +20,6 @@ #include <stdio.h> #include <stdlib.h> -#include <sys/mman.h> - #include "inteltool.h" /* @@ -31,15 +29,20 @@ { int i, size = (16 * 1024); volatile uint8_t *mchbar; - uint32_t mchbar_phys; + uint64_t mchbar_phys; printf("\n============= MCHBAR ============\n\n"); switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945P: + case PCI_DEVICE_ID_INTEL_82975X: mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; break; + case PCI_DEVICE_ID_INTEL_PM965: + mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have MCHBAR.\n"); return 1; @@ -48,22 +51,21 @@ return 1; } - mchbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) mchbar_phys); + mchbar = map_physical(mchbar_phys, size); - if (mchbar == MAP_FAILED) { + if (mchbar == NULL) { perror("Error mapping MCHBAR"); exit(1); } - printf("MCHBAR = 0x%08x (MEM)\n\n", mchbar_phys); + printf("MCHBAR = 0x%08llx (MEM)\n\n", mchbar_phys); for (i = 0; i < size; i += 4) { if (*(uint32_t *)(mchbar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i)); } - munmap((void *)mchbar, size); + unmap_physical((void *)mchbar, size); return 0; } Modified: trunk/util/inteltool/pcie.c =================================================================== --- trunk/util/inteltool/pcie.c 2008-12-04 00:58:10 UTC (rev 3793) +++ trunk/util/inteltool/pcie.c 2008-12-04 15:18:20 UTC (rev 3794) @@ -19,8 +19,6 @@ #include <stdio.h> #include <stdlib.h> -#include <sys/mman.h> - #include "inteltool.h" /* @@ -30,15 +28,20 @@ { int i, size = (4 * 1024); volatile uint8_t *epbar; - uint32_t epbar_phys; + uint64_t epbar_phys; printf("\n============= EPBAR =============\n\n"); switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945P: + case PCI_DEVICE_ID_INTEL_82975X: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; break; + case PCI_DEVICE_ID_INTEL_PM965: + epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; + epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; + break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have EPBAR.\n"); return 1; @@ -47,21 +50,20 @@ return 1; } - epbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) epbar_phys); + epbar = map_physical(epbar_phys, size); - if (epbar == MAP_FAILED) { + if (epbar == NULL) { perror("Error mapping EPBAR"); exit(1); } - printf("EPBAR = 0x%08x (MEM)\n\n", epbar_phys); + printf("EPBAR = 0x%08llx (MEM)\n\n", epbar_phys); for (i = 0; i < size; i += 4) { if (*(uint32_t *)(epbar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i)); } - munmap((void *)epbar, size); + unmap_physical((void *)epbar, size); return 0; } @@ -72,15 +74,20 @@ { int i, size = (4 * 1024); volatile uint8_t *dmibar; - uint32_t dmibar_phys; + uint64_t dmibar_phys; printf("\n============= DMIBAR ============\n\n"); switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945P: + case PCI_DEVICE_ID_INTEL_82975X: dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; + case PCI_DEVICE_ID_INTEL_PM965: + dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; + dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; + break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have DMIBAR.\n"); return 1; @@ -89,21 +96,20 @@ return 1; } - dmibar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) dmibar_phys); + dmibar = map_physical(dmibar_phys, size); - if (dmibar == MAP_FAILED) { + if (dmibar == NULL) { perror("Error mapping DMIBAR"); exit(1); } - printf("DMIBAR = 0x%08x (MEM)\n\n", dmibar_phys); + printf("DMIBAR = 0x%08llx (MEM)\n\n", dmibar_phys); for (i = 0; i < size; i += 4) { if (*(uint32_t *)(dmibar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i)); } - munmap((void *)dmibar, size); + unmap_physical((void *)dmibar, size); return 0; } @@ -112,8 +118,8 @@ */ int print_pciexbar(struct pci_dev *nb) { - uint32_t pciexbar_reg; - uint32_t pciexbar_phys; + uint64_t pciexbar_reg; + uint64_t pciexbar_phys; volatile uint8_t *pciexbar; int max_busses, devbase, i; int bus, dev, fn; @@ -123,8 +129,13 @@ switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945P: + case PCI_DEVICE_ID_INTEL_82975X: pciexbar_reg = pci_read_long(nb, 0x48); break; + case PCI_DEVICE_ID_INTEL_PM965: + pciexbar_reg = pci_read_long(nb, 0x60); + pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; + break; case 0x1234: // Dummy for non-existent functionality printf("Error: This northbrigde does not have PCIEXBAR.\n"); return 1; @@ -140,15 +151,15 @@ switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB - pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + pciexbar_phys = pciexbar_reg & (0xff << 28); max_busses = 256; break; case 1: // 128M - pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + pciexbar_phys = pciexbar_reg & (0x1ff << 27); max_busses = 128; break; case 2: // 64M - pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + pciexbar_phys = pciexbar_reg & (0x3ff << 26); max_busses = 64; break; default: // RSVD @@ -156,12 +167,11 @@ return 1; } - printf("PCIEXBAR: 0x%08x\n", pciexbar_phys); + printf("PCIEXBAR: 0x%08llx\n", pciexbar_phys); - pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ, - MAP_SHARED, fd_mem, (off_t) pciexbar_phys); + pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024)); - if (pciexbar == MAP_FAILED) { + if (pciexbar == NULL) { perror("Error mapping PCIEXBAR"); exit(1); } @@ -194,7 +204,7 @@ } } - munmap((void *)pciexbar, (max_busses * 1024 * 1024)); + unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024)); return 0; } Modified: trunk/util/inteltool/powermgt.c =================================================================== --- trunk/util/inteltool/powermgt.c 2008-12-04 00:58:10 UTC (rev 3793) +++ trunk/util/inteltool/powermgt.c 2008-12-04 15:18:20 UTC (rev 3794) @@ -19,14 +19,137 @@ */ #include <stdio.h> -#include <sys/io.h> - #include "inteltool.h" +static const io_register_t ich7_pm_registers[] = { + { 0x00, 2, "PM1_STS" }, + { 0x02, 2, "PM1_EN" }, + { 0x04, 4, "PM1_CNT" }, + { 0x08, 4, "PM1_TMR" }, + { 0x0c, 4, "RESERVED" }, + { 0x10, 4, "PROC_CNT" }, +#if DANGEROUS_REGISTERS + /* These registers return 0 on read, but reading them may cause + * the system to enter C2/C3/C4 state, which might hang the system. + */ + { 0x14, 1, "LV2 (Mobile/Ultra Mobile)" }, + { 0x15, 1, "LV3 (Mobile/Ultra Mobile)" }, + { 0x16, 1, "LV4 (Mobile/Ultra Mobile)" }, +#endif + { 0x17, 1, "RESERVED" }, + { 0x18, 4, "RESERVED" }, + { 0x1c, 4, "RESERVED" }, + { 0x20, 1, "PM2_CNT (Mobile/Ultra Mobile)" }, + { 0x21, 1, "RESERVED" }, + { 0x22, 2, "RESERVED" }, + { 0x24, 4, "RESERVED" }, + { 0x28, 4, "GPE0_STS" }, + { 0x2C, 4, "GPE0_EN" }, + { 0x30, 4, "SMI_EN" }, + { 0x34, 4, "SMI_STS" }, + { 0x38, 2, "ALT_GP_SMI_EN" }, + { 0x3a, 2, "ALT_GP_SMI_STS" }, + { 0x3c, 4, "RESERVED" }, + { 0x40, 2, "RESERVED" }, + { 0x42, 1, "GPE_CNTL" }, + { 0x43, 1, "RESERVED" }, + { 0x44, 2, "DEVACT_STS" }, + { 0x46, 2, "RESERVED" }, + { 0x48, 4, "RESERVED" }, + { 0x4c, 4, "RESERVED" }, + { 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" }, + { 0x51, 1, "RESERVED" }, + { 0x52, 2, "RESERVED" }, + { 0x54, 4, "C3_RES (Mobile/Ultra Mobile)" }, + { 0x58, 4, "RESERVED" }, + { 0x5c, 4, "RESERVED" }, + /* Here start the TCO registers */ + { 0x60, 2, "TCO_RLD" }, + { 0x62, 1, "TCO_DAT_IN" }, + { 0x63, 1, "TCO_DAT_OUT" }, + { 0x64, 2, "TCO1_STS" }, + { 0x66, 2, "TCO2_STS" }, + { 0x68, 2, "TCO1_CNT" }, + { 0x6a, 2, "TCO2_CNT" }, + { 0x6c, 2, "TCO_MESSAGE" }, + { 0x6e, 1, "TCO_WDCNT" }, + { 0x6f, 1, "RESERVED" }, + { 0x70, 1, "SW_IRQ_GEN" }, + { 0x71, 1, "RESERVED" }, + { 0x72, 2, "TCO_TMR" }, + { 0x74, 4, "RESERVED" }, + { 0x78, 4, "RESERVED" }, + { 0x7c, 4, "RESERVED" }, +}; + +static const io_register_t ich8_pm_registers[] = { + { 0x00, 2, "PM1_STS" }, + { 0x02, 2, "PM1_EN" }, + { 0x04, 4, "PM1_CNT" }, + { 0x08, 4, "PM1_TMR" }, + { 0x0c, 4, "RESERVED" }, + { 0x10, 4, "PROC_CNT" }, +#if DANGEROUS_REGISTERS + /* These registers return 0 on read, but reading them may cause + * the system to enter Cx states, which might hang the system. + */ + { 0x14, 1, "LV2 (Mobile)" }, + { 0x15, 1, "LV3 (Mobile)" }, + { 0x16, 1, "LV4 (Mobile)" }, + { 0x17, 1, "LV5 (Mobile)" }, + { 0x18, 1, "LV6 (Mobile)" }, +#endif + { 0x19, 1, "RESERVED" }, + { 0x1a, 2, "RESERVED" }, + { 0x1c, 4, "RESERVED" }, + { 0x20, 1, "PM2_CNT (Mobile)" }, + { 0x21, 1, "RESERVED" }, + { 0x22, 2, "RESERVED" }, + { 0x24, 4, "RESERVED" }, + { 0x28, 4, "GPE0_STS" }, + { 0x2C, 4, "GPE0_EN" }, + { 0x30, 4, "SMI_EN" }, + { 0x34, 4, "SMI_STS" }, + { 0x38, 2, "ALT_GP_SMI_EN" }, + { 0x3a, 2, "ALT_GP_SMI_STS" }, + { 0x3c, 4, "RESERVED" }, + { 0x40, 2, "RESERVED" }, + { 0x42, 1, "GPE_CNTL" }, + { 0x43, 1, "RESERVED" }, + { 0x44, 2, "DEVACT_STS" }, + { 0x46, 2, "RESERVED" }, + { 0x48, 4, "RESERVED" }, + { 0x4c, 4, "RESERVED" }, + { 0x50, 1, "SS_CNT (Mobile)" }, + { 0x51, 1, "RESERVED" }, + { 0x52, 2, "RESERVED" }, + { 0x54, 4, "C3_RES (Mobile)" }, + { 0x58, 4, "C5_RES (Mobile)" }, + { 0x5c, 4, "RESERVED" }, + /* Here start the TCO registers */ + { 0x60, 2, "TCO_RLD" }, + { 0x62, 1, "TCO_DAT_IN" }, + { 0x63, 1, "TCO_DAT_OUT" }, + { 0x64, 2, "TCO1_STS" }, + { 0x66, 2, "TCO2_STS" }, + { 0x68, 2, "TCO1_CNT" }, + { 0x6a, 2, "TCO2_CNT" }, + { 0x6c, 2, "TCO_MESSAGE" }, + { 0x6e, 1, "TCO_WDCNT" }, + { 0x6f, 1, "RESERVED" }, + { 0x70, 1, "SW_IRQ_GEN" }, + { 0x71, 1, "RESERVED" }, + { 0x72, 2, "TCO_TMR" }, + { 0x74, 4, "RESERVED" }, + { 0x78, 4, "RESERVED" }, + { 0x7c, 4, "RESERVED" }, +}; + int print_pmbase(struct pci_dev *sb) { - int i, size = 0x80; + int i, size; uint16_t pmbase; + const io_register_t *pm_registers; printf("\n============= PMBASE ============\n\n"); @@ -36,7 +159,14 @@ case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: pmbase = pci_read_word(sb, 0x40) & 0xfffc; + pm_registers = ich7_pm_registers; + size = ARRAY_SIZE(ich7_pm_registers); break; + case PCI_DEVICE_ID_INTEL_ICH8M: + pmbase = pci_read_word(sb, 0x40) & 0xfffc; + pm_registers = ich8_pm_registers; + size = ARRAY_SIZE(ich8_pm_registers); + break; case 0x1234: // Dummy for non-existent functionality printf("This southbridge does not have PMBASE.\n"); return 1; @@ -47,8 +177,27 @@ printf("PMBASE = 0x%04x (IO)\n\n", pmbase); - for (i = 0; i < size; i += 4) { - printf("pmbase+0x%04x: 0x%08x\n", i, inl(pmbase + i)); + for (i = 0; i < size; i++) { + switch (pm_registers[i].size) { + case 4: + printf("pmbase+0x%04x: 0x%08x (%s)\n", + pm_registers[i].addr, + inl(pmbase+pm_registers[i].addr), + pm_registers[i].name); + break; + case 2: + printf("pmbase+0x%04x: 0x%04x (%s)\n", + pm_registers[i].addr, + inw(pmbase+pm_registers[i].addr), + pm_registers[i].name); + break; + case 1: + printf("pmbase+0x%04x: 0x%02x (%s)\n", + pm_registers[i].addr, + inb(pmbase+pm_registers[i].addr), + pm_registers[i].name); + break; + } } return 0; Modified: trunk/util/inteltool/rootcmplx.c =================================================================== --- trunk/util/inteltool/rootcmplx.c 2008-12-04 00:58:10 UTC (rev 3793) +++ trunk/util/inteltool/rootcmplx.c 2008-12-04 15:18:20 UTC (rev 3794) @@ -18,18 +18,8 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include <errno.h> -#include <fcntl.h> -#include <unistd.h> #include <stdio.h> -#include <string.h> #include <stdlib.h> -#include <stdint.h> -#include <getopt.h> -#include <sys/mman.h> -#include <sys/io.h> -#include <pci/pci.h> - #include "inteltool.h" int print_rcba(struct pci_dev *sb) @@ -45,6 +35,7 @@ case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: + case PCI_DEVICE_ID_INTEL_ICH8M: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_ICH: @@ -58,10 +49,9 @@ return 1; } - rcba = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) rcba_phys); + rcba = map_physical(rcba_phys, size); - if (rcba == MAP_FAILED) { + if (rcba == NULL) { perror("Error mapping RCBA"); exit(1); } @@ -73,7 +63,7 @@ printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(rcba + i)); } - munmap((void *)rcba, size); + unmap_physical((void *)rcba, size); return 0; }

1 0

BarCamp Beijing
by Bao, Zheng 04 Dec '08

04 Dec '08

http://us.apachecon.com/c/accn2008/about I am going to do a brief presentation on BarCamp Beijing. Hopefully more people in China will know this project.

3 3

[Fwd: AMD Releases Documentation for AMD SB600 and AMD 690 Chipset source code for Coreboot]
by Rudolf Marek 04 Dec '08

04 Dec '08

Just FYI: AMD helps lower barriers for Open Source Development of AMD based embedded systems Continuing its efforts to support the Open Source Community AMD has announced the release of the public versions of its SB600 documents. With the availability of the SB600 documentation, along with the already available AMD 690 Series chipset and processor documents, Open Source developers are now enabled to develop firmware and drivers for AMD based embedded systems. AMD has also contributed the AMD 690 Series chipset, SB600, and DBM690E platform source code to the coreboot project (formerly know as LinuxBIOS). In the upcoming months, AMD plans to work with the coreboot community to enable AMD 690 chipset based systems to help provide the best possible coreboot experience. "Since our earliest days in the LinuxBIOS project at Los Alamos National Labs, and continuing to its evolution to coreboot, AMD has been unequalled in their support of open source BIOS software; not just in documents, but in code and support." said Dr. Ronald G. Minnich, founder and developer of the coreboot project, and Principle Member of Technical Staff, Sandia National Labs, California. "We are looking forward to our continued work with AMD on the new chipsets." The coreboot project is an Open Source firmware replacement focused on loading the Linux® operating system. Coreboot is an alternative firmware solution for AMD customers and technology partners that require an open and customizable embedded bootloader. AMD and the coreboot community have worked closely together for a number of years to develop coreboot for the AMD Athlon™ processor, AMD Opteron™ processor, AMD Phenom™ processor, and AMD Geode™ processor and the AMD-8000™ Series, AMD 690 Series and AMD CS5536 chipsets. AMD plans to continue supporting coreboot on future embedded silicon and platform releases. In addition to this documentation, AMD embedded has also expanded its AMD 64 processors and chipset Linux support documentation. This includes BIOS, drivers and open processor information which can now be downloaded from AMD.com. AMD continues to collaborate with its customers in providing the resources and support to help enable their customers to market low-power, high-performance solutions. For more information regarding SB600 documentation, AMD 64 processor and chipset Linux support and AMD embedded solutions please see: http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_233… <http://links.mkt426.com/ctt?kn=5&m=2295441&r=MTUxNjMzMDc4MTES1&b=0&j=NjI1NT…> For more information on coreboot please see: http://www.coreboot.org/Welcome_to_coreboot <http://links.mkt426.com/ctt?kn=2&m=2295441&r=MTUxNjMzMDc4MTES1&b=0&j=NjI1NT…>

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coreboot December 2008