coreboot December 2008

coreboot@coreboot.org

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resource allocation part 2
by Myles Watson 01 Dec '08

01 Dec '08

This patch makes specific devices use the updated resource allocation code. The changes necessary are: 1. Remove all calls to compute_allocate_resources. 2. Read children's resources when yours are read. 3. Don't store resources except in phase4_set_resources. northbridge/amd/k8/domain.c: A comment for later cleanup efforts. Change the resource base from 0x400 to 0x1000 to match the granularity. Add the IORESOURCE_BRIDGE flag. Read the resources of the grandchildren. This should disappear when the domain has the children. Update k8_pci_domain_set_resources: 1. remove compute_allocate_resource call 2. Change phase4_assign_resources to phase4_set_resources northbridge/amd/k8/pci.c: Remove calls to compute_allocate_resource. Make the VGA resource remain visible. Stop passing around nodeid so much. Remove unneeded #defines southbridge/amd/amd8132/amd8132_bridge.c: Remove NPUML and NPUMB. Add a warning for bus disabling. Remove bridge_{read|set}_resources (they were there for NPUML) northbridge/intel/i440bxemulation/i440bx.c: Change phase4_assign_resources->phase4_set_resources. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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qemu dts fixes
by Myles Watson 01 Dec '08

01 Dec '08

This patch updates qemu. It takes out the bus construct from the dts, adds the dts for ide, isa, and acpi. It changes the default for ide to enabled. It makes it so that only the plugged in cards are dynamic. Since it's harder in emulation to tell if chips are cards or on the mainboard, I may be wrong with the VGA card. Help? Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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pnp fixes
by Myles Watson 01 Dec '08

01 Dec '08

This patch mostly fixes breakage that I introduced in a previous commit. It also adds the create flag to the pnp_info struct. I think we need it until we figure out how to specify which PNP devices should be created. Some need to be created even if they're disabled. It also changes a !! to a ? 1 : 0 It changes my || to | because I meant |. It puts the table in superio.c back to how it was in v2, so that there will be less pain in porting. It doesn't fix up the other superios, but I will if I get an ack. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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r3787 - trunk/coreboot-v2/src/mainboard/amd/dbm690t
by svn＠coreboot.org 01 Dec '08

01 Dec '08

Author: mjones Date: 2008-12-01 20:52:54 +0100 (Mon, 01 Dec 2008) New Revision: 3787 Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/chip.h trunk/coreboot-v2/src/mainboard/amd/dbm690t/fadt.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/irq_tables.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c Log: Add AMD dbm690t ACPI support. The following ACPI features are supported. 1. S1, S5 sleep and wake up (by power button or PS/2 keyboard/mouse). 2. AMD powernow-k8 driver. 3. Thermal configuration based on ADT7461. 4. IDE timing settings. 5. HPET timer. 6. Interrupt routing based on ACPI table. Signed-off-by: Joe Bao <zheng.bao(a)amd.com> Reviewed-by: Maggie Li <maggie.li(a)amd.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb 2008-12-01 19:49:57 UTC (rev 3786) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb 2008-12-01 19:52:54 UTC (rev 3787) @@ -54,7 +54,7 @@ default XIP_ROM_SIZE=65536 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) -arch i386 end +arch i386 end ## ## Build the objects we have code for in this directory. @@ -65,11 +65,22 @@ #dir /drivers/si/3114 if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if HAVE_PIRQ_TABLE object get_bus_conf.o - object irq_tables.o + object irq_tables.o end +if HAVE_ACPI_TABLES + object acpi_tables.o + object fadt.o + makerule dsdt.c + depends "$(MAINBOARD)/acpi/*.asl" + action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl" + action "mv dsdt.hex dsdt.c" + end + object ./dsdt.o +end + #object reset.o if USE_DCACHE_RAM @@ -78,14 +89,14 @@ makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else makerule ./cache_as_ram_auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -g -dA -fverbose-asm -c -S -o $@" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -g -dA -fverbose-asm -c -S -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -112,7 +123,7 @@ ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -134,7 +145,7 @@ end ### -### This is the early phase of coreboot startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### @@ -165,7 +176,7 @@ end ## -## Include the secondary Configuration files +## Include the secondary Configuration files ## if CONFIG_CHIP_NAME config chip.h @@ -177,7 +188,7 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) #Define vga_rom_address = 0xfff0000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. #Define gfx_dual_slot, 0: single slot, 1: dual slot #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable @@ -193,7 +204,7 @@ end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge + device pci 18.0 on # southbridge chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 @@ -221,13 +232,13 @@ register "gfx_link_width" = "0" end chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 + device pci 12.0 on end # SATA 0x4380 + device pci 13.0 on end # USB 0x4387 + device pci 13.1 on end # USB 0x4388 + device pci 13.2 on end # USB 0x4389 + device pci 13.3 on end # USB 0x438a + device pci 13.4 on end # USB 0x438b + device pci 13.5 on end # USB 2 0x4386 device pci 14.0 on # SM 0x4385 chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end @@ -242,49 +253,51 @@ device i2c 53 on end end end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8712f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e + device pci 14.1 on end # IDE 0x438c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x438d + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8712f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # ACI 0x4382 + device pci 14.6 on end # MCI 0x438e register "ide0_enable" = "1" register "sata0_enable" = "1" register "hda_viddid" = "0x10ec0882" Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2008-12-01 19:49:57 UTC (rev 3786) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2008-12-01 19:52:54 UTC (rev 3787) @@ -130,6 +130,9 @@ ## default HAVE_MP_TABLE=1 +## ACPI tables will be included +default HAVE_ACPI_TABLES=1 + ## ## Build code to export a CMOS option table ## @@ -232,7 +235,7 @@ ### ### Defaults of options that you may want to override in the target config file -### +### ## ## The default compiler @@ -242,7 +245,7 @@ ## ## Disable the gdb stub by default -## +## default CONFIG_GDB_STUB=0 @@ -275,15 +278,15 @@ ## ### Select the coreboot loglevel ## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details ## Request this level of debugging output default DEFAULT_CONSOLE_LOGLEVEL=8 Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c 2008-12-01 19:49:57 UTC (rev 3786) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c 2008-12-01 19:52:54 UTC (rev 3787) @@ -163,6 +163,7 @@ msr_t msr; struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } @@ -203,7 +204,7 @@ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); - // show final fid and vid + /* show final fid and vid */ msr=rdmsr(0xc0010042); printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/chip.h 2008-12-01 19:49:57 UTC (rev 3786) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/chip.h 2008-12-01 19:52:54 UTC (rev 3787) @@ -16,11 +16,11 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + extern struct chip_operations mainboard_amd_dbm690t_ops; -struct mainboard_amd_dbm690t_config +struct mainboard_amd_dbm690t_config { - unsigned long uma_size; /* How many UMA should be used in memory for TOP. */ + u32 uma_size; /* How many UMA should be used in memory for TOP. */ }; Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/fadt.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/fadt.c 2008-12-01 19:49:57 UTC (rev 3786) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/fadt.c 2008-12-01 19:52:54 UTC (rev 3787) @@ -1,96 +1,199 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include <string.h> -#include <console/console.h> -#include <arch/acpi.h> - - - -/** - * Create the Fixed ACPI Description Tables (FADT) for this board. - The FADT defines various fixed hardware ACPI information vital to an ACPI-compatible - OS, such as the base address for the following hardware registers blocks: - PM1a_EVT_BLK, PM1b_EVT_BLK, PM1a_CNT_BLK, PM1b_CNT_BLK, - PM2_CNT_BLK, PM_TMR_BLK, GPE0_BLK and GPE1_BLK. - The FADT also has a pointer to the DSDT that contains the Differentiated Definition Block, - which in turn provides variable information to an ACPI-compatible OS concerning the base - system design. - - Not all blocks are necessary usualy only PM1a, PMTMR and GPE0 are used. - */ -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header=&(fadt->header); - - printk_debug("pm_base: 0x%04x\n", pm_base); - - memset((void *)fadt,0,sizeof(acpi_fadt_t)); - - /* Prepare the header */ - memcpy(header->signature,"FACP",4); - header->length = 244; - header->revision = 1; - memcpy(header->oem_id,OEM_ID,6); - memcpy(header->oem_table_id,"LXBACPI ",8); - memcpy(header->asl_compiler_id,ASLC,4); - header->asl_compiler_revision=0; - - - fadt->firmware_ctrl=(u32)facs; - fadt->dsdt= (u32)dsdt; - - /* - 0: unspecified - 1: desktop - 2: mobile - 3: workstation - 4: enterprise server - */ - fadt->preferred_pm_profile=0x01; - - /* - System vector the SCI interrupt is wired to in 8259 mode. - On systems that do not contain the 8259, this field contains the Global - System interrupt number of the SCI interrupt. OSPM is required to treat - the ACPI SCI interrupt as a sharable, level, active low interrupt. - SB600 BDG 4.1 - */ - fadt->sci_int=4; - - /* - System port address of the SMI Command Port. During ACPI OS initialization, - OSPM can determine that the ACPI hardware registers are owned by SMI (by way - of the SCI_EN bit), in which case the ACPI OS issues the ACPI_ENABLE command - to the SMI_CMD port. The SCI_EN bit effectively tracks the ownership of the - ACPI hardware registers. OSPM issues commands to the SMI_CMD port - synchronously from the boot processor. - This filed is reserved and must be zero on system that does not support - System Management mode. - */ - fadt->smi_cmd = 0; - - /*Those two fields are reserved and must be zero on systems that do not - support Legacy Mode.*/ - fadt->acpi_enable = 0; - fadt->acpi_disable = 0; - - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x0; - -} +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/io.h> + +/*extern*/ u16 pm_base = 0x800; +/* pm_base should be set in sb acpi */ +/* pm_base should be got from bar2 of rs690. Here I compact ACPI + * registers into 32 bytes limit. + * */ + +#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */ +#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */ +#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */ +#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */ +#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */ +#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */ + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + pm_base &= 0xFFFF; + printk_debug("pm_base: 0x%04x\n", pm_base); + + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF); + pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8); + pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF); + pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8); + pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF); + pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8); + pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); + pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); + + /* CpuControl is in \_PR.CPU0, 6 bytes */ + pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); + pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); + + pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */ + pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */ + + pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF); + pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8); + + pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses + * the contents of the PM registers at + * index 20-2B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn*/ + pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ + + fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK; + fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; + fadt->gpe0_blk = ACPI_GPE0_BLK; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); +} Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c 2008-12-01 19:49:57 UTC (rev 3786) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c 2008-12-01 19:52:54 UTC (rev 3787) @@ -29,20 +29,20 @@ #include <cpu/amd/amdk8_sysconf.h> -/* Global variables for MB layouts and these will be shared by irqtable mptable +/* Global variables for MB layouts and these will be shared by irqtable mptable * and acpi_tables busnum is default. */ u8 bus_isa; u8 bus_rs690[8]; u8 bus_sb600[2]; -unsigned long apicid_sb600; +u32 apicid_sb600; /* * Here you only need to set value in pci1234 for HT-IO that could be installed or not * You may need to preset pci1234 for HTIO board, * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */ -unsigned long pci1234x[] = { +u32 pci1234x[] = { 0x0000ff0, }; @@ -50,22 +50,22 @@ * HT Chain device num, actually it is unit id base of every ht device in chain, * assume every chain only have 4 ht device at most */ -unsigned long hcdnx[] = { +u32 hcdnx[] = { 0x20202020, }; -unsigned long bus_type[256]; +u32 bus_type[256]; -unsigned long sbdn_rs690; -unsigned long sbdn_sb600; +u32 sbdn_rs690; +u32 sbdn_sb600; extern void get_sblk_pci1234(void); -static unsigned long get_bus_conf_done = 0; +static u32 get_bus_conf_done = 0; void get_bus_conf(void) { - unsigned long apicid_base; + u32 apicid_base; device_t dev; int i, j; Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/irq_tables.c 2008-12-01 19:49:57 UTC (rev 3786) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/irq_tables.c 2008-12-01 19:52:54 UTC (rev 3787) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2008-12-01 19:49:57 UTC (rev 3786) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2008-12-01 19:52:54 UTC (rev 3787) @@ -19,12 +19,25 @@ #include <console/console.h> #include <device/device.h> +#include <device/pci.h> #include <arch/io.h> #include <boot/coreboot_tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> +#include <device/pci_def.h> #include "chip.h" +#define ADT7461_ADDRESS 0x4C +#define SMBUS_IO_BASE 0x1000 + +extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); +extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, + u8 val); +#define ADT7461_read_byte(address) \ + do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) +#define ADT7461_write_byte(address, val) \ + do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) + /******************************************************** * dbm690t uses a BCM5789 as on-board NIC. * It has a pin named LOW_POWER to enable it into LOW POWER state. @@ -63,6 +76,109 @@ outb(byte, 0xC52); } +/******************************************************** +* dbm690t uses SB600 GPIO9 to detect IDE_DMA66. +* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to +* get the cable type, 40 pin or 80 pin? +********************************************************/ +static void get_ide_dma66() +{ + u8 byte; + /*u32 sm_dev, ide_dev; */ + device_t sm_dev, ide_dev; + struct bus pbus; + + sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + + byte = + pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, + sm_dev->path.u.pci.devfn, 0xA9); + byte |= (1 << 5); /* Set Gpio9 as input */ + pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, + sm_dev->path.u.pci.devfn, 0xA9, byte); + + ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); + byte = + pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary, + ide_dev->path.u.pci.devfn, 0x56); + byte &= ~(7 << 0); + if ((1 << 5) & pci_cf8_conf1. + read8(&pbus, sm_dev->bus->secondary, sm_dev->path.u.pci.devfn, + 0xAA)) + byte |= 2 << 0; /* mode 2 */ + else + byte |= 5 << 0; /* mode 5 */ + pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary, + ide_dev->path.u.pci.devfn, 0x56, byte); +} + +/* + * set thermal config + */ +static void set_thermal_config() +{ + u8 byte; + u16 word; + device_t sm_dev; + struct bus pbus; + + /* set ADT 7461 */ + ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ + ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */ + ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */ + ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */ + + ADT7461_write_byte(0x19, 0x55); /* External THERM limit */ + ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */ + + byte = ADT7461_read_byte(0x02); /* read status register to clear it */ + printk_info("Init adt7461 end , status 0x02 %02x\n", byte); + + /* sb600 settings for thermal config */ + /* set SB600 GPIO 64 to GPIO with pull-up */ + byte = pm2_ioread(0x42); + byte &= 0x3f; + pm2_iowrite(0x42, byte); + + /* set GPIO 64 to input */ + sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + word = + pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary, + sm_dev->path.u.pci.devfn, 0x56); + word |= 1 << 7; + pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, + sm_dev->path.u.pci.devfn, 0x56, word); + + /* set GPIO 64 internal pull-up */ + byte = pm2_ioread(0xf0); + byte &= 0xee; + pm2_iowrite(0xf0, byte); + + /* set Talert to be active low */ + byte = pm_ioread(0x67); + byte &= ~(1 << 5); + pm_iowrite(0x67, byte); + + /* set Talert to generate ACPI event */ + byte = pm_ioread(0x3c); + byte &= 0xf3; + pm_iowrite(0x3c, byte); + + /* THERMTRIP pin */ + /* byte = pm_ioread(0x68); + * byte |= 1 << 3; + * pm_iowrite(0x68, byte); + * + * byte = pm_ioread(0x55); + * byte |= 1 << 0; + * pm_iowrite(0x55, byte); + * + * byte = pm_ioread(0x67); + * byte &= ~( 1 << 6); + * pm_iowrite(0x67, byte); + */ +} + /************************************************* * enable the dedicated function in dbm690t board. * This function called early than rs690_enable. @@ -72,47 +188,54 @@ struct mainboard_amd_dbm690t_config *mainboard = (struct mainboard_amd_dbm690t_config *)dev->chip_info; + printk_info("Mainboard DBM690T Enable. dev=0x%x\n", dev); + #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ msr = rdmsr(TOP_MEM); - printk_info("dbm690t_enable, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", msr.lo, msr.hi); + printk_info + ("dbm690t_enable, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + msr.lo, msr.hi); /* TOP_MEM2: the top of DRAM above 4G */ msr2 = rdmsr(TOP_MEM2); - printk_info("dbm690t_enable, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", msr2.lo, msr2.hi); + printk_info + ("dbm690t_enable, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + msr2.lo, msr2.hi); switch (msr.lo) { - case 0x10000000: /* 256M system memory */ - uma_memory_size = 0x2000000; /* 32M recommended UMA */ - break; + case 0x10000000: /* 256M system memory */ + uma_memory_size = 0x2000000; /* 32M recommended UMA */ + break; - case 0x18000000: /* 384M system memory */ - uma_memory_size = 0x4000000; /* 64M recommended UMA */ - break; + case 0x18000000: /* 384M system memory */ + uma_memory_size = 0x4000000; /* 64M recommended UMA */ + break; - case 0x20000000: /* 512M system memory */ - uma_memory_size = 0x4000000; /* 64M recommended UMA */ - break; + case 0x20000000: /* 512M system memory */ + uma_memory_size = 0x4000000; /* 64M recommended UMA */ + break; - default: /* 1GB and above system memory */ - uma_memory_size = 0x8000000; /* 128M recommended UMA */ - break; + default: /* 1GB and above system memory */ + uma_memory_size = 0x8000000; /* 128M recommended UMA */ + break; } - uma_memory_start = msr.lo - uma_memory_size;/* TOP_MEM1 */ - printk_info("dbm690t_enable: uma size 0x%08x, memory start 0x%08x\n", uma_memory_size, uma_memory_start); + uma_memory_start = msr.lo - uma_memory_size; /* TOP_MEM1 */ + printk_info("dbm690t_enable: uma size 0x%08x, memory start 0x%08x\n", + uma_memory_size, uma_memory_start); /* TODO: TOP_MEM2 */ #else - uma_memory_size = 0x8000000; /* 128M recommended UMA */ - uma_memory_start = 0x38000000; /* 1GB system memory supposed */ + uma_memory_size = 0x8000000; /* 128M recommended UMA */ + uma_memory_start = 0x38000000; /* 1GB system memory supposed */ #endif - printk_info("dbm690t_enable. dev=0x%x\n", dev); - enable_onboard_nic(); + get_ide_dma66(); + set_thermal_config(); } /* @@ -122,5 +245,5 @@ #if CONFIG_CHIP_NAME == 1 CHIP_NAME("AMD Dbm690t Mainboard") #endif - .enable_dev = dbm690t_enable, + .enable_dev = dbm690t_enable, }; Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c 2008-12-01 19:49:57 UTC (rev 3786) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c 2008-12-01 19:52:54 UTC (rev 3787) @@ -31,11 +31,11 @@ extern u8 bus_rs690[8]; extern u8 bus_sb600[2]; -extern unsigned long apicid_sb600; +extern u32 apicid_sb600; -extern unsigned long bus_type[256]; -extern unsigned long sbdn_rs690; -extern unsigned long sbdn_sb600; +extern u32 bus_type[256]; +extern u32 sbdn_rs690; +extern u32 sbdn_sb600; extern void get_bus_conf(void); @@ -102,7 +102,7 @@ /* dword |= 1<<22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); - /* + /* * 00:12.0: PROG SATA : INT F * 00:13.0: INTA USB_0 * 00:13.1: INTB USB_1 @@ -121,7 +121,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - + IO_LOCAL_INT(mp_ExtINT, 0x0, apicid_sb600, 0x0); /* ISA ints are edge-triggered, and usually originate from the ISA bus, @@ -143,8 +143,12 @@ /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ +#if HAVE_ACPI_TABLES == 0 #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) +#else +#define PCI_INT(bus, dev, fn, pin) +#endif /* usb */ PCI_INT(0x0, 0x13, 0x0, 0x10);

1 0

r3786 - trunk/coreboot-v2/src/southbridge/amd/rs690
by svn＠coreboot.org 01 Dec '08

01 Dec '08

Author: mjones Date: 2008-12-01 20:49:57 +0100 (Mon, 01 Dec 2008) New Revision: 3786 Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/chip.h trunk/coreboot-v2/src/southbridge/amd/rs690/rs690.c trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_early_setup.c trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_ht.c trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c Log: Add AMD rs690 VID DID reporting and some minor cleanups. Signed-off-by: Joe Bao <zheng.bao(a)amd.com> Reviewed-by: Maggie Li <maggie.li(a)amd.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/chip.h =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/chip.h 2008-12-01 19:37:21 UTC (rev 3785) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/chip.h 2008-12-01 19:49:57 UTC (rev 3786) @@ -21,9 +21,9 @@ #define RS690_CHIP_H /* Member variables are defined in Config.lb. */ -struct southbridge_amd_rs690_config +struct southbridge_amd_rs690_config { - unsigned long vga_rom_address; /* The location that the VGA rom has been appened. */ + u32 vga_rom_address; /* The location that the VGA rom has been appened. */ u8 gpp_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */ u8 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */ u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */ Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690.c 2008-12-01 19:37:21 UTC (rev 3785) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690.c 2008-12-01 19:49:57 UTC (rev 3786) @@ -29,26 +29,7 @@ #include <cpu/amd/mtrr.h> #include "rs690.h" -static device_t find_nb_dev(device_t dev, u32 devfn) -{ - device_t nb_dev; - nb_dev = dev_find_slot(dev->bus->secondary, devfn); - - if (!nb_dev) - return nb_dev; - - if ((nb_dev->vendor != PCI_VENDOR_ID_ATI) - || (nb_dev->device != PCI_DEVICE_ID_ATI_RS690_HT)) { - u32 id; - id = pci_read_config32(nb_dev, PCI_VENDOR_ID); - if (id != (PCI_VENDOR_ID_ATI | (PCI_DEVICE_ID_ATI_RS690_HT << 16))) { - nb_dev = 0; - } - } - return nb_dev; -} - /***************************************** * Compliant with CIM_33's ATINB_MiscClockCtrl *****************************************/ @@ -65,7 +46,7 @@ word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8); word &= 0xf00; - pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word); + pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word); word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8); word &= ~((1 << 12) | (1 << 13) | (1 << 14)); @@ -123,6 +104,12 @@ set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8); } + +u32 get_vid_did(device_t dev) +{ + return pci_read_config32(dev, 0); +} + /*********************************************** * 0:00.0 NBCFG : * 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default @@ -140,39 +127,25 @@ void rs690_enable(device_t dev) { device_t nb_dev = 0, sb_dev = 0; - int index = -1; - u32 i; - u32 devfn; - u32 deviceid, vendorid; + int dev_ind; - vendorid = pci_read_config32(dev, PCI_VENDOR_ID); - deviceid = (vendorid >> 16) & 0xffff; - vendorid &= 0xffff; - printk_info("rs690_enable VID=0x%x, DID=0x%x\n", vendorid, deviceid); + printk_info("rs690_enable: dev=0x%x, VID_DID=0x%x\n", dev, get_vid_did(dev)); - /********************************************************** - * Work for bus0, internal GFX located on bus1 and will return after find_nb_dev. - **********************************************************/ - i = (dev->path.u.pci.devfn) & ~7; - for (devfn = 0; devfn <= i; devfn += (1 << 3)) { - nb_dev = find_nb_dev(dev, devfn); - if (nb_dev) - break; - } + nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!nb_dev) { - printk_info("CAN NOT FIND RS690 DEVICE!\n"); - return; /* nb_dev is not dev */ + die("rs690_enable: CAN NOT FIND RS690 DEVICE, HALT!\n"); + /* NOT REACHED */ } /* sb_dev (dev 8) is a bridge that links to southbridge. */ sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); if (!sb_dev) { - printk_info("rs690_enable CAN NOT FIND SB bridge, HALT!\n"); - for (;;) ; + die("rs690_enable: CAN NOT FIND SB bridge, HALT!\n"); + /* NOT REACHED */ } - printk_info("rs690_enable bus0, dev=0x%x\n", (dev->path.u.pci.devfn - devfn) >> 3); - switch (dev->path.u.pci.devfn - devfn) { + dev_ind = dev->path.u.pci.devfn >> 3; + switch (dev_ind) { case 0: /* bus0, dev0, fun0; */ printk_info("Bus-0, Dev-0, Fun-0.\n"); enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ @@ -185,36 +158,34 @@ rs690_config_misc_clk(nb_dev); break; - case 1 << 3: /* bus0, dev1 */ + case 1: /* bus0, dev1 */ printk_info("Bus-0, Dev-1, Fun-0.\n"); break; - case 2 << 3: /* bus0, dev2,3, two GFX */ - case 3 << 3: + case 2: /* bus0, dev2,3, two GFX */ + case 3: printk_info("Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); - index = (dev->path.u.pci.devfn - devfn) >> 3; - set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << index, - (dev->enabled ? 0 : 1) << index); + set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, + (dev->enabled ? 0 : 1) << dev_ind); if (dev->enabled) - rs690_gfx_init(nb_dev, dev, index); + rs690_gfx_init(nb_dev, dev, dev_ind); break; - case 4 << 3: /* bus0, dev4-7, four GPP */ - case 5 << 3: - case 6 << 3: - case 7 << 3: + case 4: /* bus0, dev4-7, four GPP */ + case 5: + case 6: + case 7: printk_info("Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", dev->enabled); - index = (dev->path.u.pci.devfn - devfn) >> 3; - set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << index, - (dev->enabled ? 0 : 1) << index); + set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, + (dev->enabled ? 0 : 1) << dev_ind); if (dev->enabled) - rs690_gpp_sb_init(nb_dev, dev, index); + rs690_gpp_sb_init(nb_dev, dev, dev_ind); break; - case 8 << 3: /* bus0, dev8, SB */ + case 8: /* bus0, dev8, SB */ printk_info("Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, (dev->enabled ? 1 : 0) << 6); if (dev->enabled) - rs690_gpp_sb_init(nb_dev, dev, index); + rs690_gpp_sb_init(nb_dev, dev, dev_ind); disable_pcie_bar3(nb_dev); break; default: Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c 2008-12-01 19:37:21 UTC (rev 3785) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c 2008-12-01 19:49:57 UTC (rev 3786) @@ -63,8 +63,8 @@ /*get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c); - printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, - dev->path.u.pci.devfn); + /*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, + dev->path.u.pci.devfn);*/ addr |= dev->bus->secondary << 20 | /* bus num */ dev->path.u.pci.devfn << 12 | reg_pos; Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_early_setup.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_early_setup.c 2008-12-01 19:37:21 UTC (rev 3785) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_early_setup.c 2008-12-01 19:49:57 UTC (rev 3786) @@ -18,7 +18,6 @@ */ - #define NBHTIU_INDEX 0xA8 #define NBMISC_INDEX 0x60 #define NBMC_INDEX 0xE8 @@ -185,7 +184,7 @@ * get k8's ht freq, in k8's function 0, offset 0x88 * bit11-8, specifics the maximum operation frequency of the link's transmitter clock. * The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero - * value to this reg, and that value takes effect on the next warm reset or + * value to this reg, and that value takes effect on the next warm reset or * LDTSTOP_L disconnect sequence. * 0000b = 200Mhz * 0010b = 400Mhz @@ -300,7 +299,7 @@ /*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR, * force this BAR as mem type in rs690_gfx.c */ set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03); - + } /***************************************** Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c 2008-12-01 19:37:21 UTC (rev 3785) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c 2008-12-01 19:49:57 UTC (rev 3786) @@ -72,7 +72,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) { - unsigned short deviceid, vendorid; + u16 deviceid, vendorid; struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)dev->chip_info; deviceid = pci_read_config16(dev, PCI_DEVICE_ID); @@ -109,11 +109,6 @@ clkind_write(dev, 0x5C, 0x0); } -static void rs690_gfx_set_resources(struct device *dev) -{ - printk_info("rs690_gfx_set_resources.\n"); - pci_dev_set_resources(dev); -} /* * Set registers in RS690 and CPU to enable the internal GFX. @@ -137,7 +132,7 @@ /* set TOM */ rs690_set_tom(nb_dev); - + /* LPC DMA Deadlock workaround? */ k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); l_dword = pci_read_config32(k8_f0, 0x68); @@ -206,9 +201,9 @@ .set_subsystem = pci_dev_set_subsystem, }; -static struct device_operations ht_ops = { +static struct device_operations pcie_ops = { .read_resources = rs690_gfx_read_resources, - .set_resources = rs690_gfx_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = internal_gfx_pci_dev_init, /* The option ROM initializes the device. rs690_gfx_init, */ .scan_bus = 0, @@ -216,8 +211,8 @@ .ops_pci = &lops_pci, }; -static struct pci_driver internal_gfx_driver __pci_driver = { - .ops = &ht_ops, +static struct pci_driver pcie_driver __pci_driver = { + .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_RS690MT_INT_GFX, }; @@ -350,7 +345,7 @@ } -/* For single port GFX configuration Only +/* For single port GFX configuration Only * width: * 000 = x16 * 001 = x1 @@ -492,7 +487,7 @@ set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10); printk_info("rs690_gfx_init step8.3.\n"); - /* step 8.4 if the LTSSM could not see all 8 TS1 during Polling Active, it can still + /* step 8.4 if the LTSSM could not see all 8 TS1 during Polling Active, it can still * time out and go back to Detect Idle.*/ set_pcie_enable_bits(dev, 0x02, 1 << 14, 1 << 14); printk_info("rs690_gfx_init step8.4.\n"); @@ -510,7 +505,7 @@ set_pcie_enable_bits(dev, 0xa0, 3 << 30, 3 << 30); printk_info("rs690_gfx_init step8.8.\n"); - /* step 8.9 Setting this register to 0x1 will workaround a PCI Compliance failure reported by Vista DTM. + /* step 8.9 Setting this register to 0x1 will workaround a PCI Compliance failure reported by Vista DTM. * SLOT_IMPLEMENTED@PCIE_CAP */ reg16 = pci_read_config16(dev, 0x5a); reg16 |= 0x100; @@ -563,7 +558,7 @@ /* step 10.e: LCLK clock gating, done in rs690_config_misc_clk() */ - /* step 11 Poll GPIO to determine whether it is single-port or dual-port configuration. + /* step 11 Poll GPIO to determine whether it is single-port or dual-port configuration. * While details will be added later in the document, for now assue the single-port configuration. */ /* skip */ Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_ht.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_ht.c 2008-12-01 19:37:21 UTC (rev 3785) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_ht.c 2008-12-01 19:49:57 UTC (rev 3786) @@ -61,7 +61,7 @@ dword |= (1 << 30); /* Clear possible errors */ pci_write_config32(dev, 0x04, dword); - /* + /* * 1 is APIC enable * 18 is enable nb to accept A4 interrupt request from SB. */ Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c 2008-12-01 19:37:21 UTC (rev 3785) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c 2008-12-01 19:49:57 UTC (rev 3786) @@ -116,37 +116,6 @@ pci_write_config32(dev, 0x04, dword); } -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - /*.enable = rs690_enable, */ - .ops_pci = &lops_pci, -}; - -static struct pci_driver pcie_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE, -}; - -static struct pci_driver pcie_driver_dev7 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV7, -}; -static struct pci_driver pcie_driver_dev8 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8, -}; - /********************************************************************** **********************************************************************/ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)

1 0

r3785 - trunk/coreboot-v2/src/southbridge/amd/sb600
by svn＠coreboot.org 01 Dec '08

01 Dec '08

Author: mjones Date: 2008-12-01 20:37:21 +0100 (Mon, 01 Dec 2008) New Revision: 3785 Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/chip.h trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_hda.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_ide.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_reset.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sata.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_smbus.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_smbus.h Log: Add AMD sb600 HPET setup and some minor cleanups. Signed-off-by: Joe Bao <zheng.bao(a)amd.com> Reviewed-by: Maggie Li <maggie.li(a)amd.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/chip.h =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/chip.h 2008-12-01 14:18:57 UTC (rev 3784) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/chip.h 2008-12-01 19:37:21 UTC (rev 3785) @@ -20,11 +20,11 @@ #ifndef SB600_CHIP_H #define SB600_CHIP_H -struct southbridge_amd_sb600_config +struct southbridge_amd_sb600_config { - unsigned int ide0_enable : 1; - unsigned int sata0_enable : 1; - unsigned long hda_viddid; + u32 ide0_enable : 1; + u32 sata0_enable : 1; + u32 hda_viddid; }; struct chip_operations; extern struct chip_operations southbridge_amd_sb600_ops; Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c 2008-12-01 14:18:57 UTC (rev 3784) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c 2008-12-01 19:37:21 UTC (rev 3785) @@ -24,6 +24,7 @@ #define SMBUS_IO_BASE 0x1000 /* Is it a temporary SMBus I/O base address? */ /*SIZE 0x40 */ + static void pmio_write(u8 reg, u8 value) { outb(reg, PM_INDEX); @@ -44,6 +45,7 @@ if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\r\n"); + /* NOT REACHED */ } return pci_read_config8(dev, 0x08); } @@ -259,6 +261,7 @@ if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\r\n"); + /* NOT REACHED */ } printk_info("SMBus controller enabled, sb revision is 0x%x\r\n", get_sb600_revision()); @@ -317,7 +320,7 @@ pci_write_config8(dev, 0x62, byte); /* Features Enable */ - pci_write_config32(dev, 0x64, 0x829E79BF); + pci_write_config32(dev, 0x64, 0x829E7DBF); /* bit10: Enables the HPET interrupt. */ /* SerialIrq Control */ pci_write_config8(dev, 0x69, 0x90); @@ -373,7 +376,7 @@ byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */ pci_write_config8(dev, 0x4A, byte); - /* Set LPC ROM size, it has been done in sb600_lpc_init(). + /* Set LPC ROM size, it has been done in sb600_lpc_init(). * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB; * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB * pci_write_config16(dev, 0x68, 0x000e) @@ -382,7 +385,7 @@ /* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */ pci_write_config8(dev, 0x7C, 0x05); - /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, + /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, * TODO: I don't know what are their mean? */ printk_info("sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -397,7 +400,7 @@ pci_write_config8(dev, 0x40, 0x26); - /* I don't know why CIM set reg0x1c as 0x11. + /* I don't know why CIM set reg0x1c as 0x11. * System will block at sdram_initialize() if I set it before call sdram_initialize(). * If it is necessary to set reg0x1c as 0x11, please call this function after sdram_initialize(). * pci_write_config8(dev, 0x1c, 0x11); @@ -490,8 +493,10 @@ pmio_write(0x9e, byte); /* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */ + /* We have to clear this bit here, otherwise the kernel hangs. */ byte = pmio_read(0x55); byte |= 1 << 7; + byte |= 1 << 1; pmio_write(0x55, byte); /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */ @@ -550,7 +555,7 @@ byte |= (1 << 3); pci_write_config8(dev, 0x41, byte); - /* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles) + /* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles) * generated PCIRST#. */ byte = pmio_read(0x65); byte |= (1 << 4); Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_hda.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_hda.c 2008-12-01 14:18:57 UTC (rev 3784) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_hda.c 2008-12-01 19:37:21 UTC (rev 3785) @@ -55,7 +55,7 @@ return 0; } -static int codec_detect(u8 * base) +static u32 codec_detect(u8 * base) { u32 dword; @@ -148,7 +148,7 @@ 0x01f71ec4, 0x01f71f01, }; -static unsigned find_verb(u32 viddid, u32 ** verb) +static u32 find_verb(u32 viddid, u32 ** verb) { device_t azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2)); struct southbridge_amd_sb600_config *cfg = Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_ide.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_ide.c 2008-12-01 14:18:57 UTC (rev 3784) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_ide.c 2008-12-01 19:37:21 UTC (rev 3785) @@ -38,13 +38,10 @@ pci_write_config32(dev, 0x70, dword); /* Ultra DMA mode */ + /* enable UDMA */ byte = pci_read_config8(dev, 0x54); byte |= 1 << 0; pci_write_config8(dev, 0x54, byte); - byte = pci_read_config8(dev, 0x56); - byte &= ~(7 << 0); - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(dev, 0x56, byte); /* Enable I/O Access&& Bus Master */ dword = pci_read_config16(dev, 0x4); Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c 2008-12-01 14:18:57 UTC (rev 3784) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c 2008-12-01 19:37:21 UTC (rev 3785) @@ -82,14 +82,14 @@ compact_resources(dev); } -/** +/** * @brief Enable resources for children devices - * + * * @param dev the device whos children's resources are to be enabled - * + * * This function is call by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. - * + * * Indirect mutual recursion: * enable_childrens_resources() -> enable_resources() * enable_resources() -> device_operation::enable_resources() @@ -115,7 +115,7 @@ && (child->path.type == DEVICE_PATH_PNP)) { for (i = 0; i < child->resources; i++) { struct resource *res; - unsigned long base, end; /* don't need long long */ + u32 base, end; /* don't need long long */ res = &child->resource[i]; if (!(res->flags & IORESOURCE_IO)) continue; Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_reset.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_reset.c 2008-12-01 14:18:57 UTC (rev 3784) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_reset.c 2008-12-01 19:37:21 UTC (rev 3785) @@ -24,7 +24,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; +typedef u32 device_t; #include "../../../northbridge/amd/amdk8/reset_test.c" Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sata.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sata.c 2008-12-01 14:18:57 UTC (rev 3784) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sata.c 2008-12-01 19:37:21 UTC (rev 3785) @@ -62,12 +62,12 @@ sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x7; sata_bar4 = pci_read_config16(dev, 0x20) & ~0x7; - printk_debug("sata_bar0=%x\n", sata_bar0); /* 3030 */ - printk_debug("sata_bar1=%x\n", sata_bar1); /* 3070 */ - printk_debug("sata_bar2=%x\n", sata_bar2); /* 3040 */ - printk_debug("sata_bar3=%x\n", sata_bar3); /* 3080 */ - printk_debug("sata_bar4=%x\n", sata_bar4); /* 3000 */ - printk_debug("sata_bar5=%x\n", sata_bar5); /* e0309000 */ + /* printk_debug("sata_bar0=%x\n", sata_bar0); */ /* 3030 */ + /* printk_debug("sata_bar1=%x\n", sata_bar1); */ /* 3070 */ + /* printk_debug("sata_bar2=%x\n", sata_bar2); */ /* 3040 */ + /* printk_debug("sata_bar3=%x\n", sata_bar3); */ /* 3080 */ + /* printk_debug("sata_bar4=%x\n", sata_bar4); */ /* 3000 */ + /* printk_debug("sata_bar5=%x\n", sata_bar5); */ /* e0309000 */ /* Program the 2C to 0x43801002 */ dword = 0x43801002; @@ -142,15 +142,15 @@ /* Use BAR5+0x2A8,BAR0+0x6 for Secondary Slave */ byte = readb(sata_bar5 + 0x128); - printk_debug("byte=%x\n", byte); + /* printk_debug("byte=%x\n", byte); */ byte &= 0xF; if (byte == 0x3) { outb(0xA0, sata_bar0 + 0x6); while ((inb(sata_bar0 + 0x6) != 0xA0) || ((inb(sata_bar0 + 0x7) & 0x88) != 0)) { mdelay(10); - printk_debug("0x6=%x,0x7=%x\n", inb(sata_bar0 + 0x6), - inb(sata_bar0 + 0x7)); + /* printk_debug("0x6=%x,0x7=%x\n", inb(sata_bar0 + 0x6), + inb(sata_bar0 + 0x7)); */ printk_debug("drive detection fail,trying...\n"); } printk_debug("Primary master device is ready\n"); Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c 2008-12-01 14:18:57 UTC (rev 3784) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c 2008-12-01 19:37:21 UTC (rev 3785) @@ -41,8 +41,8 @@ #endif struct ioapicreg { - unsigned int reg; - unsigned int value_low, value_high; + u32 reg; + u32 value_low, value_high; }; static struct ioapicreg ioapicregvalues[] = { @@ -89,18 +89,18 @@ /* Be careful and don't write past the end... */ }; -static void setup_ioapic(unsigned long ioapic_base) +static void setup_ioapic(u32 ioapic_base) { int i; - unsigned long value_low, value_high; - volatile unsigned long *l; + u32 value_low, value_high; + volatile u32 *l; struct ioapicreg *a = ioapicregvalues; ioapicregvalues[0].value_high = lapicid() << (56 - 32); printk_debug("lapicid = %016x\n", ioapicregvalues[0].value_high); - l = (unsigned long *)ioapic_base; + l = (u32 *)ioapic_base; for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { @@ -126,9 +126,9 @@ u8 byte; u8 byte_old; u32 dword; - unsigned long ioapic_base; - int on; - int nmi_option; + u32 ioapic_base; + u32 on; + u32 nmi_option; printk_info("sm_init().\n"); @@ -143,6 +143,10 @@ dword |= 1 << 9; pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */ + /* bit 10: MultiMediaTimerIrqEn */ + dword = pci_read_config8(dev, 0x64); + dword |= 1 << 10; + pci_write_config8(dev, 0x64, dword); /* enable serial irq */ byte = pci_read_config8(dev, 0x69); byte |= 1 << 7; /* enable serial irq function */ @@ -191,8 +195,21 @@ byte = pm_ioread(0x68); byte &= ~(1 << 1); + /* 2.6 */ + byte |= 1 << 2; pm_iowrite(0x68, byte); + /* 2.6 */ + byte = pm_ioread(0x65); + byte &= ~(1 << 7); + pm_iowrite(0x65, byte); + + /* 2.3.4 */ + byte = pm_ioread(0x52); + byte &= ~0x2F; + byte |= 0x8; + pm_iowrite(0x52, byte); + byte = pm_ioread(0x8D); byte &= ~(1 << 6); pm_iowrite(0x8D, byte); @@ -344,10 +361,20 @@ static void sb600_sm_read_resources(device_t dev) { struct resource *res; + u8 byte; + /* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */ + byte = pm_ioread(0x55); + byte |= 1 << 7; + pm_iowrite(0x55, byte); + /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); + /* pci_dev_read_resources(dev); */ + byte = pm_ioread(0x55); + byte &= ~(1 << 7); + pm_iowrite(0x55, byte); + /* apic */ res = new_resource(dev, 0x74); res->base = 0xfec00000; @@ -357,19 +384,49 @@ res->gran = 8; res->flags = IORESOURCE_MEM | IORESOURCE_FIXED; + res = new_resource(dev, 0x14); /* hpet */ + res->base = 0xfed00000; /* reset hpet to widely accepted address */ + res->size = 0x400; + res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ + res->align = 8; + res->gran = 8; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED; /* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */ + /* smbus */ + res = new_resource(dev, 0x10); + res->base = 0xB00; + res->size = 0x10; + res->limit = 0xFFFFUL; /* res->base + res->size -1; */ + res->align = 8; + res->gran = 8; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED; + + compact_resources(dev); } static void sb600_sm_set_resources(struct device *dev) { struct resource *res; + u8 byte; pci_dev_set_resources(dev); + + /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */ + byte = pm_ioread(0x52); + byte |= 1 << 6; + pm_iowrite(0x52, byte); + res = find_resource(dev, 0x74); pci_write_config32(dev, 0x74, res->base | 1 << 3); + + res = find_resource(dev, 0x14); + pci_write_config32(dev, 0x14, res->base); + + res = find_resource(dev, 0x10); + pci_write_config32(dev, 0x10, res->base | 1); } static struct pci_operations lops_pci = { Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_smbus.c 2008-12-01 14:18:57 UTC (rev 3784) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_smbus.c 2008-12-01 19:37:21 UTC (rev 3785) @@ -17,12 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -//#include <arch/io.h> -//#include <device/device.h> -//#include <device/pci.h> -//#include <device/pci_ids.h> -//#include <device/pci_ops.h> -//#include <device/smbus_def.h> #include "sb600_smbus.h" static inline void smbus_delay(void) @@ -32,7 +26,7 @@ static int smbus_wait_until_ready(u32 smbus_io_base) { - unsigned long loops; + u32 loops; loops = SMBUS_TIMEOUT; do { u8 val; @@ -48,7 +42,7 @@ static int smbus_wait_until_done(u32 smbus_io_base) { - unsigned long loops; + u32 loops; loops = SMBUS_TIMEOUT; do { u8 val; @@ -121,7 +115,7 @@ return 0; } -static int do_smbus_read_byte(u32 smbus_io_base, u32 device, +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) { u8 byte; @@ -152,7 +146,7 @@ return byte; } -static int do_smbus_write_byte(u32 smbus_io_base, u32 device, +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) { u8 byte; @@ -183,10 +177,11 @@ return 0; } -static void alink_ab_indx(unsigned int reg_space, unsigned int reg_addr, - unsigned int mask, unsigned int val) +static void alink_ab_indx(u32 reg_space, u32 reg_addr, + u32 mask, u32 val) { - unsigned int tmp; + u32 tmp; + outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX); tmp = inl(AB_DATA); @@ -201,10 +196,10 @@ /* space = 0: AX_INDXC, AX_DATAC * space = 1: AX_INDXP, AX_DATAP */ -static void alink_ax_indx(unsigned int space /*c or p? */ , unsigned int axindc, - unsigned int mask, unsigned int val) +static void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, + u32 mask, u32 val) { - unsigned int tmp; + u32 tmp; /* read axindc to tmp */ outl(space << 30 | space << 3 | 0x30, AB_INDX); @@ -221,6 +216,3 @@ outl(space << 30 | space << 3 | 0x34, AB_INDX); outl(tmp, AB_DATA); } - - - Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_smbus.h =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_smbus.h 2008-12-01 14:18:57 UTC (rev 3784) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_smbus.h 2008-12-01 19:37:21 UTC (rev 3785) @@ -44,7 +44,7 @@ #define AB_INDX 0xCD8 #define AB_DATA (AB_INDX+4) -/* Between 1-10 seconds, We should never timeout normally +/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ #define SMBUS_TIMEOUT (100*1000*10)

1 0

[PATCH] Athlon64 K8 fixes
by Robert Millan 01 Dec '08

01 Dec '08

Hi, My Athlon64 / K8 socket 939 setup needed the following adjustments to fix memory read/write errors. Thanks to Rudolf for hinting on which bits I should check for. Details: - bit 9, mandated by spec to always be set on sodimm or socket 939 dual dimm. - bit 28, enable 2T timing. no idea why, but I get memory errors without it. - bit 29, upper chip select. mandated by spec on socket 939. My patch also adds missing descriptions, based on the ones from the spec (http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/260…) -- Robert Millan The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and how) you may access your data; but nobody's threatening your freedom: we still allow you to remove your data and not access it at all."

5 8

[PATCH] superiotool: dump winbond hardware monitor registers
by Stefan Reinauer 01 Dec '08

01 Dec '08

See patch. The Winbond SuperIO chips have another indirection of registers. The hwmon has generic registers and banked registers, mostly temperature handling, and SMI/GPIO stuff. Regards, Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 * Not all LDNs are switched via register offset 0x07, make it a parameter * add support for dumping the hardware monitor of Winbond W83627THF/THG parts with -e Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: fintek.c =================================================================== --- fintek.c (revision 3779) +++ fintek.c (working copy) @@ -137,7 +137,7 @@ get_superio_name(reg_table, did), vid, did, port); chip_found = 1; - dump_superio("Fintek", reg_table, port, did); + dump_superio("Fintek", reg_table, port, did, LDN_SEL); exit_conf_mode_winbond_fintek_ite_8787(port); } Index: winbond.c =================================================================== --- winbond.c (revision 3779) +++ winbond.c (working copy) @@ -468,6 +468,51 @@ {EOT} }; +static const struct superio_registers hwm_table[] = { + {0x828, "W83627THF/THG", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x1e,0x1f, + 0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, + 0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31,0x32,0x33,0x34, + 0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e, + 0x3f, + 0x40,0x41,0x42,0x43,0x44,0x47,0x48,0x49,0x4a,0x4b, + 0x4c,0x4d,0x4e,0x4f,EOT}, + {RSVD,0xff,RSVD,0xff,0x00,0x00,0x00,0x00,0x01,0x01, + 0x01,0x01,0x3c,0x3c,0x0a,0x0a,RSVD,0xff,0x00,0x00, + 0x00,0x01,0x01,0x3c,0x43,RSVD,0xff,0xff,RSVD,RSVD, + NANA,NANA, + NANA,NANA,NANA,NANA,NANA,RSVD,RSVD,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + RSVD,RSVD,RSVD,RSVD,NANA,NANA,NANA,NANA,NANA,RSVD, + RSVD, + 0x03,0x00,0x00,0xfe,0xff,0x5f,NANA,0x03,RSVD,0x44, + 0x18,0x15,0x80,0x5c,EOT}}, + {0x0, "BANK 0", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5d,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,0x00,0x80,0x90,0x70, + 0x00,EOT}}, + {0x1, "BANK 1", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT}, + {NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}}, + {0x2, "BANK 2", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT}, + {NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}}, + {0x4, "BANK 4", + {0x50,0x51,0x53,0x54,0x55,0x56,0x59,0x5a,0x5b,EOT}, + {0x00,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x5, "BANK 5", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {EOT}}}, + {EOT} +}; + + static void enter_conf_mode_winbond_88(uint16_t port) { OUTB(0x88, port); @@ -486,7 +531,7 @@ static void probe_idregs_winbond_helper(const char *init, uint16_t port) { - uint16_t id; + uint16_t id, hwmport; uint8_t devid, rev, olddevid; probing_for("Winbond", init, port); @@ -522,7 +567,28 @@ get_superio_name(reg_table, id), devid, rev, port); chip_found = 1; - dump_superio("Winbond", reg_table, port, id); + dump_superio("Winbond", reg_table, port, id, LDN_SEL); + + if (extra_dump) { + regwrite(port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */ + + if ((regval(port, 0x30) & (1 << 0)) != (1 << 0)) { + printf("Hardware Monitor disabled or does not exist.\n"); + return; + } + + /* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */ + hwmport = regval(port, 0x60) << 8; + hwmport |= regval(port, 0x61); + + /* HWM address register = HWM base address + 5. */ + hwmport += 5; + + printf("Hardware Monitor (0x%04x)\n", hwmport); + dump_superio("Winbond-HWM", hwm_table, hwmport, id, + WINBOND_HWM_SEL); + } + } void probe_idregs_winbond(uint16_t port) Index: ite.c =================================================================== --- ite.c (revision 3779) +++ ite.c (working copy) @@ -534,7 +534,7 @@ get_superio_name(reg_table, id), id, chipver, port); chip_found = 1; - dump_superio("ITE", reg_table, port, id); + dump_superio("ITE", reg_table, port, id, LDN_SEL); if (extra_dump) { regwrite(port, 0x07, 0x04); /* Select LDN 4 (EC). */ @@ -547,7 +547,7 @@ ecport += 5; printf("Environment controller (0x%04x)\n", ecport); - dump_superio("ITE-EC", ec_table, ecport, id); + dump_superio("ITE-EC", ec_table, ecport, id, LDN_SEL); } } Index: nsc.c =================================================================== --- nsc.c (revision 3779) +++ nsc.c (working copy) @@ -506,7 +506,7 @@ get_superio_name(reg_table, id), id, rev, port); chip_found = 1; - dump_superio("NSC", reg_table, port, id); + dump_superio("NSC", reg_table, port, id, LDN_SEL); } void print_nsc_chips(void) Index: superiotool.c =================================================================== --- superiotool.c (revision 3779) +++ superiotool.c (working copy) @@ -82,7 +82,7 @@ } static void dump_regs(const struct superio_registers reg_table[], - int i, int j, uint16_t port) + int i, int j, uint16_t port, uint8_t bank_sel) { int k; const int16_t *idx; @@ -91,7 +91,7 @@ printf("LDN 0x%02x", reg_table[i].ldn[j].ldn); if (reg_table[i].ldn[j].name != NULL) printf(" (%s)", reg_table[i].ldn[j].name); - regwrite(port, 0x07, reg_table[i].ldn[j].ldn); + regwrite(port, bank_sel, reg_table[i].ldn[j].ldn); } else { printf("Register dump:"); } @@ -131,7 +131,7 @@ void dump_superio(const char *vendor, const struct superio_registers reg_table[], - uint16_t port, uint16_t id) + uint16_t port, uint16_t id, uint8_t bank_sel) { int i, j, no_dump_available = 1; @@ -149,7 +149,7 @@ if (reg_table[i].ldn[j].ldn == EOT) break; no_dump_available = 0; - dump_regs(reg_table, i, j, port); + dump_regs(reg_table, i, j, port, bank_sel); } if (no_dump_available) Index: ali.c =================================================================== --- ali.c (revision 3779) +++ ali.c (working copy) @@ -95,7 +95,7 @@ get_superio_name(reg_table, id), id, rev, port); chip_found = 1; - dump_superio("ALi", reg_table, port, id); + dump_superio("ALi", reg_table, port, id, LDN_SEL); exit_conf_mode_ali(port); } Index: smsc.c =================================================================== --- smsc.c (revision 3779) +++ smsc.c (working copy) @@ -643,7 +643,7 @@ id, rev, port); chip_found = 1; - dump_superio((id == 0x77 ? "ASUS" : "SMSC"), reg_table, port, id); + dump_superio((id == 0x77 ? "ASUS" : "SMSC"), reg_table, port, id, LDN_SEL); exit_conf_mode_smsc(port); } Index: superiotool.h =================================================================== --- superiotool.h (revision 3779) +++ superiotool.h (working copy) @@ -73,10 +73,14 @@ #define MISC -5 /* Needs special comment in output */ #define MAXLDN 0x14 /* Biggest LDN */ #define LDNSIZE (MAXLDN + 3) /* Biggest LDN + 0 + NOLDN + EOT */ -#define MAXNUMIDX 170 /* Maximum number of indexes */ +#define MAXNUMIDX 170 /* Maximum number of indices */ #define IDXSIZE (MAXNUMIDX + 1) #define MAXNUMPORTS (6 + 1) /* Maximum number of Super I/O ports */ +/* select registers for various components */ +#define LDN_SEL 0x07 /* LDN select register */ +#define WINBOND_HWM_SEL 0x4e /* Hardware Monitor Bank Select */ + /* Command line parameters. */ extern int dump, verbose, extra_dump; @@ -102,7 +106,7 @@ const char *get_superio_name(const struct superio_registers reg_table[], uint16_t id); void dump_superio(const char *name, const struct superio_registers reg_table[], - uint16_t port, uint16_t id); + uint16_t port, uint16_t id, uint8_t bank_sel); void probing_for(const char *vendor, const char *info, uint16_t port); void print_vendor_chips(const char *vendor, const struct superio_registers reg_table[]);

2 2

r3784 - trunk/util/superiotool
by svn＠coreboot.org 01 Dec '08

01 Dec '08

Author: uwe Date: 2008-12-01 15:18:57 +0100 (Mon, 01 Dec 2008) New Revision: 3784 Modified: trunk/util/superiotool/ali.c trunk/util/superiotool/fintek.c trunk/util/superiotool/ite.c trunk/util/superiotool/nsc.c trunk/util/superiotool/smsc.c trunk/util/superiotool/superiotool.c trunk/util/superiotool/superiotool.h trunk/util/superiotool/winbond.c Log: The Winbond Super I/O chips have another indirection of registers. The hwmon has generic registers and banked registers, mostly temperature handling, and SMI/GPIO stuff. Not all LDNs are switched via register offset 0x07, make it a parameter. Add support for dumping the hardware monitor of Winbond W83627THF/THG parts with the -e option. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/ali.c =================================================================== --- trunk/util/superiotool/ali.c 2008-11-30 14:52:46 UTC (rev 3783) +++ trunk/util/superiotool/ali.c 2008-12-01 14:18:57 UTC (rev 3784) @@ -95,7 +95,7 @@ get_superio_name(reg_table, id), id, rev, port); chip_found = 1; - dump_superio("ALi", reg_table, port, id); + dump_superio("ALi", reg_table, port, id, LDN_SEL); exit_conf_mode_ali(port); } Modified: trunk/util/superiotool/fintek.c =================================================================== --- trunk/util/superiotool/fintek.c 2008-11-30 14:52:46 UTC (rev 3783) +++ trunk/util/superiotool/fintek.c 2008-12-01 14:18:57 UTC (rev 3784) @@ -137,7 +137,7 @@ get_superio_name(reg_table, did), vid, did, port); chip_found = 1; - dump_superio("Fintek", reg_table, port, did); + dump_superio("Fintek", reg_table, port, did, LDN_SEL); exit_conf_mode_winbond_fintek_ite_8787(port); } Modified: trunk/util/superiotool/ite.c =================================================================== --- trunk/util/superiotool/ite.c 2008-11-30 14:52:46 UTC (rev 3783) +++ trunk/util/superiotool/ite.c 2008-12-01 14:18:57 UTC (rev 3784) @@ -534,10 +534,10 @@ get_superio_name(reg_table, id), id, chipver, port); chip_found = 1; - dump_superio("ITE", reg_table, port, id); + dump_superio("ITE", reg_table, port, id, LDN_SEL); if (extra_dump) { - regwrite(port, 0x07, 0x04); /* Select LDN 4 (EC). */ + regwrite(port, LDN_SEL, 0x04); /* Select LDN 4 (EC). */ /* Get EC base address (stored in LDN 4, index 0x60/0x61). */ ecport = regval(port, 0x60) << 8; @@ -547,7 +547,7 @@ ecport += 5; printf("Environment controller (0x%04x)\n", ecport); - dump_superio("ITE-EC", ec_table, ecport, id); + dump_superio("ITE-EC", ec_table, ecport, id, LDN_SEL); } } @@ -583,5 +583,5 @@ void print_ite_chips(void) { print_vendor_chips("ITE", reg_table); - print_vendor_chips("ITE EC", ec_table); + print_vendor_chips("ITE-EC", ec_table); } Modified: trunk/util/superiotool/nsc.c =================================================================== --- trunk/util/superiotool/nsc.c 2008-11-30 14:52:46 UTC (rev 3783) +++ trunk/util/superiotool/nsc.c 2008-12-01 14:18:57 UTC (rev 3784) @@ -506,7 +506,7 @@ get_superio_name(reg_table, id), id, rev, port); chip_found = 1; - dump_superio("NSC", reg_table, port, id); + dump_superio("NSC", reg_table, port, id, LDN_SEL); } void print_nsc_chips(void) Modified: trunk/util/superiotool/smsc.c =================================================================== --- trunk/util/superiotool/smsc.c 2008-11-30 14:52:46 UTC (rev 3783) +++ trunk/util/superiotool/smsc.c 2008-12-01 14:18:57 UTC (rev 3784) @@ -643,7 +643,8 @@ id, rev, port); chip_found = 1; - dump_superio((id == 0x77 ? "ASUS" : "SMSC"), reg_table, port, id); + dump_superio((id == 0x77 ? "ASUS" : "SMSC"), reg_table, port, id, + LDN_SEL); exit_conf_mode_smsc(port); } Modified: trunk/util/superiotool/superiotool.c =================================================================== --- trunk/util/superiotool/superiotool.c 2008-11-30 14:52:46 UTC (rev 3783) +++ trunk/util/superiotool/superiotool.c 2008-12-01 14:18:57 UTC (rev 3784) @@ -82,7 +82,7 @@ } static void dump_regs(const struct superio_registers reg_table[], - int i, int j, uint16_t port) + int i, int j, uint16_t port, uint8_t ldn_sel) { int k; const int16_t *idx; @@ -91,7 +91,7 @@ printf("LDN 0x%02x", reg_table[i].ldn[j].ldn); if (reg_table[i].ldn[j].name != NULL) printf(" (%s)", reg_table[i].ldn[j].name); - regwrite(port, 0x07, reg_table[i].ldn[j].ldn); + regwrite(port, ldn_sel, reg_table[i].ldn[j].ldn); } else { printf("Register dump:"); } @@ -131,7 +131,7 @@ void dump_superio(const char *vendor, const struct superio_registers reg_table[], - uint16_t port, uint16_t id) + uint16_t port, uint16_t id, uint8_t ldn_sel) { int i, j, no_dump_available = 1; @@ -149,7 +149,7 @@ if (reg_table[i].ldn[j].ldn == EOT) break; no_dump_available = 0; - dump_regs(reg_table, i, j, port); + dump_regs(reg_table, i, j, port, ldn_sel); } if (no_dump_available) Modified: trunk/util/superiotool/superiotool.h =================================================================== --- trunk/util/superiotool/superiotool.h 2008-11-30 14:52:46 UTC (rev 3783) +++ trunk/util/superiotool/superiotool.h 2008-12-01 14:18:57 UTC (rev 3784) @@ -73,10 +73,14 @@ #define MISC -5 /* Needs special comment in output */ #define MAXLDN 0x14 /* Biggest LDN */ #define LDNSIZE (MAXLDN + 3) /* Biggest LDN + 0 + NOLDN + EOT */ -#define MAXNUMIDX 170 /* Maximum number of indexes */ +#define MAXNUMIDX 170 /* Maximum number of indices */ #define IDXSIZE (MAXNUMIDX + 1) #define MAXNUMPORTS (6 + 1) /* Maximum number of Super I/O ports */ +/* Select registers for various components. */ +#define LDN_SEL 0x07 /* LDN select register */ +#define WINBOND_HWM_SEL 0x4e /* Hardware monitor bank select */ + /* Command line parameters. */ extern int dump, verbose, extra_dump; @@ -102,7 +106,7 @@ const char *get_superio_name(const struct superio_registers reg_table[], uint16_t id); void dump_superio(const char *name, const struct superio_registers reg_table[], - uint16_t port, uint16_t id); + uint16_t port, uint16_t id, uint8_t ldn_sel); void probing_for(const char *vendor, const char *info, uint16_t port); void print_vendor_chips(const char *vendor, const struct superio_registers reg_table[]); Modified: trunk/util/superiotool/winbond.c =================================================================== --- trunk/util/superiotool/winbond.c 2008-11-30 14:52:46 UTC (rev 3783) +++ trunk/util/superiotool/winbond.c 2008-12-01 14:18:57 UTC (rev 3784) @@ -468,6 +468,55 @@ {EOT} }; +static const struct superio_registers hwm_table[] = { + {0x828, "W83627THF/THG", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x1e,0x1f, + 0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, + 0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31,0x32,0x33,0x34, + 0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e, + 0x3f, + 0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49, + 0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,EOT}, + {RSVD,0xff,RSVD,0xff,0x00,0x00,0x00,0x00,0x01,0x01, + 0x01,0x01,0x3c,0x3c,0x0a,0x0a,RSVD,0xff,0x00,0x00, + 0x00,0x01,0x01,0x3c,0x43,RSVD,0xff,0xff,RSVD,RSVD, + NANA,NANA, + NANA,NANA,NANA,NANA,NANA,RSVD,RSVD,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + RSVD,RSVD,RSVD,RSVD,NANA,NANA,NANA,NANA,NANA,RSVD, + RSVD, + 0x03,0x00,0x00,0xfe,0xff,RSVD,RSVD,0x5f,NANA,0x03, + RSVD,0x44,0x18,0x15,0x80,0x5c,EOT}}, + {0x0, "Bank 0", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5d,0x5e,0x5f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,0x00,0x80,0x90,0x70, + 0x00,RSVD,RSVD,EOT}}, + {0x1, "Bank 1", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT}, + {NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}}, + {0x2, "Bank 2", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT}, + {NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}}, + {0x4, "Bank 4", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x59,0x5a, + 0x5b,EOT}, + {0x00,0xff,RSVD,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,EOT}}, + {0x5, "Bank 5", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,EOT}, + {NANA,NANA,RSVD,RSVD,NANA,NANA,NANA,NANA,EOT}}, + {0x6, "Bank 6", + {0x50,EOT}, + {RSVD,EOT}}, + {EOT}}}, + {EOT} +}; + static void enter_conf_mode_winbond_88(uint16_t port) { OUTB(0x88, port); @@ -486,7 +535,7 @@ static void probe_idregs_winbond_helper(const char *init, uint16_t port) { - uint16_t id; + uint16_t id, hwmport; uint8_t devid, rev, olddevid; probing_for("Winbond", init, port); @@ -522,7 +571,27 @@ get_superio_name(reg_table, id), devid, rev, port); chip_found = 1; - dump_superio("Winbond", reg_table, port, id); + dump_superio("Winbond", reg_table, port, id, LDN_SEL); + + if (extra_dump) { + regwrite(port, LDN_SEL, 0x0b); /* Select LDN 0xb (HWM). */ + + if ((regval(port, 0x30) & (1 << 0)) != (1 << 0)) { + printf("Hardware Monitor disabled or does not exist.\n"); + return; + } + + /* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */ + hwmport = regval(port, 0x60) << 8; + hwmport |= regval(port, 0x61); + + /* HWM address register = HWM base address + 5. */ + hwmport += 5; + + printf("Hardware monitor (0x%04x)\n", hwmport); + dump_superio("Winbond-HWM", hwm_table, hwmport, id, + WINBOND_HWM_SEL); + } } void probe_idregs_winbond(uint16_t port) @@ -547,4 +616,5 @@ void print_winbond_chips(void) { print_vendor_chips("Winbond", reg_table); + print_vendor_chips("Winbond-HWM", hwm_table); }

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[RFC] flashrom: sector-based flashing
by Carl-Daniel Hailfinger 01 Dec '08

01 Dec '08

Hi, flashrom hasn't seen any major design changes in the last few months and most chips still perform whole-chip erase instead of sector-based erase. I'd like to introduce a function which takes a range and rounds the start and the end of the range to the nearest block boundary. void roundup(struct flashchip *flash, int *startpos, int *endpos); Take an example 256 kByte flash chip with the following sector layout: 0x00000-0x0ffff 64kB block 0x10000-0x1ffff 64kB block 0x20000-0x2ffff 64kB block 0x30000-0x37fff 32kB block 0x38000-0x3bfff 16kB block 0x3c000-0x3dfff 8kB block 0x3e000-0x3efff 4kB block 0x3f000-0x3ffff 4kB block startpos=0x38123; endpos=0x3e005; roundup(flash, &startpos, &endpos); //results follow: //startpos=0x38000; //endpos=0x3efff; That way, it is easily possible to check whether a given range can be handled by sector-based erase and write. You can use that result to tell the user that a range outside the intended range will get flashed. It is also possible to refuse flashing in that case. Since the function will be generic and take a struct flashchip, there's no need to store a pointer to it with each chip and you can call the generic one from anywhere. What do you think? Regards, Carl-Daniel -- http://www.hailfinger.org/

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coreboot December 2008