coreboot December 2008

coreboot@coreboot.org

77 participants
330 discussions

fix VT8237S/K8M890 powernow
by Rudolf Marek 07 Dec '08

07 Dec '08

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello all, I finally got the powernow working after countless hours. And CPU runs fullspeed after power up! The patch changes the LDTSTOP length as well mostly default content of 0xec, 0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong. Furthermore this fix for powernow may not work on CPUs hit by errata #181. Workaround should be implemented. The powernow may not work on pre-A2 revisions of VT8237S silicon, revision reg is unknown. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkk4ZfwACgkQ3J9wPJqZRNXv6QCeLPi9cX3OM9v/V/RoABUUJNcL txkAn1nz4yCEQyFZC6quJ1GwvUStmozQ =UKX4 -----END PGP SIGNATURE-----

3 3

Re: [coreboot] r1065 - in coreboot-v3: arch/x86 mainboard/kontron mainboard/kontron/986lcd-m
by Peter Stuge 06 Dec '08

06 Dec '08

svn(a)coreboot.org wrote: > + $(Q)cd $(obj) && ./util/lar/lar -e $(COMPRESSFLAG) -a $(obj)/coreboot.rom $(SMM):normal/smm; normal/smm vs. blob/vsa - should one of them be changed? //Peter

3 2

[PATCH] LAR: Don't clobber top 8 bytes
by Carl-Daniel Hailfinger 06 Dec '08

06 Dec '08

LAR currently overwrites the top 13 bytes (0xfffff3-0xffffff) of the bootblock with zeros, then it stores the ROM size in 0xfffff4-0xfffff7. The top 8 bytes are unused in that scheme. Leave the top 8 bytes as they are and allow us to store something in there during the bootblock build process. The byte at 0xfffff3 is 0xff by default on x86 and setting it to 0 is not needed. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-lar_dont_erase_top_8_bytes/util/lar/stream.c =================================================================== --- corebootv3-lar_dont_erase_top_8_bytes/util/lar/stream.c (Revision 1061) +++ corebootv3-lar_dont_erase_top_8_bytes/util/lar/stream.c (Arbeitskopie) @@ -245,8 +245,9 @@ } /** - * Add the LAR archive size to the bootblock, and clean up some other params - * in what we're loosely calling the "bootblockh header" + * Add the LAR archive size to the bootblock at 0xfffffff4 + * in what we're loosely calling the "bootblock header". + * Leave anything else alone. * @param ptr Pointer to the start of the bootblock * @param size The size value to write to the bootblock header */ @@ -255,7 +256,6 @@ int i; u32 *p; - memset(ptr + (BOOTBLOCK_SIZE - 13), 0, 13); p = (u32 *) (ptr + BOOTBLOCK_SIZE - 12); p[0] = size; } -- http://www.hailfinger.org/

6 11

patch: smm support
by ron minnich 06 Dec '08

06 Dec '08

attached. ron

3 3

r1065 - in coreboot-v3: arch/x86 mainboard/kontron mainboard/kontron/986lcd-m
by svn＠coreboot.org 06 Dec '08

06 Dec '08

Author: rminnich Date: 2008-12-06 04:59:24 +0100 (Sat, 06 Dec 2008) New Revision: 1065 Modified: coreboot-v3/arch/x86/Kconfig coreboot-v3/arch/x86/Makefile coreboot-v3/mainboard/kontron/986lcd-m/Makefile coreboot-v3/mainboard/kontron/986lcd-m/mainboard.h coreboot-v3/mainboard/kontron/Kconfig Log: Add support for creating an smm top-level object. Whether SMM is added or not depends on the mainboard. To enable SMM, the Kconfig variable SMM should be set, and the SMM variable should be defined in the mainbard. Also correct a type CONFIG_HPET should be HPET. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/arch/x86/Kconfig =================================================================== --- coreboot-v3/arch/x86/Kconfig 2008-12-03 23:39:49 UTC (rev 1064) +++ coreboot-v3/arch/x86/Kconfig 2008-12-06 03:59:24 UTC (rev 1065) @@ -72,13 +72,21 @@ arch/x86/Makefile for more hints on possible values. It is usually set in mainboard/*/Kconfig. -config CONFIG_HPET +config HPET boolean depends CPU_AMD_K8 help Whether to configure a High Precision Event Timer (HPET). Note that HPETs are known to be bug-prone. +config SMM + boolean + help + Whether to configure System Management Mode support. + This is mainboard-enabled. This is a tricky option that + should not be enabled/disabled casually, as some chipsets + will not work without some form of SMM enabled. + config K8_REV_F_SUPPORT hex default 0 if CPU_AMD_K8 Modified: coreboot-v3/arch/x86/Makefile =================================================================== --- coreboot-v3/arch/x86/Makefile 2008-12-03 23:39:49 UTC (rev 1064) +++ coreboot-v3/arch/x86/Makefile 2008-12-06 03:59:24 UTC (rev 1065) @@ -48,7 +48,7 @@ COMPRESSFLAG := -C nrv2b endif -$(obj)/coreboot.rom $(obj)/coreboot.map: $(obj)/coreboot.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/coreboot.initram $(obj)/coreboot.stage2 $(obj)/option_table +$(obj)/coreboot.rom $(obj)/coreboot.map: $(obj)/coreboot.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/coreboot.initram $(obj)/coreboot.stage2 $(obj)/option_table $(SMM) $(Q)printf " LAR $(subst $(shell pwd)/,,$(@))\n" $(Q)rm -f $(obj)/coreboot.rom $(Q)cd $(obj) && \ @@ -74,6 +74,10 @@ $(Q)printf " ZEROING lar -z ./coreboot.rom\n" $(Q)cd $(obj) && ./util/lar/lar -z ./coreboot.rom endif +ifeq ($(CONFIG_SMM),y) + $(Q)printf " Adding smm.elf\n" + $(Q)cd $(obj) && ./util/lar/lar -e $(COMPRESSFLAG) -a $(obj)/coreboot.rom $(SMM):normal/smm; +endif $(Q)# QEMU wants bios.bin: $(Q)# Run "qemu -L build/ -serial stdio -hda /dev/zero". $(Q)printf " CP $(subst $(shell pwd)/,,$(obj)/bios.bin)\n" Modified: coreboot-v3/mainboard/kontron/986lcd-m/Makefile =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/Makefile 2008-12-03 23:39:49 UTC (rev 1064) +++ coreboot-v3/mainboard/kontron/986lcd-m/Makefile 2008-12-06 03:59:24 UTC (rev 1065) @@ -35,3 +35,4 @@ $(Q)printf " BUILD DUMMY VPD\n" $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) +SMM := $(obj)/southbridge/intel/i82801gx/smm.elf Modified: coreboot-v3/mainboard/kontron/986lcd-m/mainboard.h =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/mainboard.h 2008-12-03 23:39:49 UTC (rev 1064) +++ coreboot-v3/mainboard/kontron/986lcd-m/mainboard.h 2008-12-06 03:59:24 UTC (rev 1065) @@ -31,3 +31,5 @@ /* nowhere else to go yet */ #define TEST_SMM_FLASH_LOCKDOWN 0 +#define TTYS0_BASE 0x3f8 + Modified: coreboot-v3/mainboard/kontron/Kconfig =================================================================== --- coreboot-v3/mainboard/kontron/Kconfig 2008-12-03 23:39:49 UTC (rev 1064) +++ coreboot-v3/mainboard/kontron/Kconfig 2008-12-06 03:59:24 UTC (rev 1065) @@ -32,6 +32,7 @@ select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627THG select PIRQ_TABLE + select SMM help Kontron 986LCD-M Series mainboards

1 0

qemu floppy filo or ...
by ron minnich 06 Dec '08

06 Dec '08

So, has anybody tried to boot a floppy i qemu lately? Just had a request. I'm not even sure how to proceed. ron

4 4

#107: flashrom: Display test status in -L chip listing
by coreboot 06 Dec '08

06 Dec '08

#107: flashrom: Display test status in -L chip listing ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: minor | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: testing | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/107> coreboot <http://www.coreboot.org/>

3 6

r3803 - trunk/util/flashrom
by svn＠coreboot.org 06 Dec '08

06 Dec '08

Author: stuge Date: 2008-12-06 02:37:09 +0100 (Sat, 06 Dec 2008) New Revision: 3803 Modified: trunk/util/flashrom/flashrom.c Log: flashrom: Display test status in -L chip listing Looks like this: Supported flash chips: Tested OK operations: Known BAD operations: AMD Am29F002(N)BB AMD Am29F002(N)BT PROBE READ ERASE WRITE AMD Am29F016D AMD Am29F040B PROBE READ ERASE WRITE AMD Am29LV040B Atmel AT45CS1282 READ Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/flashrom.c =================================================================== --- trunk/util/flashrom/flashrom.c 2008-12-05 22:38:18 UTC (rev 3802) +++ trunk/util/flashrom/flashrom.c 2008-12-06 01:37:09 UTC (rev 3803) @@ -205,14 +205,61 @@ return 0; } +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define POS_PRINT(x) do { pos += strlen(x); printf(x); } while (0) + void print_supported_chips(void) { - int i; + int okcol = 0, pos = 0; + struct flashchip *f; - printf("Supported ROM chips:\n\n"); + for (f = flashchips; f->name != NULL; f++) { + if (GENERIC_DEVICE_ID == f->model_id) + continue; + okcol = MAX(okcol, strlen(f->vendor) + 1 + strlen(f->name)); + } + okcol = (okcol + 7) & ~7; - for (i = 0; flashchips[i].name != NULL; i++) - printf("%s %s\n", flashchips[i].vendor, flashchips[i].name); + POS_PRINT("Supported flash chips:"); + while (pos < okcol) { + printf("\t"); + pos += 8 - (pos % 8); + } + printf("Tested OK operations:\tKnown BAD operations:\n\n"); + + for (f = flashchips; f->name != NULL; f++) { + printf("%s %s", f->vendor, f->name); + pos = strlen(f->vendor) + 1 + strlen(f->name); + while (pos < okcol) { + printf("\t"); + pos += 8 - (pos % 8); + } + if ((f->tested & TEST_OK_MASK)) { + if ((f->tested & TEST_OK_PROBE)) + POS_PRINT("PROBE "); + if ((f->tested & TEST_OK_READ)) + POS_PRINT("READ "); + if ((f->tested & TEST_OK_ERASE)) + POS_PRINT("ERASE "); + if ((f->tested & TEST_OK_WRITE)) + POS_PRINT("WRITE"); + } + while (pos < okcol + 24) { + printf("\t"); + pos += 8 - (pos % 8); + } + if ((f->tested & TEST_BAD_MASK)) { + if ((f->tested & TEST_BAD_PROBE)) + printf("PROBE "); + if ((f->tested & TEST_BAD_READ)) + printf("READ "); + if ((f->tested & TEST_BAD_ERASE)) + printf("ERASE "); + if ((f->tested & TEST_BAD_WRITE)) + printf("WRITE"); + } + printf("\n"); + } } void usage(const char *name)

1 0

AMD MCT fixes
by Stefan Reinauer 05 Dec '08

05 Dec '08

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Fixes to AMD MCT code, found by Marco Schmidt <mschmidt(a)dspace.de> Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: src/northbridge/amd/amdmct/mct/mct_d.c =================================================================== --- src/northbridge/amd/amdmct/mct/mct_d.c (revision 3796) +++ src/northbridge/amd/amdmct/mct/mct_d.c (working copy) @@ -3400,6 +3400,8 @@ u8 max_dimms; // FIXME: skip for Ax + + dev = pDCTstat->dev_dct; /* Tri-state unused ODTs when motherboard termination is available */ max_dimms = (u8) mctGet_NVbits(NV_MAX_DIMMS); Index: src/northbridge/amd/amdmct/wrappers/mcti_d.c =================================================================== --- src/northbridge/amd/amdmct/wrappers/mcti_d.c (revision 3796) +++ src/northbridge/amd/amdmct/wrappers/mcti_d.c (working copy) @@ -197,13 +197,16 @@ case NV_CS_SpareCTL: val = 0; /* Disabled */ //val = 1; /* Enabled */ + break; case NV_SyncOnUnEccEn: val = 0; /* Disabled */ //val = 1; /* Enabled */ + break; case NV_Unganged: /* channel interleave is better performance than ganged mode at this time */ val = 1; /* Enabled */ //val = 0; /* Disabled */ + break; case NV_ChannelIntlv: val = 5; /* Not currently checked in mctchi_d.c */ /* Bit 0 = 0 - Disable @@ -213,7 +216,7 @@ * 10b - Hash*, XOR of address bits [20:16, 6] * 11b - Hash*, XOR of address bits [20:16, 9] */ - + break; } return val;

2 2

r3802 - in trunk/coreboot-v2/src/northbridge/amd/amdmct: mct wrappers
by svn＠coreboot.org 05 Dec '08

05 Dec '08

Author: stepan Date: 2008-12-05 23:38:18 +0100 (Fri, 05 Dec 2008) New Revision: 3802 Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c Log: Fixes to AMD MCT code, found by Marco Schmidt <mschmidt(a)dspace.de> Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c 2008-12-05 18:38:57 UTC (rev 3801) +++ trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c 2008-12-05 22:38:18 UTC (rev 3802) @@ -3400,6 +3400,8 @@ u8 max_dimms; // FIXME: skip for Ax + + dev = pDCTstat->dev_dct; /* Tri-state unused ODTs when motherboard termination is available */ max_dimms = (u8) mctGet_NVbits(NV_MAX_DIMMS); Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c 2008-12-05 18:38:57 UTC (rev 3801) +++ trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c 2008-12-05 22:38:18 UTC (rev 3802) @@ -197,13 +197,16 @@ case NV_CS_SpareCTL: val = 0; /* Disabled */ //val = 1; /* Enabled */ + break; case NV_SyncOnUnEccEn: val = 0; /* Disabled */ //val = 1; /* Enabled */ + break; case NV_Unganged: /* channel interleave is better performance than ganged mode at this time */ val = 1; /* Enabled */ //val = 0; /* Disabled */ + break; case NV_ChannelIntlv: val = 5; /* Not currently checked in mctchi_d.c */ /* Bit 0 = 0 - Disable @@ -213,7 +216,7 @@ * 10b - Hash*, XOR of address bits [20:16, 6] * 11b - Hash*, XOR of address bits [20:16, 9] */ - + break; } return val;

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coreboot December 2008