coreboot December 2008

coreboot@coreboot.org

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330 discussions

HT reset hang on 690G/SB600 board Asus M2A-VM
by Carl-Daniel Hailfinger 11 Dec '08

11 Dec '08

Hi! I'm trying to get coreboot v2 running on my Asus M2A-VM. It is very similar to the AMD DBM690T. It has a 690G/SB600 chipset and an IT8716F SuperIO. My codebase is a slightly modified amd/dbm690t target. I only changed the CPU socket to AM2. coreboot-2.0.0.0-failover Do 11. Dez 01:16:13 CET 2008 starting... bsp_apicid=0x0 core0 started: SBLink=00 NC node|link=00 rs690_early_setup() get_cpu_rev EAX=0x50ff2. CPU Rev is K8_G0. NB Revision is A12. rs690_ht_init k8_ht_freq=0. k8_optimization() rs690_por_init sb600_early_setup() sb600_devices_por_init() sb600_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is 0x13 sb600_devices_por_init(): IDE Device, BDF:0-20-1 sb600_devices_por_init(): LPC Device, BDF:0-20-3 sb600_devices_por_init(): P2P Bridge, BDF:0-20-4 sb600_devices_por_init(): SATA Device, BDF:0-18-0 sb600_pmio_por_init() begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202 Current fid_cur: 0x2, fid_max: 0xa Requested fid_new: 0xa FidVid table step fidvid: 0xa end msr fid, vid: hi=0x310a120a, lo=0xa0a020a needs_reset=0x1 ht reset - It hangs after that soft reset. No POST code, nothing else. Any insights are appreciated. Processor info follows: hilbert:~ # cat /proc/cpuinfo processor : 0 vendor_id : AuthenticAMD cpu family : 15 model : 95 model name : AMD Athlon(tm) 64 Processor 3000+ stepping : 2 cpu MHz : 1800.000 cache size : 512 KB fpu : yes fpu_exception : yes cpuid level : 1 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx mmxext fxsr_opt rdtscp lm 3dnowext 3dnow rep_good pni cx16 lahf_lm svm extapic cr8_legacy bogomips : 3602.72 TLB size : 1024 4K pages clflush size : 64 cache_alignment : 64 address sizes : 40 bits physical, 48 bits virtual power management: ts fid vid ttp tm stc Regards, Carl-Daniel -- http://www.hailfinger.org/

5 12

[PATCH][v3] Check that CAR and ROM areas don't collide
by Corey Osgood 11 Dec '08

11 Dec '08

include/arch/x86/cpu.h is probably not the best place for this, but AFAIK it should be included by and work for all possible targets. Another possible solution is something like this, I don't think I like it as well, and it fails the KISS test IMO: mainboard/Kconfig: config COREBOOT_ROMSIZE_KB_128 bool "128 KB" depends (0xffffffff - (128 * 1024) > (CONFIG_CARBASE + CONFIG_CARSIZE))) help Choose this option if you have a 128 KB ROM chip. -Corey

4 12

r1071 - coreboot-v3/include/arch/x86
by svn＠coreboot.org 11 Dec '08

11 Dec '08

Author: cozzie Date: 2008-12-11 07:33:29 +0100 (Thu, 11 Dec 2008) New Revision: 1071 Modified: coreboot-v3/include/arch/x86/cpu.h Log: Check that the CAR and ROM areas don't collide. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/include/arch/x86/cpu.h =================================================================== --- coreboot-v3/include/arch/x86/cpu.h 2008-12-10 21:23:09 UTC (rev 1070) +++ coreboot-v3/include/arch/x86/cpu.h 2008-12-11 06:33:29 UTC (rev 1071) @@ -26,7 +26,15 @@ #include <device/device.h> #include <shared.h> #include <mtrr.h> +#include <config.h> +/* Check that the CAR and ROM areas aren't going to collide */ +#if ((0x100000000 - (CONFIG_COREBOOT_ROMSIZE_KB * 1024)) < (CONFIG_CARBASE + CONFIG_CARSIZE)) +#error Your current Cache-As-Ram base does not allow room to map the selected\ + chip size to memory. Please select a different chip size or move the CAR\ + base to another sane location. +#endif + #define X86_VENDOR_INTEL 0 #define X86_VENDOR_CYRIX 1 #define X86_VENDOR_AMD 2

1 0

The name is wrong in news about AMD Pistachio support in coreboot page:
by Li, Maggie 11 Dec '08

11 Dec '08

Hi, It should be “pistachio”, not “pistacio”. Best regards Maggie li

2 1

[PATCH] early_mtrr_init is broken, comment it out
by Carl-Daniel Hailfinger 10 Dec '08

10 Dec '08

early_mtrr_init() nukes all MTRRs including those which we use for CAR. That means if it ever gets called while CAR is active, our stack will be dropped and mayhem will ensue. Besides that, it just replicated stage0.S functionality which already nukes all MTRRs before enabling CAR. We could move XIP ROM caching from stage0.S to early_mtrr_init(). It would probably slow down booting a bit, but the amount of asm code would be reduced. Thanks to Corey for telling me that early_mtrr_init() broke booting for him. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-kill_early_mtrr_init/arch/x86/stage1_mtrr.c =================================================================== --- corebootv3-kill_early_mtrr_init/arch/x86/stage1_mtrr.c (Revision 1066) +++ corebootv3-kill_early_mtrr_init/arch/x86/stage1_mtrr.c (Arbeitskopie) @@ -67,6 +67,11 @@ enable_cache(); } +/* early_mtrr_init was only usable for ROMCC compiled code. It nukes CAR. + * The only remaining purpose would be to enable ROM caching here instead of + * in stage0.S and even that is debatable. + */ +#if 0 /* the fixed and variable MTTRs are power-up with random values, * clear them to MTRR_TYPE_UNCACHEABLE for safty. */ @@ -130,6 +135,7 @@ do_early_mtrr_init(mtrr_msrs); enable_cache(); } +#endif int early_mtrr_init_detected(void) { -- http://www.hailfinger.org/

3 3

v3 cn700 patch dump
by Corey Osgood 10 Dec '08

10 Dec '08

Attached is the net result of what I've done to try to figure out what's going on with the cn700, right now it reboots part of the way through initram, probably as a result of the GP3 timer not getting reset like it should. I'm heading into finals week, so I probably won't be able to get back to this until late December. -Corey

4 9

r1070 - in coreboot-v3: include/arch/x86 mainboard/jetway/j7f2 mainboard/via/epia-cn northbridge/via/cn700 southbridge/via/vt8237 superio/via/vt1211
by svn＠coreboot.org 10 Dec '08

10 Dec '08

Author: cozzie Date: 2008-12-10 22:23:09 +0100 (Wed, 10 Dec 2008) New Revision: 1070 Added: coreboot-v3/northbridge/via/cn700/stage1.c Modified: coreboot-v3/include/arch/x86/mtrr.h coreboot-v3/mainboard/jetway/j7f2/Makefile coreboot-v3/mainboard/jetway/j7f2/initram.c coreboot-v3/mainboard/jetway/j7f2/stage1.c coreboot-v3/mainboard/via/epia-cn/Makefile coreboot-v3/mainboard/via/epia-cn/initram.c coreboot-v3/mainboard/via/epia-cn/stage1.c coreboot-v3/northbridge/via/cn700/cn700.h coreboot-v3/northbridge/via/cn700/initram.c coreboot-v3/southbridge/via/vt8237/ide.c coreboot-v3/southbridge/via/vt8237/lpc.c coreboot-v3/southbridge/via/vt8237/sata.c coreboot-v3/southbridge/via/vt8237/stage1.c coreboot-v3/southbridge/via/vt8237/vt8237.h coreboot-v3/superio/via/vt1211/vt1211.h Log: This patch: * Moves non-DRAM early init code out of initram and into stage1, where it should have been in the first place * Fixes an issue with GP3 timer causing system reboot (possibly not present in current svn, but was present in my local copy) * Fixes serial garbage from stage1 on jetway j7f2 * Fixes ROM mapping for flash > 512k on vt8237 * Makes a couple minor whitespace changes * Moves some function prototypes to the headers where they belong * Nukes some phase2 hackery that belongs in phase4 (eventually) * Comments out early_mtrr_init() for via/epia-cn, this breaks booting on jetway j7f2 * Moves troublesome SATA init code into stage1 - change of device class hangs coreboot * Gets to vt8237 IDE phase6 init and dies on jetway/j7f2: Phase 6: Initializing devices... Phase 6: Root Device init. Phase 6: PCI: 00:10.1 init. Primary IDE interface enabled Secondary IDE interface enabled <hang> Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/include/arch/x86/mtrr.h =================================================================== --- coreboot-v3/include/arch/x86/mtrr.h 2008-12-10 19:07:16 UTC (rev 1069) +++ coreboot-v3/include/arch/x86/mtrr.h 2008-12-10 21:23:09 UTC (rev 1070) @@ -35,6 +35,7 @@ void x86_setup_var_mtrrs(unsigned address_bits); void x86_setup_mtrrs(unsigned address_bits); int x86_mtrr_check(void); +void early_mtrr_init(void); #endif Modified: coreboot-v3/mainboard/jetway/j7f2/Makefile =================================================================== --- coreboot-v3/mainboard/jetway/j7f2/Makefile 2008-12-10 19:07:16 UTC (rev 1069) +++ coreboot-v3/mainboard/jetway/j7f2/Makefile 2008-12-10 21:23:09 UTC (rev 1070) @@ -21,11 +21,12 @@ ## TODO STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ + $(src)/northbridge/via/cn700/stage1.c \ + $(src)/southbridge/via/vt8237/stage1.c \ $(src)/arch/x86/stage1_mtrr.c INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/via/cn700/initram.c \ - $(src)/southbridge/via/vt8237/stage1.c \ $(src)/lib/ramtest.c \ $(src)/arch/x86/pci_ops_conf1.c Modified: coreboot-v3/mainboard/jetway/j7f2/initram.c =================================================================== --- coreboot-v3/mainboard/jetway/j7f2/initram.c 2008-12-10 19:07:16 UTC (rev 1069) +++ coreboot-v3/mainboard/jetway/j7f2/initram.c 2008-12-10 21:23:09 UTC (rev 1070) @@ -22,13 +22,9 @@ #include <types.h> #include <lib.h> #include <console.h> -#include <io.h> #include <spd.h> -#include <via_c7.h> #include <arch/x86/pci_ops.h> #include <device/pci.h> -#include <device/pci_ids.h> -#include <superio/fintek/f71805f/f71805f.h> #include <southbridge/via/vt8237/vt8237.h> #include <northbridge/via/cn700/cn700.h> @@ -65,7 +61,7 @@ void dump_smbus_registers(void) { int device; - for(device = 1; device < (int)0x80; device++) { + for(device = (int)0x50; device < (int)0x52; device++) { int j; //if(spd_read_byte(device, 0) < 0 ) // continue; @@ -87,100 +83,9 @@ } } -static void enable_mainboard_devices(void) -{ - u32 dev; - - pci_conf1_find_device(0x1106, 0x3227, &dev); - /* Disable GP3 */ - pci_conf1_write_config8(dev, 0x98, 0x00); - - pci_conf1_write_config8(dev, 0x50, 0x88);//disable mc97, sata - pci_conf1_write_config8(dev, 0x51, 0x1f); - pci_conf1_write_config8(dev, 0x58, 0x60); - pci_conf1_write_config8(dev, 0x59, 0x80); - pci_conf1_write_config8(dev, 0x5b, 0x08); - - pci_conf1_find_device(0x1106, 0x0571, &dev); - - /* Make it respond to IO space */ - pci_conf1_write_config8(dev, 0x04, 0x07); - - /* Compatibility mode addresses */ - //pci_conf1_write_config32(dev, 0x10, 0); - //pci_conf1_write_config32(dev, 0x14, 0); - //pci_conf1_write_config32(dev, 0x18, 0); - //pci_conf1_write_config32(dev, 0x1b, 0); - - /* Native mode base address */ - //pci_conf1_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1); - - pci_conf1_write_config8(dev, 0x40, 0x4b);//was 0x3 - pci_conf1_write_config8(dev, 0x41, 0xf2); - pci_conf1_write_config8(dev, 0x42, 0x09); - /* I'll be damned if I know what these do */ - pci_conf1_write_config8(dev, 0x3c, 0xff);//was 0x0e - pci_conf1_write_config8(dev, 0x3d, 0x00);//was 0x00 -} - -static void enable_shadow_ram(void) -{ - u8 shadowreg; - - printk(BIOS_DEBUG, "Enabling shadow ram\n"); - /* Enable shadow ram as normal dram */ - /* 0xc0000-0xcffff */ - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff); - /* 0xd0000-0xdffff */ - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff); - /* 0xe0000-0xeffff */ - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff); - - /* 0xf0000-0xfffff */ - shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83); - shadowreg |= 0x30; - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg); - - /* Do it again for the vlink controller */ - shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63); - shadowreg |= 0x30; - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg); -} - -static void enable_vlink(void) -{ - printk(BIOS_DEBUG, "Enabling Via V-Link\n"); - - /* Enable V-Link statically in 8x mode, using Jetway default values */ -//40: 14 19 88 80 82 44 00 04 13 b9 88 80 82 44 00 01 - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04); - //pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01); -//b0: 05 01 00 83 35 66 66 64 45 98 77 11 00 00 00 00 - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77); - - /* This has to be done last, I think */ - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); -} - int main(void) { + /* TODO: Kill off this struct, like Uwe's doing in v2 */ struct board_info ctrl[] = { { .d0f2 = PCI_BDF(0, 0, 2), @@ -194,14 +99,7 @@ printk(BIOS_DEBUG, "In initram.c main()\n"); - enable_vlink(); - enable_mainboard_devices(); - enable_shadow_ram(); - - c7_cpu_setup(PCI_BDF(0, 0, 2)); - - enable_smbus(SMBUS_IO_BASE); - //find_smbus_devices(0x00, 0xff); + //dump_smbus_registers(); sdram_set_registers(ctrl); sdram_set_spd_registers(ctrl); ddr2_sdram_enable(ctrl); Modified: coreboot-v3/mainboard/jetway/j7f2/stage1.c =================================================================== --- coreboot-v3/mainboard/jetway/j7f2/stage1.c 2008-12-10 19:07:16 UTC (rev 1069) +++ coreboot-v3/mainboard/jetway/j7f2/stage1.c 2008-12-10 21:23:09 UTC (rev 1070) @@ -19,33 +19,27 @@ */ #include <types.h> -#include <lib.h> #include <console.h> -#include <io.h> -#include <arch/x86/pci_ops.h> +#include <arch/x86/mtrr.h> +#include <arch/x86/legacy.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <superio/fintek/f71805f/f71805f.h> #include <northbridge/via/cn700/cn700.h> +#include <southbridge/via/vt8237/vt8237.h> +#define SMBUS_IO_BASE 0x0400 + void hardware_stage1(void) { - u32 dev; - post_code(POST_START_OF_MAIN); f71805f_enable_serial(0x2e); - - /* Enable multifunction for northbridge. */ - pci_conf1_write_config8(0x00, 0x4f, 0x01); + uart_init(); printk(BIOS_SPEW, "In hardware_stage1()\n"); - /* Disabled GP3, to keep the system from rebooting automatically */ - //pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VT8237R_LPC, &dev); - dev = PCI_BDF(0, 17, 0); - pci_conf1_write_config8(dev, 0x98, 0x00); + cn700_stage1(); + vt8237_stage1(SMBUS_IO_BASE); } void mainboard_pre_payload(void) { - //banner(BIOS_DEBUG, "mainboard_pre_payload: done"); } Modified: coreboot-v3/mainboard/via/epia-cn/Makefile =================================================================== --- coreboot-v3/mainboard/via/epia-cn/Makefile 2008-12-10 19:07:16 UTC (rev 1069) +++ coreboot-v3/mainboard/via/epia-cn/Makefile 2008-12-10 21:23:09 UTC (rev 1070) @@ -20,11 +20,12 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \ $(src)/arch/x86/stage1_mtrr.c \ - $(src)/mainboard/$(MAINBOARDDIR)/stage1.c + $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ + $(src)/southbridge/via/vt8237/stage1.c \ + $(src)/northbridge/via/cn700/stage1.c \ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/via/cn700/initram.c \ - $(src)/southbridge/via/vt8237/stage1.c \ $(src)/lib/ramtest.c STAGE2_MAINBOARD_SRC = Modified: coreboot-v3/mainboard/via/epia-cn/initram.c =================================================================== --- coreboot-v3/mainboard/via/epia-cn/initram.c 2008-12-10 19:07:16 UTC (rev 1069) +++ coreboot-v3/mainboard/via/epia-cn/initram.c 2008-12-10 21:23:09 UTC (rev 1070) @@ -22,12 +22,9 @@ #include <types.h> #include <lib.h> #include <console.h> -#include <io.h> #include <spd.h> -#include <via_c7.h> #include <arch/x86/pci_ops.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <superio/via/vt1211/vt1211.h> #include <southbridge/via/vt8237/vt8237.h> #include <northbridge/via/cn700/cn700.h> @@ -87,98 +84,6 @@ } } -static void enable_mainboard_devices(void) -{ - u32 dev; - - pci_conf1_find_device(0x1106, 0x3227, &dev); - /* Disable GP3 */ - pci_conf1_write_config8(dev, 0x98, 0x00); - - pci_conf1_write_config8(dev, 0x50, 0x88);//disable mc97, sata - pci_conf1_write_config8(dev, 0x51, 0x1f); - pci_conf1_write_config8(dev, 0x58, 0x60); - pci_conf1_write_config8(dev, 0x59, 0x80); - pci_conf1_write_config8(dev, 0x5b, 0x08); - - pci_conf1_find_device(0x1106, 0x0571, &dev); - - /* Make it respond to IO space */ - pci_conf1_write_config8(dev, 0x04, 0x07); - - /* Compatibility mode addresses */ - //pci_conf1_write_config32(dev, 0x10, 0); - //pci_conf1_write_config32(dev, 0x14, 0); - //pci_conf1_write_config32(dev, 0x18, 0); - //pci_conf1_write_config32(dev, 0x1b, 0); - - /* Native mode base address */ - //pci_conf1_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1); - - pci_conf1_write_config8(dev, 0x40, 0x4b);//was 0x3 - pci_conf1_write_config8(dev, 0x41, 0xf2); - pci_conf1_write_config8(dev, 0x42, 0x09); - /* I'll be damned if I know what these do */ - pci_conf1_write_config8(dev, 0x3c, 0xff);//was 0x0e - pci_conf1_write_config8(dev, 0x3d, 0x00);//was 0x00 -} - -static void enable_shadow_ram(void) -{ - u8 shadowreg; - - printk(BIOS_DEBUG, "Enabling shadow ram\n"); - /* Enable shadow ram as normal dram */ - /* 0xc0000-0xcffff */ - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff); - /* 0xd0000-0xdffff */ - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff); - /* 0xe0000-0xeffff */ - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff); - - /* 0xf0000-0xfffff */ - shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83); - shadowreg |= 0x30; - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg); - - /* Do it again for the vlink controller */ - shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63); - shadowreg |= 0x30; - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg); -} - -static void enable_vlink(void) -{ - printk(BIOS_DEBUG, "Enabling Via V-Link\n"); - - /* Enable V-Link statically in 8x mode, using Jetway default values */ -//40: 14 19 88 80 82 44 00 04 13 b9 88 80 82 44 00 01 - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04); - //pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01); -//b0: 05 01 00 83 35 66 66 64 45 98 77 11 00 00 00 00 - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77); - - /* This has to be done last, I think */ - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); -} - int main(void) { struct board_info ctrl[] = { @@ -194,14 +99,6 @@ printk(BIOS_DEBUG, "In initram.c main()\n"); - enable_vlink(); - enable_mainboard_devices(); - enable_shadow_ram(); - - c7_cpu_setup(PCI_BDF(0, 0, 2)); - - enable_smbus(SMBUS_IO_BASE); - //find_smbus_devices(0x00, 0xff); sdram_set_registers(ctrl); sdram_set_spd_registers(ctrl); ddr2_sdram_enable(ctrl); Modified: coreboot-v3/mainboard/via/epia-cn/stage1.c =================================================================== --- coreboot-v3/mainboard/via/epia-cn/stage1.c 2008-12-10 19:07:16 UTC (rev 1069) +++ coreboot-v3/mainboard/via/epia-cn/stage1.c 2008-12-10 21:23:09 UTC (rev 1070) @@ -22,37 +22,28 @@ #include <types.h> #include <lib.h> #include <console.h> -#include <io.h> -#include <arch/x86/pci_ops.h> +#include <arch/x86/mtrr.h> #include <device/pci.h> -#include <device/pci_ids.h> -#include <superio/fintek/f71805f/f71805f.h> #include <northbridge/via/cn700/cn700.h> +#include <southbridge/via/vt8237/vt8237.h> +#include <superio/via/vt1211/vt1211.h> +#define SMBUS_IO_BASE 0x400 + void hardware_stage1(void) { - void early_mtrr_init(void); - void vt1211_enable_serial(u8 dev, u8 serial, u16 iobase); - u32 dev; - post_code(POST_START_OF_MAIN); - /* do this or watch the system run slowly */ - early_mtrr_init(); + /* do this and the system won't run at all */ + //early_mtrr_init(); vt1211_enable_serial(0x2e, 2, 0x3f8); - /* Enable multifunction for northbridge. */ - pci_conf1_write_config8(0x00, 0x4f, 0x01); - printk(BIOS_SPEW, "In hardware_stage1()\n"); - /* Disabled GP3, to keep the system from rebooting automatically */ - //pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VT8237R_LPC, &dev); - dev = PCI_BDF(0, 17, 0); - pci_conf1_write_config8(dev, 0x98, 0x00); + cn700_stage1(); + vt8237_stage1(SMBUS_IO_BASE); } void mainboard_pre_payload(void) { - //banner(BIOS_DEBUG, "mainboard_pre_payload: done"); } Modified: coreboot-v3/northbridge/via/cn700/cn700.h =================================================================== --- coreboot-v3/northbridge/via/cn700/cn700.h 2008-12-10 19:07:16 UTC (rev 1069) +++ coreboot-v3/northbridge/via/cn700/cn700.h 2008-12-10 21:23:09 UTC (rev 1070) @@ -28,7 +28,7 @@ u16 spd_channel0[2]; }; -void c7_cpu_setup(u32); +void cn700_stage1(void); void sdram_set_registers(struct board_info *); void sdram_set_spd_registers(struct board_info *); void ddr2_sdram_enable(struct board_info *); Modified: coreboot-v3/northbridge/via/cn700/initram.c =================================================================== --- coreboot-v3/northbridge/via/cn700/initram.c 2008-12-10 19:07:16 UTC (rev 1069) +++ coreboot-v3/northbridge/via/cn700/initram.c 2008-12-10 21:23:09 UTC (rev 1070) @@ -128,97 +128,6 @@ } /** - * Configure the bus between the cpu and the northbridge. This might be able to - * be moved to post-ram code in the future. For the most part, these registers - * should not be messed around with. These are too complex to explain short of - * copying the datasheets into the comments, but most of these values are from - * the BIOS Porting Guide, so they should work on any board. If they don't, - * try the values from your factory BIOS. - * - * TODO: Changing the DRAM frequency doesn't work (hard lockup) - * - * @param dev The northbridge's CPU Host Interface (D0F2) - */ -void c7_cpu_setup(u32 dev) -{ - /* Host bus interface registers (D0F2 0x50-0x67) */ - /* Request phase control */ - pci_conf1_write_config8(dev, 0x50, 0x88); - /* CPU Interface Control */ - pci_conf1_write_config8(dev, 0x51, 0x7a); - pci_conf1_write_config8(dev, 0x52, 0x6f); - /* Arbitration */ - pci_conf1_write_config8(dev, 0x53, 0x88); - /* Miscellaneous Control */ - pci_conf1_write_config8(dev, 0x54, 0x1e); - pci_conf1_write_config8(dev, 0x55, 0x16); - /* Write Policy */ - pci_conf1_write_config8(dev, 0x56, 0x01); - /* Miscellaneous Control */ - /* DRAM Operating Frequency (bits 7:5 Rx57) - * 000 : 100MHz 001 : 133MHz - * 010 : 166MHz 011 : 200MHz - * 100 : 266MHz 101 : 333MHz - * 110/111 : Reserved - * bits 4:0: Reserved - */ - /* CPU Miscellaneous Control */ - pci_conf1_write_config8(dev, 0x59, 0x44); - /* Write Policy */ - pci_conf1_write_config8(dev, 0x5d, 0xb2); - /* Bandwidth Timer */ - pci_conf1_write_config8(dev, 0x5e, 0x88); - /* CPU Miscellaneous Control */ - pci_conf1_write_config8(dev, 0x5f, 0xc7); - - /* Line DRDY# Timing Control */ - pci_conf1_write_config8(dev, 0x60, 0xff); - pci_conf1_write_config8(dev, 0x61, 0xff); - pci_conf1_write_config8(dev, 0x62, 0x0f); - /* QW DRDY# Timing Control */ - pci_conf1_write_config8(dev, 0x63, 0xff); - pci_conf1_write_config8(dev, 0x64, 0xff); - pci_conf1_write_config8(dev, 0x65, 0x0f); - /* Read Line Burst DRDY# Timing Control */ - pci_conf1_write_config8(dev, 0x66, 0xff); - pci_conf1_write_config8(dev, 0x67, 0x30); - - /* Host Bus I/O Circuit (see datasheet) */ - /* Host Address Pullup/down Driving */ - pci_conf1_write_config8(dev, 0x70, 0x11); - pci_conf1_write_config8(dev, 0x71, 0x11); - pci_conf1_write_config8(dev, 0x72, 0x11); - pci_conf1_write_config8(dev, 0x73, 0x11); - /* Miscellaneous Control */ - pci_conf1_write_config8(dev, 0x74, 0x35); - /* AGTL+ I/O Circuit */ - pci_conf1_write_config8(dev, 0x75, 0x28); - /* AGTL+ Compensation Status */ - pci_conf1_write_config8(dev, 0x76, 0x74); - /* AGTL+ Auto Compensation Offest */ - pci_conf1_write_config8(dev, 0x77, 0x00); - /* Host FSB CKG Control */ - pci_conf1_write_config8(dev, 0x78, 0x0a); - /* Address/Address Clock Output Delay Control */ - pci_conf1_write_config8(dev, 0x79, 0xaa); - /* Address Strobe Input Delay Control */ - pci_conf1_write_config8(dev, 0x7a, 0x24); - /* Address CKG Rising/Falling Time Control */ - pci_conf1_write_config8(dev, 0x7b, 0xaa); - /* Address CKG Clock Rising/Falling Time Control */ - pci_conf1_write_config8(dev, 0x7c, 0x00); - /* Undefined (can't remember why I did this) */ - pci_conf1_write_config8(dev, 0x7d, 0x6d); - - pci_conf1_write_config8(dev, 0x7e, 0x00); - pci_conf1_write_config8(dev, 0x7f, 0x00); - pci_conf1_write_config8(dev, 0x80, 0x1b); - pci_conf1_write_config8(dev, 0x81, 0x0a); - pci_conf1_write_config8(dev, 0x82, 0x0a); - pci_conf1_write_config8(dev, 0x83, 0x0a); -} - -/** * Set up various ram and other control registers statically. Some of these may * not be needed, other should be done with spd info, but that's a project for * the future @@ -353,10 +262,6 @@ pci_conf1_write_config8(dev->d0f3, 0x74, 0x04); pci_conf1_write_config8(dev->d0f3, 0x75, 0x04); pci_conf1_write_config8(dev->d0f3, 0x76, 0x00); - - /* Thanks to Urbez Santana Roma for this */ - pci_conf1_write_config8(dev->d1f0, 0x19, 0x1); - pci_conf1_write_config8(dev->d1f0, 0x1a, 0x1); } /** Added: coreboot-v3/northbridge/via/cn700/stage1.c =================================================================== --- coreboot-v3/northbridge/via/cn700/stage1.c (rev 0) +++ coreboot-v3/northbridge/via/cn700/stage1.c 2008-12-10 21:23:09 UTC (rev 1070) @@ -0,0 +1,185 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <console.h> +#include <device/pci.h> +#include <config.h> +#include "cn700.h" + +static void enable_shadow_ram(void) +{ + u8 shadowreg; + + printk(BIOS_DEBUG, "Enabling shadow ram\n"); + /* Enable shadow ram as normal dram */ + /* 0xc0000-0xcffff */ + pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff); + /* 0xd0000-0xdffff */ + pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff); + /* 0xe0000-0xeffff */ + pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff); + + /* 0xf0000-0xfffff */ + shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83); + shadowreg |= 0x30; + pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg); + + /* Do it again for the vlink controller */ + shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63); + shadowreg |= 0x30; + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg); +} + +static void enable_vlink(void) +{ + printk(BIOS_DEBUG, "Enabling Via V-Link\n"); + + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04); + //pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77); + + /* This has to be done last, I think */ + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); +} + +/** + * Configure the bus between the cpu and the northbridge. This might be able to + * be moved to post-ram code in the future. For the most part, these registers + * should not be messed around with. These are too complex to explain short of + * copying the datasheets into the comments, but most of these values are from + * the BIOS Porting Guide, so they should work on any board. If they don't, + * try the values from your factory BIOS. + * + * TODO: Changing the DRAM frequency doesn't work (hard lockup) + * + * @param dev The northbridge's CPU Host Interface (D0F2) + */ +static void c7_cpu_setup(void) +{ + u32 dev = PCI_BDF(0, 0, 2); + + /* Host bus interface registers (D0F2 0x50-0x67) */ + /* Request phase control */ + pci_conf1_write_config8(dev, 0x50, 0x88); + /* CPU Interface Control */ + pci_conf1_write_config8(dev, 0x51, 0x7a); + pci_conf1_write_config8(dev, 0x52, 0x6f); + /* Arbitration */ + pci_conf1_write_config8(dev, 0x53, 0x88); + /* Miscellaneous Control */ + pci_conf1_write_config8(dev, 0x54, 0x1e); + pci_conf1_write_config8(dev, 0x55, 0x16); + /* Write Policy */ + pci_conf1_write_config8(dev, 0x56, 0x01); + /* Miscellaneous Control */ + /* DRAM Operating Frequency (bits 7:5 Rx57) + * 000 : 100MHz 001 : 133MHz + * 010 : 166MHz 011 : 200MHz + * 100 : 266MHz 101 : 333MHz + * 110/111 : Reserved + * bits 4:0: Reserved + */ + /* CPU Miscellaneous Control */ + pci_conf1_write_config8(dev, 0x59, 0x44); + /* Write Policy */ + pci_conf1_write_config8(dev, 0x5d, 0xb2); + /* Bandwidth Timer */ + pci_conf1_write_config8(dev, 0x5e, 0x88); + /* CPU Miscellaneous Control */ + pci_conf1_write_config8(dev, 0x5f, 0xc7); + + /* Line DRDY# Timing Control */ + pci_conf1_write_config8(dev, 0x60, 0xff); + pci_conf1_write_config8(dev, 0x61, 0xff); + pci_conf1_write_config8(dev, 0x62, 0x0f); + /* QW DRDY# Timing Control */ + pci_conf1_write_config8(dev, 0x63, 0xff); + pci_conf1_write_config8(dev, 0x64, 0xff); + pci_conf1_write_config8(dev, 0x65, 0x0f); + /* Read Line Burst DRDY# Timing Control */ + pci_conf1_write_config8(dev, 0x66, 0xff); + pci_conf1_write_config8(dev, 0x67, 0x30); + + /* Host Bus I/O Circuit (see datasheet) */ + /* Host Address Pullup/down Driving */ + pci_conf1_write_config8(dev, 0x70, 0x11); + pci_conf1_write_config8(dev, 0x71, 0x11); + pci_conf1_write_config8(dev, 0x72, 0x11); + pci_conf1_write_config8(dev, 0x73, 0x11); + /* Miscellaneous Control */ + pci_conf1_write_config8(dev, 0x74, 0x35); + /* AGTL+ I/O Circuit */ + pci_conf1_write_config8(dev, 0x75, 0x28); + /* AGTL+ Compensation Status */ + pci_conf1_write_config8(dev, 0x76, 0x74); + /* AGTL+ Auto Compensation Offest */ + pci_conf1_write_config8(dev, 0x77, 0x00); + /* Host FSB CKG Control */ + pci_conf1_write_config8(dev, 0x78, 0x0a); + /* Address/Address Clock Output Delay Control */ + pci_conf1_write_config8(dev, 0x79, 0xaa); + /* Address Strobe Input Delay Control */ + pci_conf1_write_config8(dev, 0x7a, 0x24); + /* Address CKG Rising/Falling Time Control */ + pci_conf1_write_config8(dev, 0x7b, 0xaa); + /* Address CKG Clock Rising/Falling Time Control */ + pci_conf1_write_config8(dev, 0x7c, 0x00); + /* Undefined (can't remember why I did this) */ + pci_conf1_write_config8(dev, 0x7d, 0x6d); + + pci_conf1_write_config8(dev, 0x7e, 0x00); + pci_conf1_write_config8(dev, 0x7f, 0x00); + pci_conf1_write_config8(dev, 0x80, 0x1b); + pci_conf1_write_config8(dev, 0x81, 0x0a); + pci_conf1_write_config8(dev, 0x82, 0x0a); + pci_conf1_write_config8(dev, 0x83, 0x0a); +} + +void cn700_stage1(void) +{ + /* Enable multifunction for northbridge. */ + pci_conf1_write_config8(0x00, 0x4f, 0x01); + + /* Put Bus 1 in its proper place */ + pci_conf1_write_config8(PCI_BDF(0, 1, 0), 0x19, 0x1); + pci_conf1_write_config8(PCI_BDF(0, 1, 0), 0x1a, 0x1); + + enable_shadow_ram(); + enable_vlink(); + c7_cpu_setup(); +} Modified: coreboot-v3/southbridge/via/vt8237/ide.c =================================================================== --- coreboot-v3/southbridge/via/vt8237/ide.c 2008-12-10 19:07:16 UTC (rev 1069) +++ coreboot-v3/southbridge/via/vt8237/ide.c 2008-12-10 21:23:09 UTC (rev 1070) @@ -95,8 +95,8 @@ {.pci = {.vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VT8237_PATA}}}, .constructor = default_device_constructor, - .phase2_fixup = vt8237_enable, - .phase3_scan = 0, + //.phase2_fixup = vt8237_enable, + //.phase3_scan = 0, //.phase4_enable_disable = vt8237_enable, //.phase4_read_resources = pci_dev_read_resources, //.phase4_set_resources = pci_set_resources, Modified: coreboot-v3/southbridge/via/vt8237/lpc.c =================================================================== --- coreboot-v3/southbridge/via/vt8237/lpc.c 2008-12-10 19:07:16 UTC (rev 1069) +++ coreboot-v3/southbridge/via/vt8237/lpc.c 2008-12-10 21:23:09 UTC (rev 1070) @@ -448,7 +448,6 @@ {.pci = {.vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VT8237R_LPC}}}, .constructor = default_device_constructor, - .phase2_fixup = vt8237_enable, .phase3_scan = scan_static_bus, .phase4_read_resources = vt8237_read_resources, .phase4_set_resources = pci_set_resources, @@ -461,7 +460,6 @@ {.pci = {.vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VT8237S_LPC}}}, .constructor = default_device_constructor, - .phase2_fixup = vt8237_enable, .phase3_scan = scan_static_bus, .phase4_read_resources = vt8237_read_resources, .phase4_set_resources = pci_set_resources, Modified: coreboot-v3/southbridge/via/vt8237/sata.c =================================================================== --- coreboot-v3/southbridge/via/vt8237/sata.c 2008-12-10 19:07:16 UTC (rev 1069) +++ coreboot-v3/southbridge/via/vt8237/sata.c 2008-12-10 21:23:09 UTC (rev 1070) @@ -23,6 +23,9 @@ #include "vt8237.h" /* TODO: use phase2_fixup to disable SATA */ + +/* Causes coreboot to hang, so moved to stage1 code + TODO: Fix vt8237s */ static void sata_i_init(struct device *dev) { u8 reg; @@ -100,12 +103,12 @@ {.pci = {.vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VT8237R_SATA}}}, .constructor = default_device_constructor, - .phase3_scan = 0, + //.phase3_scan = 0, //.phase4_enable_disable = vt8237_enable, //.phase4_read_resources = pci_dev_read_resources, //.phase4_set_resources = pci_set_resources, //.phase5_enable_resources = pci_dev_enable_resources, - .phase6_init = sata_i_init, + //.phase6_init = sata_i_init, }; struct device_operations vt8237s_sata = { @@ -113,8 +116,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VT8237S_SATA}}}, .constructor = default_device_constructor, - .phase2_fixup = 0, - .phase3_scan = 0, + //.phase3_scan = 0, //.phase4_enable_disable = vt8237_enable, //.phase4_read_resources = pci_dev_read_resources, //.phase4_set_resources = pci_set_resources, Modified: coreboot-v3/southbridge/via/vt8237/stage1.c =================================================================== --- coreboot-v3/southbridge/via/vt8237/stage1.c 2008-12-10 19:07:16 UTC (rev 1069) +++ coreboot-v3/southbridge/via/vt8237/stage1.c 2008-12-10 21:23:09 UTC (rev 1070) @@ -27,12 +27,13 @@ #include <device/pci_ids.h> #include <spd.h> #include "vt8237.h" +#include <config.h> /* TODO List: * * Merge the rest of the functions from v2, except smbus_fixup which doesn't * seem to be necessary any more (?) * * Clean up vt8237_early_network_init. - * Comments in code indicate that it's broken? + * Comments in code indicate that it's broken? * * Figure out if the smbus actually needs to be reset after every transaction. */ @@ -189,6 +190,76 @@ inb(smbus_io_base + SMBHSTCTL); } +/* The change from RAID to SATA in phase6 causes coreboot to lock up, so do it + * as early as possible. Move back to stage2 later */ +static void sata_stage1(void) +{ + u32 dev; + u8 reg; + + pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_SATA, &dev); + + printk(BIOS_DEBUG, "Configuring VIA SATA controller\n"); + + /* Class IDE Disk */ + reg = pci_conf1_read_config8(dev, SATA_MISC_CTRL); + reg &= 0x7f; /* Sub Class Write Protect off */ + pci_conf1_write_config8(dev, SATA_MISC_CTRL, reg); + + /* Change the device class to SATA from RAID. */ + pci_conf1_write_config8(dev, PCI_CLASS_DEVICE, 0x1); + reg |= 0x80; /* Sub Class Write Protect on */ + pci_conf1_write_config8(dev, SATA_MISC_CTRL, reg); +} + +void vt8237_stage1(u16 smbus_io_base) +{ + u32 dev; + u32 ide_dev; + + printk(BIOS_DEBUG, "Doing vt8237r/s stage1 init\n"); + + pci_conf1_find_device(0x1106, 0x3227, &dev); + pci_conf1_find_device(0x1106, 0x0571, &ide_dev); + + /* Disable GP3 timer, or else the system reboots when it runs out */ + pci_conf1_write_config8(dev, 0x98, 0x00); + + /* Change the ROM size mapping based on where CAR is located */ +#if (CONFIG_CARBASE + CONFIG_CARSIZE) < 0xffc00000 + pci_conf1_write_config8(dev, 0x41, 0x7f); +#elif (CONFIG_CARBASE + CONFIG_CARSIZE) < 0xffe00000 + pci_conf1_write_config8(dev, 0x41, 0x70); +#elif (CONFIG_CARBASE + CONFIG_CARSIZE) < 0xfff00000 + pci_conf1_write_config8(dev, 0x41, 0x40); +#endif + + pci_conf1_write_config8(dev, 0x50, 0x80);//disable mc97 + pci_conf1_write_config8(dev, 0x51, 0x1f); + pci_conf1_write_config8(dev, 0x58, 0x60); + pci_conf1_write_config8(dev, 0x59, 0x80); + pci_conf1_write_config8(dev, 0x5b, 0x08); + + /* Make it respond to IO space */ + pci_conf1_write_config8(ide_dev, 0x04, 0x07); + + /* Compatibility mode addresses */ + //pci_conf1_write_config32(ide_dev, 0x10, 0); + //pci_conf1_write_config32(ide_dev, 0x14, 0); + //pci_conf1_write_config32(ide_dev, 0x18, 0); + //pci_conf1_write_config32(ide_dev, 0x1b, 0); + + /* Native mode base address */ + //pci_conf1_write_config32(ide_dev, 0x20, BUS_MASTER_ADDR | 1); + + pci_conf1_write_config8(ide_dev, 0x40, 0x3);//was 0x3 + pci_conf1_write_config8(ide_dev, 0x41, 0xf2); + pci_conf1_write_config8(ide_dev, 0x42, 0x09); + + sata_stage1(); + enable_smbus(smbus_io_base); +} + /* TODO: * Magic numbers -> #defines * fix? Modified: coreboot-v3/southbridge/via/vt8237/vt8237.h =================================================================== --- coreboot-v3/southbridge/via/vt8237/vt8237.h 2008-12-10 19:07:16 UTC (rev 1069) +++ coreboot-v3/southbridge/via/vt8237/vt8237.h 2008-12-10 21:23:09 UTC (rev 1070) @@ -77,6 +77,7 @@ } __attribute__ ((packed)); void enable_smbus(u16); +void vt8237_stage1(u16); u8 smbus_read_byte(u16, u8, u16); void vt8237_enable(struct device *); Modified: coreboot-v3/superio/via/vt1211/vt1211.h =================================================================== --- coreboot-v3/superio/via/vt1211/vt1211.h 2008-12-10 19:07:16 UTC (rev 1069) +++ coreboot-v3/superio/via/vt1211/vt1211.h 2008-12-10 21:23:09 UTC (rev 1070) @@ -34,4 +34,6 @@ #define VT1211_FIR 12 /* IRDA */ #define VT1211_ROM 13 /* ROM control */ +void vt1211_enable_serial(u8 dev, u8 serial, u16 iobase); + #endif /* SUPERIO_VIA_VT1211_VT122_H */

1 0

v3 set_subsystem functions unsigned -> u16
by Myles Watson 10 Dec '08

10 Dec '08

This patch changes unsigned [int] to u16 for subsystem IDs. They're in the hardware and have a specific size. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 2

r1069 - in coreboot-v3: device include/device northbridge/intel/i945 southbridge/amd/amd8111 southbridge/intel/i82801gx southbridge/nvidia/mcp55
by svn＠coreboot.org 10 Dec '08

10 Dec '08

Author: myles Date: 2008-12-10 20:07:16 +0100 (Wed, 10 Dec 2008) New Revision: 1069 Modified: coreboot-v3/device/pci_device.c coreboot-v3/include/device/pci.h coreboot-v3/northbridge/intel/i945/northbridge.c coreboot-v3/southbridge/amd/amd8111/ac97.c coreboot-v3/southbridge/amd/amd8111/acpi.c coreboot-v3/southbridge/amd/amd8111/ide.c coreboot-v3/southbridge/amd/amd8111/lpc.c coreboot-v3/southbridge/amd/amd8111/nic.c coreboot-v3/southbridge/amd/amd8111/smbus.c coreboot-v3/southbridge/amd/amd8111/usb.c coreboot-v3/southbridge/intel/i82801gx/lpc.c coreboot-v3/southbridge/intel/i82801gx/usb_ehci.c coreboot-v3/southbridge/nvidia/mcp55/mcp55.c coreboot-v3/southbridge/nvidia/mcp55/mcp55.h Log: This patch changes unsigned [int] to u16 for subsystem IDs. They're in the hardware and have a specific size. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/device/pci_device.c =================================================================== --- coreboot-v3/device/pci_device.c 2008-12-10 18:50:54 UTC (rev 1068) +++ coreboot-v3/device/pci_device.c 2008-12-10 19:07:16 UTC (rev 1069) @@ -710,8 +710,7 @@ delay(1); } -void pci_dev_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) +void pci_dev_set_subsystem(struct device *dev, u16 vendor, u16 device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); Modified: coreboot-v3/include/device/pci.h =================================================================== --- coreboot-v3/include/device/pci.h 2008-12-10 18:50:54 UTC (rev 1068) +++ coreboot-v3/include/device/pci.h 2008-12-10 19:07:16 UTC (rev 1069) @@ -44,7 +44,7 @@ /* Common pci operations without a standard interface */ struct pci_operations { /* set the Subsystem IDs for the PCI device */ - void (*set_subsystem)(struct device * dev, unsigned vendor, unsigned device); + void (*set_subsystem)(struct device * dev, u16 vendor, u16 device); }; /* Common pci bus operations */ @@ -60,8 +60,8 @@ struct pci_driver { struct device_operations *ops; - unsigned short vendor; - unsigned short device; + u16 vendor; + u16 device; }; #define __pci_driver __attribute__ ((used,__section__(".rodata.pci_driver"))) @@ -94,7 +94,7 @@ unsigned pci_find_next_capability(struct device * dev, unsigned cap, unsigned last); unsigned pci_find_capability(struct device * dev, unsigned cap); struct resource *pci_get_resource(struct device *dev, unsigned long index); -void pci_dev_set_subsystem(struct device * dev, unsigned vendor, unsigned device); +void pci_dev_set_subsystem(struct device * dev, u16 vendor, u16 device); void pci_domain_read_resources(struct device *dev); void ram_resource(struct device *dev, unsigned long index, Modified: coreboot-v3/northbridge/intel/i945/northbridge.c =================================================================== --- coreboot-v3/northbridge/intel/i945/northbridge.c 2008-12-10 18:50:54 UTC (rev 1068) +++ coreboot-v3/northbridge/intel/i945/northbridge.c 2008-12-10 19:07:16 UTC (rev 1069) @@ -231,7 +231,7 @@ pci_set_resources(dev); } -static void i945_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void i945_set_subsystem(struct device * dev, u16 vendor, u16 device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); Modified: coreboot-v3/southbridge/amd/amd8111/ac97.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-12-10 18:50:54 UTC (rev 1068) +++ coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-12-10 19:07:16 UTC (rev 1069) @@ -28,7 +28,7 @@ #include <config.h> #include "amd8111.h" -static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, u16 vendor, u16 device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); Modified: coreboot-v3/southbridge/amd/amd8111/acpi.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-12-10 18:50:54 UTC (rev 1068) +++ coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-12-10 19:07:16 UTC (rev 1069) @@ -208,7 +208,7 @@ } -static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, u16 vendor, u16 device) { pci_write_config32(dev, 0x7c, ((device & 0xffff) << 16) | (vendor & 0xffff)); Modified: coreboot-v3/southbridge/amd/amd8111/ide.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ide.c 2008-12-10 18:50:54 UTC (rev 1068) +++ coreboot-v3/southbridge/amd/amd8111/ide.c 2008-12-10 19:07:16 UTC (rev 1069) @@ -63,7 +63,7 @@ pci_write_config16(dev, 0x42, word); } -static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, u16 vendor, u16 device) { pci_write_config32(dev, 0x70, ((device & 0xffff) << 16) | (vendor & 0xffff)); Modified: coreboot-v3/southbridge/amd/amd8111/lpc.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-12-10 18:50:54 UTC (rev 1068) +++ coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-12-10 19:07:16 UTC (rev 1069) @@ -197,7 +197,7 @@ enable_childrens_resources(dev); } -static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, u16 vendor, u16 device) { pci_write_config32(dev, 0x70, ((device & 0xffff) << 16) | (vendor & 0xffff)); Modified: coreboot-v3/southbridge/amd/amd8111/nic.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/nic.c 2008-12-10 18:50:54 UTC (rev 1068) +++ coreboot-v3/southbridge/amd/amd8111/nic.c 2008-12-10 19:07:16 UTC (rev 1069) @@ -83,7 +83,7 @@ printk(BIOS_DEBUG, "Done\n"); } -static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, u16 vendor, u16 device) { pci_write_config32(dev, 0xc8, ((device & 0xffff) << 16) | (vendor & 0xffff)); Modified: coreboot-v3/southbridge/amd/amd8111/smbus.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/smbus.c 2008-12-10 18:50:54 UTC (rev 1068) +++ coreboot-v3/southbridge/amd/amd8111/smbus.c 2008-12-10 19:07:16 UTC (rev 1069) @@ -34,7 +34,7 @@ #include <io.h> #include "amd8111.h" -static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, u16 vendor, u16 device) { pci_write_config32(dev, 0x44, ((device & 0xffff) << 16) | (vendor & 0xffff)); Modified: coreboot-v3/southbridge/amd/amd8111/usb.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/usb.c 2008-12-10 18:50:54 UTC (rev 1068) +++ coreboot-v3/southbridge/amd/amd8111/usb.c 2008-12-10 19:07:16 UTC (rev 1069) @@ -34,7 +34,7 @@ #include "amd8111.h" -static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, u16 vendor, u16 device) { pci_write_config32(dev, 0x70, ((device & 0xffff) << 16) | (vendor & 0xffff)); Modified: coreboot-v3/southbridge/intel/i82801gx/lpc.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/lpc.c 2008-12-10 18:50:54 UTC (rev 1068) +++ coreboot-v3/southbridge/intel/i82801gx/lpc.c 2008-12-10 19:07:16 UTC (rev 1069) @@ -325,7 +325,7 @@ enable_childrens_resources(dev); } -static void set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device * dev, u16 vendor, u16 device) { printk(BIOS_DEBUG, "Setting LPC bridge subsystem ID\n"); pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, Modified: coreboot-v3/southbridge/intel/i82801gx/usb_ehci.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/usb_ehci.c 2008-12-10 18:50:54 UTC (rev 1068) +++ coreboot-v3/southbridge/intel/i82801gx/usb_ehci.c 2008-12-10 19:07:16 UTC (rev 1069) @@ -49,8 +49,7 @@ printk(BIOS_DEBUG, "done.\n"); } -static void usb_ehci_set_subsystem(struct device * dev, unsigned vendor, - unsigned device) +static void usb_ehci_set_subsystem(struct device * dev, u16 vendor, u16 device) { u8 access_cntl; Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-12-10 18:50:54 UTC (rev 1068) +++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-12-10 19:07:16 UTC (rev 1069) @@ -248,8 +248,7 @@ } -void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) +void mcp55_pci_dev_set_subsystem(struct device *dev, u16 vendor, u16 device) { pci_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.h =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/mcp55.h 2008-12-10 18:50:54 UTC (rev 1068) +++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.h 2008-12-10 19:07:16 UTC (rev 1069) @@ -24,8 +24,7 @@ #define PCI_MCP55_SUBSYSTEM_VENDOR_ID 0x40 -void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device); +void mcp55_pci_dev_set_subsystem(struct device *dev, u16 vendor, u16 device); extern struct pci_operations mcp55_pci_dev_ops_pci; #endif /* MCP55_H */

1 0

v3 Kontron warnings
by Myles Watson 10 Dec '08

10 Dec '08

This patch fixes some warnings in the Kontron build and a little bit of whitespace. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

4 7

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