coreboot December 2008

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77 participants
330 discussions

Re: [coreboot] r3813 - trunk/coreboot-v2/src/mainboard/amd/pistachio
by Carl-Daniel Hailfinger 14 Dec '08

14 Dec '08

On 14.12.2008 01:01, svn(a)coreboot.org wrote: > Author: stepan > Date: 2008-12-14 01:01:04 +0100 (Sun, 14 Dec 2008) > New Revision: 3813 > > Modified: > trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb > trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c > Log: > oops. there went a new mainboard into the tree and i missed it. Add mainboard > specific changes based on the DBM690T code. > > Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> > Acked-by: Stefan Reinauer <stepan(a)coresystems.de> > Thanks for fixing this! Regards, Carl-Daniel -- http://www.hailfinger.org/

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r3813 - trunk/coreboot-v2/src/mainboard/amd/pistachio
by svn＠coreboot.org 14 Dec '08

14 Dec '08

Author: stepan Date: 2008-12-14 01:01:04 +0100 (Sun, 14 Dec 2008) New Revision: 3813 Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c Log: oops. there went a new mainboard into the tree and i missed it. Add mainboard specific changes based on the DBM690T code. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb 2008-12-13 20:51:34 UTC (rev 3812) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb 2008-12-14 00:01:04 UTC (rev 3813) @@ -91,6 +91,7 @@ uses CONFIG_VIDEO_MB uses CONFIG_GFXUMA +uses HAVE_MAINBOARD_RESOURCES ### ### Build options @@ -299,6 +300,7 @@ default CONFIG_VIDEO_MB=1 default CONFIG_GFXUMA=1 +default HAVE_MAINBOARD_RESOURCES=1 ### End Options.lb end Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c 2008-12-13 20:51:34 UTC (rev 3812) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c 2008-12-14 00:01:04 UTC (rev 3813) @@ -42,6 +42,8 @@ #define ADT7475_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address, val) +unsigned long uma_memory_start, uma_memory_size; + /******************************************************** * pistachio uses a BCM5787 as on-board NIC. * It has a pin named LOW_POWER to enable it into LOW POWER state. @@ -322,12 +324,23 @@ set_thermal_config(); } +int add_mainboard_resources(struct lb_memory *mem) +{ + /* UMA is removed from system memory in the northbridge code, but + * in some circumstances we want the memory mentioned as reserved. + */ +#if (CONFIG_GFXUMA == 1) + printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n", + uma_memory_start, uma_memory_size); + lb_add_memory_range(mem, LB_MEM_RESERVED, + uma_memory_start, uma_memory_size); +#endif +} + /* * CONFIG_CHIP_NAME defined in Option.lb. */ struct chip_operations mainboard_amd_pistachio_ops = { -#if CONFIG_CHIP_NAME == 1 - CHIP_NAME("AMD pistachio Mainboard") -#endif - .enable_dev = pistachio_enable, + CHIP_NAME("AMD Pistachio Mainboard") + .enable_dev = pistachio_enable, };

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Re: [coreboot] Fwd: [RFC] Here we go... the SLOF biosemu for coreboot-v3
by Pattrick Hueper 14 Dec '08

14 Dec '08

On Sun, Dec 14, 2008 at 12:04 AM, Pattrick Hueper <phueper(a)hueper.net> wrote: > On Sat, Dec 13, 2008 at 11:37 PM, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: >> There's one thing we have to decide on, though. Should all of this be >> committed as one big block or is a split into multiple patches preferable? >> I'd like at least one commit which mirrors the YABEL part of the SLOF >> tree (commit 0aab2795a986e76286386ebd02e59ca75a528538). Later changes >> can be grouped, but it never huts to have a reference point available, >> especially if there is a chance that the YABEL codebase may get some >> fixes in SLOF. > > I agree, i would like to have: > > - the original SLOF tree 0aab2795a986e76286386ebd02e59ca75a528538 > - the original SLOF x86emu patches 9644fedf2dbbb2b3bcd4331758bc2e6a335ee8af > - and the rest grouped together > > as separate commits. As you said, it makes sense to have a reference > back to the SLOF source code. > > I will prepare those patches (should be pretty easy with git) and > resend them to the list. > > Cheers, Patty > Ok, here are the updated patches. - one for x86emu changes from SLOF 1.7.0-4 - one for unmodified biosemu from SLOF 1.7.0-4 - one for warning fixes in x86emu ( i think it makes sense to have these separate, they are not part of SLOF and only affect x86emu) - one for the integration of biosemu aka YABEL into coreboot Patty

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r3812 build service
by coreboot information 13 Dec '08

13 Dec '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3812 to the coreboot source repository and caused the following changes: Change Log: Move mainboard specific changes to the coreboot memory table into the mainboard specific code. (And add a hook to allow other mainboards do a similar thing if required) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G Minnich <rminnich(a)gmail.com> Build Log: Compilation of amd:pistachio has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3812&device=pistachio&vend… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3812 - in trunk/coreboot-v2/src: arch/i386/boot config include/boot mainboard/amd/dbm690t southbridge/amd/rs690
by svn＠coreboot.org 13 Dec '08

13 Dec '08

Author: stepan Date: 2008-12-13 21:51:34 +0100 (Sat, 13 Dec 2008) New Revision: 3812 Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.h trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/include/boot/coreboot_tables.h trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c Log: Move mainboard specific changes to the coreboot memory table into the mainboard specific code. (And add a hook to allow other mainboards do a similar thing if required) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2008-12-12 03:40:21 UTC (rev 3811) +++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2008-12-13 20:51:34 UTC (rev 3812) @@ -357,7 +357,8 @@ } } -static void lb_add_memory_range(struct lb_memory *mem, +/* This function is used in mainboard specific code, too */ +void lb_add_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size) { lb_remove_memory_range(mem, start, size); @@ -447,15 +448,10 @@ lb_add_memory_range(mem, LB_MEM_TABLE, rom_table_start, rom_table_end-rom_table_start); - /* AMD rs690 chip, we should remove the UMA from system memory. */ -#if (CONFIG_GFXUMA == 1) - printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n", - uma_memory_start, uma_memory_size); - lb_add_memory_range(mem, LB_MEM_TABLE, - uma_memory_start, uma_memory_size); +#if (HAVE_MAINBOARD_RESOURCES == 1) + add_mainboard_resources(mem); #endif - /* Note: * I assume that there is always memory at immediately after * the low_table_end. This means that after I setup the coreboot table. Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.h 2008-12-12 03:40:21 UTC (rev 3811) +++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.h 2008-12-13 20:51:34 UTC (rev 3812) @@ -26,4 +26,7 @@ extern struct cmos_option_table option_table; +/* defined by mainboard.c if the mainboard requires extra resources */ +int add_mainboard_resources(struct lb_memory *mem); + #endif /* COREBOOT_TABLE_H */ Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2008-12-12 03:40:21 UTC (rev 3811) +++ trunk/coreboot-v2/src/config/Options.lb 2008-12-13 20:51:34 UTC (rev 3812) @@ -1101,6 +1101,12 @@ comment "GFX UMA" end +define HAVE_MAINBOARD_RESOURCES + default 0 + export always + comment "Enable if the mainboard/chipset requires extra entries in the memory map" +end + define CONFIG_SPLASH_GRAPHIC default 0 export used Modified: trunk/coreboot-v2/src/include/boot/coreboot_tables.h =================================================================== --- trunk/coreboot-v2/src/include/boot/coreboot_tables.h 2008-12-12 03:40:21 UTC (rev 3811) +++ trunk/coreboot-v2/src/include/boot/coreboot_tables.h 2008-12-13 20:51:34 UTC (rev 3812) @@ -43,12 +43,6 @@ * See also: util/lbtdump/lbtdump.c */ -/* AMD rs690 chip, declare global variables. */ -#if (CONFIG_GFXUMA == 1) - unsigned long uma_memory_start, uma_memory_size; -#endif - - struct lb_uint64 { uint32_t lo; uint32_t hi; Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2008-12-12 03:40:21 UTC (rev 3811) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2008-12-13 20:51:34 UTC (rev 3812) @@ -91,6 +91,7 @@ uses CONFIG_VIDEO_MB uses CONFIG_GFXUMA +uses HAVE_MAINBOARD_RESOURCES ### ### Build options @@ -299,6 +300,7 @@ default CONFIG_VIDEO_MB=1 default CONFIG_GFXUMA=1 +default HAVE_MAINBOARD_RESOURCES=1 ### End Options.lb end Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2008-12-12 03:40:21 UTC (rev 3811) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2008-12-13 20:51:34 UTC (rev 3812) @@ -41,6 +41,8 @@ #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) +unsigned long uma_memory_start, uma_memory_size; + /******************************************************** * dbm690t uses a BCM5789 as on-board NIC. * It has a pin named LOW_POWER to enable it into LOW POWER state. @@ -241,13 +243,24 @@ get_ide_dma66(); set_thermal_config(); } + +int add_mainboard_resources(struct lb_memory *mem) +{ + /* UMA is removed from system memory in the northbridge code, but + * in some circumstances we want the memory mentioned as reserved. + */ +#if (CONFIG_GFXUMA == 1) + printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n", + uma_memory_start, uma_memory_size); + lb_add_memory_range(mem, LB_MEM_RESERVED, + uma_memory_start, uma_memory_size); +#endif +} /* * CONFIG_CHIP_NAME defined in Option.lb. */ struct chip_operations mainboard_amd_dbm690t_ops = { -#if CONFIG_CHIP_NAME == 1 - CHIP_NAME("AMD Dbm690t Mainboard") -#endif - .enable_dev = dbm690t_enable, + CHIP_NAME("AMD DBM690T Mainboard") + .enable_dev = dbm690t_enable, }; Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c 2008-12-12 03:40:21 UTC (rev 3811) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c 2008-12-13 20:51:34 UTC (rev 3812) @@ -307,6 +307,8 @@ */ void rs690_set_tom(device_t nb_dev) { + extern unsigned long uma_memory_start; + /* set TOM */ pci_write_config32(nb_dev, 0x90, uma_memory_start); nbmc_write_index(nb_dev, 0x1e, uma_memory_start);

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[PATCH] make mainboard specific table changes mainboard specific
by Stefan Reinauer 13 Dec '08

13 Dec '08

See patch... -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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Athlon XP discussion
by Joseph Smith 13 Dec '08

13 Dec '08

Just curious, with all the support from AMD, how come no one ever ventured down the Athlon XP road? Athlon XP setups are very cheap these days, possibly making development cost effective??? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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[RFC] Add reviewed-by markers to code sections
by Carl-Daniel Hailfinger 12 Dec '08

12 Dec '08

Hi, I'm currently trying to get my Asus M2A-VM board (690G/SB600) board running in v2. It hangs directly after HT reset. That led me to dig into the code and compare it to the data sheets. In the past, reviews were mostly centered on coding style (not only cosmetics, but also code flow) and general sanity. While that is definitely needed, I propose another layer on top of this: Verification of the code and comments against data sheet recommendations and documentation. Of course such work is neither really sexy nor does it have always an immediate effect on the usability of a particular board, but it can find bugs and hidden assumptions which may come to bite us later. I already found real bugs by comparing code and data sheets in the past, but I can't remember all the code I went through that way. The situation is probably similar for other reviewers. Adding a "Reviewed-by:" tag to the doxygen comments of each function would be a nice way to say that the function has been reviewed. Pointing to the section in the docs against which the code was verified is a ncie added bonus. Plus, comments are really cheap and don't impact compile time significantly. Example patch for a reviewed function: Review and annotate sb600_lpc_init(). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: src/southbridge/amd/sb600/sb600_early_setup.c =================================================================== --- src/southbridge/amd/sb600/sb600_early_setup.c (Revision 3803) +++ src/southbridge/amd/sb600/sb600_early_setup.c (Arbeitskopie) @@ -53,11 +53,15 @@ /*************************************** * Legacy devices are mapped to LPC space. -* serial port 0 +* Serial port 0 * KBC Port * ACPI Micro-controller port -* LPC ROM size, +* LPC ROM size +* This function does not change port 0x80 decoding. +* Console output through any port besides 0x3f8 is unsupported. * NOTE: Call me ASAP, because I will reset LPC ROM size! +* Reviewed-by: Carl-Daniel Hailfinger +* Reviewed against AMD SB600 Register Reference Manual 3.03, section 3.1 (LPC ISA Bridge) ***************************************/ static void sb600_lpc_init(void) { @@ -68,31 +72,38 @@ /* Enable lpc controller */ dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ reg32 = pci_read_config32(dev, 0x64); - reg32 |= 0x00100000; + reg32 |= (1 << 20); pci_write_config32(dev, 0x64, reg32); dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0); /* LPC Controller */ - /* Serial 0 */ + /* Decode port 0x3f8-0x3ff (Serial 0) */ +#warning Serial port decode on LPC is hardcoded to 0x3f8 reg8 = pci_read_config8(dev, 0x44); reg8 |= (1 << 6); pci_write_config8(dev, 0x44, reg8); - /* PS/2 keyboard, ACPI */ + /* Decode port 0x60-0x67 (PS/2 keyboard, ACPI) */ reg8 = pci_read_config8(dev, 0x47); reg8 |= (1 << 5) | (1 << 6); pci_write_config8(dev, 0x47, reg8); /* SuperIO, LPC ROM */ reg8 = pci_read_config8(dev, 0x48); - reg8 |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */ - reg8 |= (1 << 3) | (1 << 4); /* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */ - reg8 |= 1 << 6; /* enable for RTC I/O range */ + /* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */ + reg8 |= (1 << 1) | (1 << 0); + /* Decode variable LPC ROM address ranges 1&2 (see register 0x68-0x6b, 0x6c-0x6f) */ + reg8 |= (1 << 3) | (1 << 4); + /* Decode port 0x70-0x73 (RTC) */ + reg8 |= 1 << 6; pci_write_config8(dev, 0x48, reg8); /* hardware should enable LPC ROM by pin strapes */ - /* rom access at 0xFFF80000/0xFFF00000 - 0xFFFFFFFF */ + /* ROM access at 0xFFF80000/0xFFF00000 - 0xFFFFFFFF */ /* See detail in BDG-215SB600-03.pdf page 15. */ - pci_write_config16(dev, 0x68, 0x000e); /* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB; */ +#warning If Lpc_Rom strap is enabled, the line below has no effect, and if Lpc_Rom strap is disabled, a write to 0x6a is missing + pci_write_config16(dev, 0x68, 0x000e); /* enable LPC ROM range mirroring below 1 MB */ +#warning Due to FWH_*_IDSEL defaults, any LPC ROM chip larger than 512 kB will not work although we enable a range of 1 MB below +#warning If Lpc_Rom strap is disabled, a write to 0x6e is missing pci_write_config16(dev, 0x6c, 0xfff0); /* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB */ } -- http://www.hailfinger.org/

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patch for support mainboard pistachio:
by Li, Maggie 12 Dec '08

12 Dec '08

Hi, Attachment is the patch for mainboard PISTACHIO. The following ACPI features are supported. 1. S1, S4, S5 sleep and wake up (by power button). 2. Thermal configuration based on ADT7475. 3. HPET timer. 4. Interrupt routing based on ACPI table. Signed-off-by: Maggie Li <maggie.li(a)amd.com> Reviewed-by: Michael Xie <michael.xie(a)amd.com <mailto:michael.xie@amd.com> > Please check it, thanks. <<pistachio.patch>> Best regards Maggie li

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r3811 - trunk/coreboot-v2/src/southbridge/amd/sb600
by svn＠coreboot.org 12 Dec '08

12 Dec '08

Author: hailfinger Date: 2008-12-12 04:40:21 +0100 (Fri, 12 Dec 2008) New Revision: 3811 Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c Log: Improve comments in early SB600 setup, handle non-LPC strapping and document verification against the data sheets. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Maggie Li <maggie.li(a)amd.com> Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c 2008-12-10 15:42:37 UTC (rev 3810) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c 2008-12-12 03:40:21 UTC (rev 3811) @@ -53,11 +53,17 @@ /*************************************** * Legacy devices are mapped to LPC space. -* serial port 0 +* Serial port 0 * KBC Port * ACPI Micro-controller port -* LPC ROM size, +* LPC ROM size +* This function does not change port 0x80 decoding. +* Console output through any port besides 0x3f8 is unsupported. +* If you use FWH ROMs, you have to setup IDSEL. * NOTE: Call me ASAP, because I will reset LPC ROM size! +* Reviewed-by: Carl-Daniel Hailfinger +* Reviewed against AMD SB600 Register Reference Manual rev. 3.03, section 3.1 +* (LPC ISA Bridge) ***************************************/ static void sb600_lpc_init(void) { @@ -68,32 +74,42 @@ /* Enable lpc controller */ dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ reg32 = pci_read_config32(dev, 0x64); - reg32 |= 0x00100000; + reg32 |= 1 << 20; pci_write_config32(dev, 0x64, reg32); dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0); /* LPC Controller */ - /* Serial 0 */ + /* Decode port 0x3f8-0x3ff (Serial 0) */ +#warning Serial port decode on LPC is hardcoded to 0x3f8 reg8 = pci_read_config8(dev, 0x44); - reg8 |= (1 << 6); + reg8 |= 1 << 6; pci_write_config8(dev, 0x44, reg8); - /* PS/2 keyboard, ACPI */ + /* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/ reg8 = pci_read_config8(dev, 0x47); reg8 |= (1 << 5) | (1 << 6); pci_write_config8(dev, 0x47, reg8); /* SuperIO, LPC ROM */ reg8 = pci_read_config8(dev, 0x48); - reg8 |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */ - reg8 |= (1 << 3) | (1 << 4); /* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */ - reg8 |= 1 << 6; /* enable for RTC I/O range */ + /* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */ + reg8 |= (1 << 1) | (1 << 0); + /* Decode variable LPC ROM address ranges 1&2 (see register 0x68-0x6b, 0x6c-0x6f) */ + reg8 |= (1 << 3) | (1 << 4); + /* Decode port 0x70-0x73 (RTC) */ + reg8 |= 1 << 6; pci_write_config8(dev, 0x48, reg8); - /* hardware should enable LPC ROM by pin strapes */ - /* rom access at 0xFFF80000/0xFFF00000 - 0xFFFFFFFF */ + /* hardware should enable LPC ROM by pin straps */ + /* ROM access at 0xFFF80000/0xFFF00000 - 0xFFFFFFFF */ /* See detail in BDG-215SB600-03.pdf page 15. */ - pci_write_config16(dev, 0x68, 0x000e); /* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB; */ - pci_write_config16(dev, 0x6c, 0xfff0); /* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB */ + /* enable LPC ROM range mirroring start 0x000e(0000) */ + pci_write_config16(dev, 0x68, 0x000e); + /* enable LPC ROM range mirroring end 0x000f(ffff) */ + pci_write_config16(dev, 0x6a, 0x000f); + /* enable LPC ROM range start, 0xfff8(0000): 512KB, 0xfff0(0000): 1MB */ + pci_write_config16(dev, 0x6c, 0xfff0); + /* enable LPC ROM range end at 0xffff(ffff) */ + pci_write_config16(dev, 0x6e, 0xffff); } /* what is its usage? */ @@ -201,26 +217,36 @@ /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); + /* Chip Control: Enable subtractive decoding */ byte = pci_read_config8(dev, 0x40); byte |= 1 << 5; pci_write_config8(dev, 0x40, byte); + /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ byte = pci_read_config8(dev, 0x4B); byte |= 1 << 7; pci_write_config8(dev, 0x4B, byte); + /* The same IO Base and IO Limit here is meaningful because we set the + * bridge to be subtractive. During early setup stage, we have to make + * sure that data can go through port 0x80. + */ + /* IO Base: 0xf000 */ byte = pci_read_config8(dev, 0x1C); byte |= 0xF << 4; pci_write_config8(dev, 0x1C, byte); + /* IO Limit: 0xf000 */ byte = pci_read_config8(dev, 0x1D); byte |= 0xF << 4; pci_write_config8(dev, 0x1D, byte); + /* PCI Command: Enable IO response */ byte = pci_read_config8(dev, 0x04); byte |= 1 << 0; pci_write_config8(dev, 0x04, byte); + /* LPC controller */ dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0); byte = pci_read_config8(dev, 0x4A); @@ -234,13 +260,13 @@ device_t dev; u32 reg32; - /* enable lpc controller */ + /* Enable LPC controller */ dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); reg32 = pci_read_config32(dev, 0x64); reg32 |= 0x00100000; /* lpcEnable */ pci_write_config32(dev, 0x64, reg32); - /* enable prot80 LPC decode in pci function 3 configuration space. */ + /* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0); byte = pci_read_config8(dev, 0x4a); byte |= 1 << 5; /* enable port 80 */

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coreboot December 2008