Author: cozzie
Date: 2008-12-17 22:17:01 +0100 (Wed, 17 Dec 2008)
New Revision: 1077
Added:
coreboot-v3/arch/x86/via/c7.c
coreboot-v3/arch/x86/via/c7.dts
coreboot-v3/northbridge/via/cn700/agp.dts
coreboot-v3/northbridge/via/cn700/apic.c
coreboot-v3/northbridge/via/cn700/apic.dts
coreboot-v3/northbridge/via/cn700/memctrl.dts
coreboot-v3/northbridge/via/cn700/pci.dts
coreboot-v3/northbridge/via/cn700/pci_domain.c
coreboot-v3/northbridge/via/cn700/pci_domain.dts
coreboot-v3/northbridge/via/cn700/vga.dts
Removed:
coreboot-v3/northbridge/via/cn700/stage2.c
coreboot-v3/northbridge/via/cn700/stage2.h
Modified:
coreboot-v3/mainboard/Kconfig
coreboot-v3/mainboard/jetway/j7f2/Makefile
coreboot-v3/mainboard/jetway/j7f2/dts
coreboot-v3/mainboard/via/epia-cn/dts
coreboot-v3/northbridge/via/cn700/Makefile
coreboot-v3/northbridge/via/cn700/agp.c
coreboot-v3/northbridge/via/cn700/memctrl.c
coreboot-v3/northbridge/via/cn700/pci.c
coreboot-v3/southbridge/via/vt8237/ide.c
coreboot-v3/southbridge/via/vt8237/lpc.c
coreboot-v3/southbridge/via/vt8237/sata.c
coreboot-v3/southbridge/via/vt8237/stage1.c
Log:
Make C7/CN700 boot to memtest86, and pass that test. Booting is very slow, ~15min to get to a memtest
payload.
Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com>
Acked-by: Corey Osgood <corey.osgood(a)gmail.com>
Added: coreboot-v3/arch/x86/via/c7.c
===================================================================
--- coreboot-v3/arch/x86/via/c7.c (rev 0)
+++ coreboot-v3/arch/x86/via/c7.c 2008-12-17 21:17:01 UTC (rev 1077)
@@ -0,0 +1,230 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <console.h>
+#include <io.h>
+#include <lib.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <arch/x86/cpu.h>
+#include <statictree.h>
+#include <config.h>
+
+#include <arch/x86/mtrr.h>
+#include <arch/x86/msr.h>
+#include <arch/x86/lapic.h>
+//#include <arch/x86/cache.h>
+
+#define MSR_IA32_PERF_STATUS 0x00000198
+#define MSR_IA32_PERF_CTL 0x00000199
+#define MSR_IA32_MISC_ENABLE 0x000001a0
+
+static int c7a_speed_translation[] = {
+// LFM HFM
+ 0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M
+ 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V
+ 0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V
+ 0x0409, 0x121c, // 400MHz, 844mV --> 1800MHz, 1.148V
+ 0x0409, 0x0e1c, // 533MHz, 844mV --> 1860MHz, 1.148V
+ 0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V
+ 0x0409, 0x0f1f, // 533MHz, 844mV --> 2000MHz, 1.196V
+ 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV C7-M ULV
+ 0x0406, 0x0a09, // 400MHz, 796mV --> 1000MHz, 844mV
+ 0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV
+ 0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV
+};
+
+static int c7d_speed_translation[] = {
+// LFM HFM
+ 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V C7-M
+ 0x0409, 0x121f, // 400MHz, 844mV --> 1800MHz, 1.196V
+ 0x0809, 0x121f, // 800MHz, 844mV --> 1800MHz, 1.196V
+ 0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V
+ 0x0809, 0x141f, // 800MHz, 844mV --> 2000MHz, 1.196V
+ 0x0406, 0x0806, // 400MHz, 796mV --> 800MHz, 796mV C7-M ULV
+ 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV
+ 0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV
+ 0x0806, 0x0c09, // 800MHz, 796mV --> 1200MHz, 844mV
+ 0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV
+ 0x0806, 0x1010, // 800MHz, 796mV --> 1600MHz, 956mV
+};
+
+static void set_c7_speed(int model) {
+ int cnt, current, new, i;
+ struct msr msr;
+ printk(BIOS_DEBUG, "Enabling improved C7 clock and voltage.\n");
+
+ // Enable Speedstep
+ msr = rdmsr(MSR_IA32_MISC_ENABLE);
+ msr.lo |= (1 << 16);
+ wrmsr(MSR_IA32_MISC_ENABLE, msr);
+
+ msr = rdmsr(MSR_IA32_PERF_STATUS);
+
+ printk(BIOS_INFO, "Voltage: %dmV (min %dmV; max %dmV)\n",
+ ((int)(msr.lo & 0xff) * 16 + 700),
+ ((int)((msr.hi >> 16) & 0xff) * 16 + 700),
+ ((int)(msr.hi & 0xff) * 16 + 700));
+
+ printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n",
+ (int)((msr.lo >> 8) & 0xff),
+ (int)((msr.hi >> 24) & 0xff), (int)((msr.hi >> 8) & 0xff));
+
+ printk(BIOS_DEBUG, " msr.lo = %x\n", msr.lo);
+
+ /* Wait while CPU is busy */
+ cnt = 0;
+ while (msr.lo & ((1 << 16) | (1 << 17))) {
+ udelay(16);
+ msr = rdmsr(MSR_IA32_PERF_STATUS);
+ cnt++;
+ if (cnt > 128) {
+ printk(BIOS_DEBUG, "Could not update multiplier and voltage.\n");
+ return;
+ }
+ }
+
+ current = msr.lo & 0xffff;
+
+ // Start out with no change.
+ new = current;
+ switch (model) {
+ case 10: // model A
+ for (i = 0; i < ARRAY_SIZE(c7a_speed_translation); i += 2) {
+ if ((c7a_speed_translation[i] == current) &&
+ ((c7a_speed_translation[i + 1] & 0xff00) ==
+ (msr.hi & 0xff00))) {
+ new = c7a_speed_translation[i + 1];
+ }
+ }
+ break;
+ case 13: // model D
+ for (i = 0; i < ARRAY_SIZE(c7d_speed_translation); i += 2) {
+ if ((c7d_speed_translation[i] == current) &&
+ ((c7d_speed_translation[i + 1] & 0xff00) ==
+ (msr.hi & 0xff00))) {
+ new = c7d_speed_translation[i + 1];
+ }
+ }
+ break;
+ default:
+ printk(BIOS_INFO, "CPU type not known, multiplier unchanged.\n");
+ }
+
+ msr.lo = new;
+ msr.hi = 0;
+ printk(BIOS_DEBUG, " new msr.lo = %x\n", msr.lo);
+
+ wrmsr(MSR_IA32_PERF_CTL, msr);
+
+ /* Wait until the power transition ends */
+ cnt = 0;
+ do {
+ udelay(16);
+ msr = rdmsr(MSR_IA32_PERF_STATUS);
+ cnt++;
+ if (cnt > 128) {
+ printk(BIOS_DEBUG, "Error while updating multiplier and voltage\n");
+ break;
+ }
+ } while (msr.lo & ((1 << 16) | (1 << 17)));
+
+ printk(BIOS_INFO, "Current voltage: %dmV\n", ((int)(msr.lo & 0xff) * 16 + 700));
+ printk(BIOS_INFO, "Current CPU multiplier: %dx\n", (int)((msr.lo >> 8) & 0xff));
+}
+
+static void c7_init(struct device * dev)
+{
+ u8 brand;
+ struct cpuinfo_x86 c;
+ struct msr msr;
+
+ get_fms(&c, dev->id.pci.device);
+
+ printk(BIOS_INFO, "Detected VIA ");
+
+ switch (c.x86_model) {
+ case 10:
+ msr = rdmsr(0x1153);
+ brand = (((msr.lo >> 2) ^ msr.lo) >> 18) & 3;
+ printk(BIOS_INFO, "Model A ");
+ break;
+ case 13:
+ msr = rdmsr(0x1154);
+ brand = (((msr.lo >> 4) ^ (msr.lo >> 2))) & 0x000000ff;
+ printk(BIOS_INFO, "Model D ");
+ break;
+ default:
+ printk(BIOS_INFO, "Model Unknown ");
+ brand = 0xff;
+ }
+
+ switch (brand) {
+ case 0:
+ printk(BIOS_INFO, "C7-M\n");
+ break;
+ case 1:
+ printk(BIOS_INFO, "C7\n");
+ break;
+ case 2:
+ printk(BIOS_INFO, "Eden\n");
+ break;
+ case 3:
+ printk(BIOS_INFO, "C7-D\n");
+ break;
+ default:
+ printk(BIOS_INFO, "%02x (please report)\n", brand);
+ }
+
+ /* Gear up */
+ set_c7_speed(c.x86_model);
+
+ /* Turn on cache */
+ enable_cache();
+
+ /* Set up Memory Type Range Registers */
+ //these don't exist yet
+ //x86_setup_mtrrs(36);
+ //x86_mtrr_check();
+
+ /* Enable the local cpu apics */
+ //setup_lapic();
+};
+
+#if 1
+struct device_operations c7_cpu = {
+ .id = {.type = DEVICE_ID_PCI,
+ {.pci = {.vendor = X86_VENDOR_CENTAUR, .device = 0x06A9}}},
+ .constructor = default_device_constructor,
+ .phase3_scan = NULL,
+ .phase6_init = c7_init,
+};
+#else
+
+struct device_operations c7_cpu = {
+ .id = {.type = DEVICE_ID_PCI,
+ {.pci = {.vendor = X86_VENDOR_CENTAUR, .device = 0x06D0}}},
+ .constructor = default_device_constructor,
+ .phase3_scan = NULL,
+ .phase6_init = c7_init,
+};
+#endif
Added: coreboot-v3/arch/x86/via/c7.dts
===================================================================
--- coreboot-v3/arch/x86/via/c7.dts (rev 0)
+++ coreboot-v3/arch/x86/via/c7.dts 2008-12-17 21:17:01 UTC (rev 1077)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+{
+ device_operations = "c7_cpu";
+};
Modified: coreboot-v3/mainboard/Kconfig
===================================================================
--- coreboot-v3/mainboard/Kconfig 2008-12-16 22:46:55 UTC (rev 1076)
+++ coreboot-v3/mainboard/Kconfig 2008-12-17 21:17:01 UTC (rev 1077)
@@ -133,4 +133,3 @@
Map the config names to an integer.
endmenu
-
Modified: coreboot-v3/mainboard/jetway/j7f2/Makefile
===================================================================
--- coreboot-v3/mainboard/jetway/j7f2/Makefile 2008-12-16 22:46:55 UTC (rev 1076)
+++ coreboot-v3/mainboard/jetway/j7f2/Makefile 2008-12-17 21:17:01 UTC (rev 1077)
@@ -30,7 +30,7 @@
$(src)/lib/ramtest.c \
$(src)/arch/x86/pci_ops_conf1.c
-STAGE2_MAINBOARD_SRC =
+STAGE2_MAINBOARD_SRC = ##$(src)/arch/x86/via/c7.c
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Modified: coreboot-v3/mainboard/jetway/j7f2/dts
===================================================================
--- coreboot-v3/mainboard/jetway/j7f2/dts 2008-12-16 22:46:55 UTC (rev 1076)
+++ coreboot-v3/mainboard/jetway/j7f2/dts 2008-12-17 21:17:01 UTC (rev 1077)
@@ -45,17 +45,31 @@
mainboard_name = "J7F2";
mainboard_pci_subsystem_vendor = "0xdead"; /* TODO */
mainboard_pci_subsystem_device = "0xbeef"; /* TODO */
- cpus { };
+ cpus {
+ /config/("arch/x86/via/c7.dts");
+ };
apic@0 {
+ /config/("northbridge/via/cn700/apic.dts");
};
domain@0 {
- pci@0,0 {};
+ /config/("northbridge/via/cn700/pci_domain.dts");
+ pci@0,0 {
+ /config/("northbridge/via/cn700/agp.dts");
+ };
pci@0,1 {};
pci@0,2 {};
- pci@0,3 {};
+ pci@0,3 {
+ /config/("northbridge/via/cn700/memctrl.dts");
+ };
pci@0,4 {};
pci@0,7 {};
- pci@1,0 {};
+ /* How do I represent the bus and pci devices hanging here? */
+ pci@1,0 {
+ /config/("northbridge/via/cn700/pci.dts");
+ pci@0,1 {
+ /config/("northbridge/via/cn700/vga.dts");
+ };
+ };
pci@f,0 {};
pci@10,0 {
/config/("southbridge/via/vt8237/sata.dts");
Modified: coreboot-v3/mainboard/via/epia-cn/dts
===================================================================
--- coreboot-v3/mainboard/via/epia-cn/dts 2008-12-16 22:46:55 UTC (rev 1076)
+++ coreboot-v3/mainboard/via/epia-cn/dts 2008-12-17 21:17:01 UTC (rev 1077)
@@ -45,17 +45,31 @@
mainboard_name = "EPIA-CN";
mainboard_pci_subsystem_vendor = "0xdead"; /* TODO */
mainboard_pci_subsystem_device = "0xbeef"; /* TODO */
- cpus { };
+ cpus {
+ /config/("arch/x86/via/c7.dts");
+ };
apic@0 {
+ /config/("northbridge/via/cn700/apic.dts");
};
domain@0 {
- pci@0,0 {};
+ /config/("northbridge/via/cn700/pci_domain.dts");
+ pci@0,0 {
+ /config/("northbridge/via/cn700/agp.dts");
+ };
pci@0,1 {};
pci@0,2 {};
- pci@0,3 {};
+ pci@0,3 {
+ /config/("northbridge/via/cn700/memctrl.dts");
+ };
pci@0,4 {};
pci@0,7 {};
- pci@1,0 {};
+ /* How do I represent the bus and pci devices hanging here? */
+ pci@1,0 {
+ /config/("northbridge/via/cn700/pci.dts");
+ pci@0,1 {
+ /config/("northbridge/via/cn700/vga.dts");
+ };
+ };
pci@f,0 {};
pci@10,0 {
/config/("southbridge/via/vt8237/sata.dts");
Modified: coreboot-v3/northbridge/via/cn700/Makefile
===================================================================
--- coreboot-v3/northbridge/via/cn700/Makefile 2008-12-16 22:46:55 UTC (rev 1076)
+++ coreboot-v3/northbridge/via/cn700/Makefile 2008-12-17 21:17:01 UTC (rev 1077)
@@ -20,9 +20,12 @@
ifeq ($(CONFIG_NORTHBRIDGE_VIA_CN700),y)
-STAGE2_CHIPSET_SRC += $(src)/northbridge/via/cn700/stage2.c \
+STAGE2_CHIPSET_SRC += $(src)/northbridge/via/cn700/apic.c \
$(src)/northbridge/via/cn700/agp.c \
+ $(src)/northbridge/via/cn700/memctrl.c \
$(src)/northbridge/via/cn700/pci.c \
- $(src)/northbridge/via/cn700/vga.c
+ $(src)/northbridge/via/cn700/pci_domain.c \
+ $(src)/northbridge/via/cn700/vga.c \
+ $(src)/arch/x86/via/c7.c
endif
Modified: coreboot-v3/northbridge/via/cn700/agp.c
===================================================================
--- coreboot-v3/northbridge/via/cn700/agp.c 2008-12-16 22:46:55 UTC (rev 1076)
+++ coreboot-v3/northbridge/via/cn700/agp.c 2008-12-17 21:17:01 UTC (rev 1077)
@@ -108,7 +108,8 @@
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
- //.phase4_set_resources = pci_set_resources,
- //.phase5_enable_resources = pci_dev_enable_resources,
+ .phase4_set_resources = pci_set_resources,
+ .phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = agp_init,
+ .ops_pci_bus = &pci_cf8_conf1,
};
Added: coreboot-v3/northbridge/via/cn700/agp.dts
===================================================================
--- coreboot-v3/northbridge/via/cn700/agp.dts (rev 0)
+++ coreboot-v3/northbridge/via/cn700/agp.dts 2008-12-17 21:17:01 UTC (rev 1077)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+{
+ device_operations = "cn700_agp";
+};
Added: coreboot-v3/northbridge/via/cn700/apic.c
===================================================================
--- coreboot-v3/northbridge/via/cn700/apic.c (rev 0)
+++ coreboot-v3/northbridge/via/cn700/apic.c 2008-12-17 21:17:01 UTC (rev 1077)
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <arch/x86/cpu.h>
+
+
+static void cpu_bus_init(struct device *dev)
+{
+#warning "cpu_bus_init() empty, what should it do?"
+ printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
+ printk(BIOS_SPEW, ">> Exiting northbridge.c: %s\n", __FUNCTION__);
+}
+
+static void cpu_bus_noop(struct device *dev)
+{
+}
+
+/** Operations for when the northbridge is running an APIC cluster. */
+struct device_operations cn700_north_apic = {
+ .id = {.type = DEVICE_ID_APIC_CLUSTER,
+ {.apic_cluster = {.vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_CN700_AGP}}},
+ .constructor = default_device_constructor,
+ .phase3_scan = 0,
+ .phase4_read_resources = cpu_bus_noop,
+ .phase4_set_resources = cpu_bus_noop,
+ .phase5_enable_resources = cpu_bus_noop,
+ .phase6_init = cpu_bus_init,
+};
Added: coreboot-v3/northbridge/via/cn700/apic.dts
===================================================================
--- coreboot-v3/northbridge/via/cn700/apic.dts (rev 0)
+++ coreboot-v3/northbridge/via/cn700/apic.dts 2008-12-17 21:17:01 UTC (rev 1077)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+{
+ device_operations = "cn700_north_apic";
+};
Modified: coreboot-v3/northbridge/via/cn700/memctrl.c
===================================================================
--- coreboot-v3/northbridge/via/cn700/memctrl.c 2008-12-16 22:46:55 UTC (rev 1076)
+++ coreboot-v3/northbridge/via/cn700/memctrl.c 2008-12-17 21:17:01 UTC (rev 1077)
@@ -33,7 +33,7 @@
u8 ranks, pagec, paged, pagee, pagef, shadowreg;
/* Set up the VGA framebuffer size. */
- reg16 = (log2(CONFIG_CN700_VIDEO_MB_32) << 12) | (1 << 15);
+ reg16 = (log2f(CONFIG_CN700_VIDEO_MB_32) << 12) | (1 << 15);
pci_write_config16(dev, 0xa0, reg16);
/* Set up VGA timers. */
@@ -57,6 +57,7 @@
/* TODO: This doesn't belong here. At the very least make it a dts
* option */
+#if 0 /* Handled in stage1 */
/* Shadow RAM */
pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30;
/* PAGE C, D, E are all read write enable */
@@ -68,26 +69,25 @@
shadowreg |= pagef;
pci_write_config8(dev, 0x83, shadowreg);
/* vlink mirror */
- vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_CN700_VLINK, 0);
- if (vlink_dev) {
- pci_write_config8(vlink_dev, 0x61, pagec);
- pci_write_config8(vlink_dev, 0x62, paged);
- pci_write_config8(vlink_dev, 0x64, pagee);
-
- shadowreg = pci_read_config8(vlink_dev, 0x63);
- shadowreg |= pagef;
- pci_write_config8(vlink_dev, 0x63, shadowreg);
- }
+ vlink_dev = dev_find_slot(0, PCI_BDF(0, 7, 0))
+ pci_write_config8(vlink_dev, 0x61, pagec);
+ pci_write_config8(vlink_dev, 0x62, paged);
+ pci_write_config8(vlink_dev, 0x64, pagee);
+ shadowreg = pci_read_config8(vlink_dev, 0x63);
+ shadowreg |= pagef;
+ pci_write_config8(vlink_dev, 0x63, shadowreg);
+#endif
}
-static const struct device_operations memctrl_operations = {
- .read_resources = cn700_noop,
- .init = memctrl_init,
+struct device_operations cn700_memctrl = {
+ .id = {.type = DEVICE_ID_PCI,
+ {.pci = {.vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL}}},
+ .constructor = default_device_constructor,
+ //.phase3_scan = scan_static_bus,
+ .phase4_read_resources = pci_dev_read_resources,
+ .phase4_set_resources = pci_set_resources,
+ .phase5_enable_resources = pci_dev_enable_resources,
+ .phase6_init = memctrl_init,
+ .ops_pci = &pci_dev_ops_pci,
};
-
-static const struct pci_driver memctrl_driver __pci_driver = {
- .ops = &memctrl_operations,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL,
-};
Added: coreboot-v3/northbridge/via/cn700/memctrl.dts
===================================================================
--- coreboot-v3/northbridge/via/cn700/memctrl.dts (rev 0)
+++ coreboot-v3/northbridge/via/cn700/memctrl.dts 2008-12-17 21:17:01 UTC (rev 1077)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+{
+ device_operations = "cn700_memctrl";
+};
Modified: coreboot-v3/northbridge/via/cn700/pci.c
===================================================================
--- coreboot-v3/northbridge/via/cn700/pci.c 2008-12-16 22:46:55 UTC (rev 1076)
+++ coreboot-v3/northbridge/via/cn700/pci.c 2008-12-17 21:17:01 UTC (rev 1077)
@@ -54,8 +54,9 @@
.device = PCI_DEVICE_ID_VIA_CN700_BRIDGE}}},
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
- .phase4_read_resources = pci_dev_read_resources,
- //.phase4_set_resources = pci_set_resources,
- //.phase5_enable_resources = pci_dev_enable_resources,
+ .phase4_read_resources = NULL,
+ .phase4_set_resources = pci_set_resources,
+ .phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_bridge_init,
+ .ops_pci_bus = &pci_cf8_conf1,
};
Added: coreboot-v3/northbridge/via/cn700/pci.dts
===================================================================
--- coreboot-v3/northbridge/via/cn700/pci.dts (rev 0)
+++ coreboot-v3/northbridge/via/cn700/pci.dts 2008-12-17 21:17:01 UTC (rev 1077)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+{
+ device_operations = "cn700_pci_bridge";
+};
Added: coreboot-v3/northbridge/via/cn700/pci_domain.c
===================================================================
--- coreboot-v3/northbridge/via/cn700/pci_domain.c (rev 0)
+++ coreboot-v3/northbridge/via/cn700/pci_domain.c 2008-12-17 21:17:01 UTC (rev 1077)
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA)
+ * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <console.h>
+#include <io.h>
+#include <lib.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <arch/x86/cpu.h>
+#include <statictree.h>
+#include <config.h>
+
+static void tolm_test(void *gp, struct device *dev, struct resource *new)
+{
+ struct resource **best_p = gp;
+ struct resource *best;
+
+ best = *best_p;
+ if (!best || (best->base > new->base))
+ best = new;
+ *best_p = best;
+}
+
+static u32 find_pci_tolm(struct bus *bus)
+{
+ struct resource *min;
+ u32 tolm;
+
+ printk(BIOS_DEBUG, "Entering find_pci_tolm\n");
+
+ min = 0;
+ search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM,
+ tolm_test, &min);
+ tolm = 0xffffffffUL;
+ if (min && tolm > min->base)
+ tolm = min->base;
+
+ printk(BIOS_DEBUG, "Leaving find_pci_tolm\n");
+
+ return tolm;
+}
+
+static const u8 ramregs[4] = {0x43, 0x42, 0x41, 0x40};
+
+static void cn700_pci_domain_set_resources(struct device *dev)
+{
+ struct device *mc_dev;
+ u32 pci_tolm, tomk, tolmk;
+ u8 rambits;
+ int i, idx;
+
+ printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n");
+
+#if 0
+ if(!(pci_read_config8(dev, 0xe0) & (1 << 7)) || !(pci_read_config8(dev, 0x4f) & 1))
+ {
+ printk(BIOS_DEBUG, "Northbridge multifunction disabled, re-enabling");
+ rambits = pci_read_config8(dev, 0x4f);
+ rambits |= 1;
+ pci_write_config8(dev, 0x4f, rambits);
+ } else
+ printk(BIOS_DEBUG, "Northrbidge multifunction enabled");
+#endif
+
+ pci_tolm = find_pci_tolm(&dev->link[0]);
+ mc_dev = dev_find_pci_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);
+
+
+ /*
+ * Once the register value is not zero, the RAM size is
+ * this register's value multiply 64 * 1024 * 1024.
+ */
+ for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
+ rambits = pci_read_config8(mc_dev, ramregs[i]);
+ if (rambits != 0)
+ break;
+ }
+
+ tomk = rambits * 64 * 1024;
+ printk(BIOS_SPEW, "tomk is 0x%x\n", tomk);
+ /* Compute the Top Of Low Memory (TOLM), in Kb. */
+ tolmk = pci_tolm >> 10;
+ if (tolmk >= tomk) {
+ /* The PCI hole does does not overlap the memory. */
+ tolmk = tomk;
+ }
+ /* Report the memory regions. */
+ idx = 10;
+ /* TODO: Hole needed? */
+ ram_resource(dev, idx++, 0, 640); /* First 640k */
+ /* Leave a hole for VGA, 0xa0000 - 0xc0000 */
+ ram_resource(dev, idx++, 768,
+ (tolmk - 768 - (CONFIG_CN700_VIDEO_MB * 1024)));
+ phase4_assign_resources(&dev->link[0]);
+}
+
+/** Operations for when the northbridge is running a PCI domain. */
+struct device_operations cn700_north_domain = {
+ .id = {.type = DEVICE_ID_PCI_DOMAIN,
+ {.pci_domain = {.vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_CN700_AGP}}},
+ .constructor = default_device_constructor,
+ .phase3_scan = pci_domain_scan_bus,
+ .phase4_read_resources = pci_domain_read_resources,
+ .phase4_set_resources = cn700_pci_domain_set_resources,
+ .phase5_enable_resources = enable_childrens_resources,
+ .phase6_init = 0,
+ .ops_pci_bus = &pci_cf8_conf1,
+};
+
+
Added: coreboot-v3/northbridge/via/cn700/pci_domain.dts
===================================================================
--- coreboot-v3/northbridge/via/cn700/pci_domain.dts (rev 0)
+++ coreboot-v3/northbridge/via/cn700/pci_domain.dts 2008-12-17 21:17:01 UTC (rev 1077)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+{
+ device_operations = "cn700_north_domain";
+};
Deleted: coreboot-v3/northbridge/via/cn700/stage2.c
===================================================================
--- coreboot-v3/northbridge/via/cn700/stage2.c 2008-12-16 22:46:55 UTC (rev 1076)
+++ coreboot-v3/northbridge/via/cn700/stage2.c 2008-12-17 21:17:01 UTC (rev 1077)
@@ -1,146 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA)
- * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <console.h>
-#include <io.h>
-#include <lib.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <arch/x86/cpu.h>
-#include <statictree.h>
-#include <config.h>
-
-static void tolm_test(void *gp, struct device *dev, struct resource *new)
-{
- struct resource **best_p = gp;
- struct resource *best;
-
- best = *best_p;
- if (!best || (best->base > new->base))
- best = new;
- *best_p = best;
-}
-
-static u32 find_pci_tolm(struct bus *bus)
-{
- struct resource *min;
- u32 tolm;
-
- printk(BIOS_DEBUG, "Entering find_pci_tolm\n");
-
- min = 0;
- search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM,
- tolm_test, &min);
- tolm = 0xffffffffUL;
- if (min && tolm > min->base)
- tolm = min->base;
-
- printk(BIOS_DEBUG, "Leaving find_pci_tolm\n");
-
- return tolm;
-}
-
-static const u8 ramregs[4] = {0x43, 0x42, 0x41, 0x40};
-
-static void pci_domain_set_resources(struct device *dev)
-{
- struct device *mc_dev;
- u32 pci_tolm;
-
- printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n");
-
- pci_tolm = find_pci_tolm(&dev->link[0]);
- mc_dev = dev_find_pci_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);
-
- if (mc_dev) {
- u32 tomk, tolmk;
- u8 rambits;
- int i, idx;
-
- /*
- * Once the register value is not zero, the RAM size is
- * this register's value multiply 64 * 1024 * 1024.
- */
- for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
- rambits = pci_read_config8(mc_dev, ramregs[i]);
- if (rambits != 0)
- break;
- }
-
- tomk = rambits * 64 * 1024;
- printk(BIOS_SPEW, "tomk is 0x%x\n", tomk);
- /* Compute the Top Of Low Memory (TOLM), in Kb. */
- tolmk = pci_tolm >> 10;
- if (tolmk >= tomk) {
- /* The PCI hole does does not overlap the memory. */
- tolmk = tomk;
- }
- /* Report the memory regions. */
- idx = 10;
- /* TODO: Hole needed? */
- ram_resource(dev, idx++, 0, 640); /* First 640k */
- /* Leave a hole for VGA, 0xa0000 - 0xc0000 */
- ram_resource(dev, idx++, 768,
- (tolmk - 768 - CONFIG_CN700_VIDEO_MB_32 * 1024));
- }
- phase4_assign_resources(&dev->link[0]);
-}
-
-static void cpu_bus_init(struct device *dev)
-{
-#warning "cpu_bus_init() empty, what should it do?"
- printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
- printk(BIOS_SPEW, ">> Exiting northbridge.c: %s\n", __FUNCTION__);
-}
-
-static void cpu_bus_noop(struct device *dev)
-{
-}
-
-/** Operations for when the northbridge is running a PCI domain. */
-struct device_operations cn700_north_domain = {
- .id = {.type = DEVICE_ID_PCI_DOMAIN,
- {.pci_domain = {.vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_CN700_AGP}}},
- .constructor = default_device_constructor,
- .phase3_scan = pci_domain_scan_bus,
- .phase4_read_resources = pci_domain_read_resources,
- .phase4_set_resources = pci_domain_set_resources,
- .phase5_enable_resources = enable_childrens_resources,
- .phase6_init = 0,
-};
-
-/** Operations for when the northbridge is running an APIC cluster. */
-struct device_operations cn700_north_apic = {
- .id = {.type = DEVICE_ID_APIC_CLUSTER,
- {.apic_cluster = {.vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_CN700_AGP}}},
- .constructor = default_device_constructor,
- .phase3_scan = 0,
- .phase4_read_resources = cpu_bus_noop,
- .phase4_set_resources = cpu_bus_noop,
- .phase5_enable_resources = cpu_bus_noop,
- .phase6_init = cpu_bus_init,
-};
Deleted: coreboot-v3/northbridge/via/cn700/stage2.h
===================================================================
--- coreboot-v3/northbridge/via/cn700/stage2.h 2008-12-16 22:46:55 UTC (rev 1076)
+++ coreboot-v3/northbridge/via/cn700/stage2.h 2008-12-17 21:17:01 UTC (rev 1077)
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef NORTHBRIDGE_VIA_CN700_STAGE2_H
-#define NORTHBRIDGE_VIA_CN700_STAGE2_H
-
-extern unsigned int cn700_scan_root_bus(device_t root, unsigned int max);
-
-#endif
Added: coreboot-v3/northbridge/via/cn700/vga.dts
===================================================================
--- coreboot-v3/northbridge/via/cn700/vga.dts (rev 0)
+++ coreboot-v3/northbridge/via/cn700/vga.dts 2008-12-17 21:17:01 UTC (rev 1077)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+{
+ device_operations = "cn700_vga";
+};
Modified: coreboot-v3/southbridge/via/vt8237/ide.c
===================================================================
--- coreboot-v3/southbridge/via/vt8237/ide.c 2008-12-16 22:46:55 UTC (rev 1076)
+++ coreboot-v3/southbridge/via/vt8237/ide.c 2008-12-17 21:17:01 UTC (rev 1077)
@@ -42,8 +42,11 @@
printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary",
sb->ide1_enable ? "enabled" : "disabled");
enables = pci_read_config8(dev, IDE_CS) & ~0x3;
+ printk(BIOS_DEBUG, "POI1");
enables |= (sb->ide0_enable << 1) | sb->ide1_enable;
+ printk(BIOS_DEBUG, "POI2");
pci_write_config8(dev, IDE_CS, enables);
+ printk(BIOS_DEBUG, "POI3");
enables = pci_read_config8(dev, IDE_CS);
printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables);
@@ -95,11 +98,13 @@
{.pci = {.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_VT8237_PATA}}},
.constructor = default_device_constructor,
- //.phase2_fixup = vt8237_enable,
+ //.phase3_chip_setup_dev = vt8237_init,
//.phase3_scan = 0,
- //.phase4_enable_disable = vt8237_enable,
- //.phase4_read_resources = pci_dev_read_resources,
- //.phase4_set_resources = pci_set_resources,
- //.phase5_enable_resources = pci_dev_enable_resources,
+ .phase4_read_resources = pci_dev_read_resources,
+ .phase4_set_resources = pci_set_resources,
+ .phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ide_init,
+ //.ops_pci = &pci_dev_ops_pci,
+ .ops_pci_bus = &pci_cf8_conf1,
+
};
Modified: coreboot-v3/southbridge/via/vt8237/lpc.c
===================================================================
--- coreboot-v3/southbridge/via/vt8237/lpc.c 2008-12-16 22:46:55 UTC (rev 1076)
+++ coreboot-v3/southbridge/via/vt8237/lpc.c 2008-12-17 21:17:01 UTC (rev 1077)
@@ -448,11 +448,13 @@
{.pci = {.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_VT8237R_LPC}}},
.constructor = default_device_constructor,
+ .phase3_chip_setup_dev = vt8237r_init,
.phase3_scan = scan_static_bus,
.phase4_read_resources = vt8237_read_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = vt8237_enable_resources,
- .phase6_init = vt8237r_init,
+ .phase6_init = NULL,
+ .ops_pci = &pci_dev_ops_pci,
};
struct device_operations vt8237s_lpc = {
Modified: coreboot-v3/southbridge/via/vt8237/sata.c
===================================================================
--- coreboot-v3/southbridge/via/vt8237/sata.c 2008-12-16 22:46:55 UTC (rev 1076)
+++ coreboot-v3/southbridge/via/vt8237/sata.c 2008-12-17 21:17:01 UTC (rev 1077)
@@ -22,11 +22,8 @@
#include <device/pci_ids.h>
#include "vt8237.h"
-/* TODO: use phase2_fixup to disable SATA */
-
-/* Causes coreboot to hang, so moved to stage1 code
- TODO: Fix vt8237s */
-static void sata_i_init(struct device *dev)
+/* TODO: Fix vt8237s */
+void sata_i_init(struct device *dev)
{
u8 reg;
@@ -103,12 +100,14 @@
{.pci = {.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_VT8237R_SATA}}},
.constructor = default_device_constructor,
- //.phase3_scan = 0,
- //.phase4_enable_disable = vt8237_enable,
- //.phase4_read_resources = pci_dev_read_resources,
- //.phase4_set_resources = pci_set_resources,
- //.phase5_enable_resources = pci_dev_enable_resources,
- //.phase6_init = sata_i_init,
+// .phase3_chip_setup_dev = vt8237_init,
+// .phase3_scan = 0,
+ .phase4_read_resources = pci_dev_read_resources,
+ .phase4_set_resources = pci_set_resources,
+ .phase5_enable_resources = pci_dev_enable_resources,
+ .phase6_init = sata_i_init,
+// .ops_pci = &pci_dev_ops_pci,
+ .ops_pci_bus = &pci_cf8_conf1,
};
struct device_operations vt8237s_sata = {
Modified: coreboot-v3/southbridge/via/vt8237/stage1.c
===================================================================
--- coreboot-v3/southbridge/via/vt8237/stage1.c 2008-12-16 22:46:55 UTC (rev 1076)
+++ coreboot-v3/southbridge/via/vt8237/stage1.c 2008-12-17 21:17:01 UTC (rev 1077)
@@ -29,6 +29,8 @@
#include "vt8237.h"
#include <config.h>
+#define SMBUS_DEBUG 0
+
/* TODO List:
* * Merge the rest of the functions from v2, except smbus_fixup which doesn't
* seem to be necessary any more (?)
@@ -50,7 +52,9 @@
if ((host_status == 0x00 || host_status == 0x40 ||
host_status == 0x42) && (loops < SMBUS_TIMEOUT))
{
+#if SMBUS_DEBUG
printk(BIOS_SPEW, "SMBus Ready/Completed Successfully\n");
+#endif
return;
}
if (loops >= SMBUS_TIMEOUT)
@@ -85,7 +89,9 @@
{
int loops;
+#if SMBUS_DEBUG
printk(BIOS_SPEW, "Waiting until SMBus ready\n");
+#endif
loops = 0;
while ((inb(smbus_io_base + SMBHSTSTAT) & 1) == 1 && loops <= SMBUS_TIMEOUT)
@@ -105,8 +111,10 @@
{
u8 val;
+#if SMBUS_DEBUG
printk(BIOS_SPEW, "SMBus Read from DIMM %d at address 0x%x\n",
(int)dimm, offset);
+#endif
smbus_reset(smbus_io_base);
@@ -129,8 +137,11 @@
smbus_wait_until_ready(smbus_io_base);
val = inb(smbus_io_base + SMBHSTDAT0);
+
+#if SMBUS_DEBUG
printk(BIOS_SPEW, "Read: 0x%x\n", val);
-
+#endif
+
/* TODO: Is this necessary? */
smbus_reset(smbus_io_base);
@@ -222,15 +233,16 @@
pci_conf1_find_device(0x1106, 0x3227, &dev);
pci_conf1_find_device(0x1106, 0x0571, &ide_dev);
- /* Disable GP3 timer, or else the system reboots when it runs out */
+ /* Disable GP3 timer, or else the system reboots when it runs out.
+ * Datasheets say this is disabled by default, they're wrong. */
pci_conf1_write_config8(dev, 0x98, 0x00);
/* Change the ROM size mapping based on where CAR is located */
-#if (CONFIG_CARBASE + CONFIG_CARSIZE) < 0xffc00000
+#if (CONFIG_CARBASE + CONFIG_CARSIZE) <= 0xffc00000
pci_conf1_write_config8(dev, 0x41, 0x7f);
-#elif (CONFIG_CARBASE + CONFIG_CARSIZE) < 0xffe00000
+#elif (CONFIG_CARBASE + CONFIG_CARSIZE) <= 0xffe00000
pci_conf1_write_config8(dev, 0x41, 0x70);
-#elif (CONFIG_CARBASE + CONFIG_CARSIZE) < 0xfff00000
+#elif (CONFIG_CARBASE + CONFIG_CARSIZE) <= 0xfff00000
pci_conf1_write_config8(dev, 0x41, 0x40);
#endif
@@ -256,7 +268,7 @@
pci_conf1_write_config8(ide_dev, 0x41, 0xf2);
pci_conf1_write_config8(ide_dev, 0x42, 0x09);
- sata_stage1();
+ //sata_stage1();
enable_smbus(smbus_io_base);
}
