coreboot December 2008

coreboot@coreboot.org

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330 discussions

v3 patches and question
by Myles Watson 19 Dec '08

19 Dec '08

serengeti.diff and dtc-links.diff make serengeti find all of its devices correctly. serengeti.diff - takes out the multiple links for the Opteron (they weren't working correctly) - adds the 8132 devices and makes them pci_a so they don't conflict with the 8111 - corrects the disabled flags (I think we should have a build error somewhere when there are incorrect flags) - moves the lpc device to the lpc bus - adds back in the second Opteron Signed-off-by: Myles Watson <mylesgw(a)gmail.com> dtc-links.diff - removes multiple link code. I know someone could probably fix it, but it's broken and not needed for now. It made siblings that were bridges be multiple links on the same device. That messed a lot of things up for Serengeti. I think it could be changed so that siblings with the same PCI identifier that are bridges become multiple links. It's ugly, though. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> pci_match_v2.diff: Even though Serengeti seems to work the same as v2, it still won't show anything on the display. The VGA device is not claiming the 0xa0000-0xc0000 address space. Since SimNOW is a simulator, I trace the memory space to see that the VGA writes are going to RAM. I put this in to make the PCI config space bit-for-bit identical at VGA ROM run. It still doesn't work. :( Any help would be appreciated. Thanks, Myles

2 6

r1080 - in coreboot-v3: . mainboard/amd mainboard/amd/serengeti southbridge/amd/amd8151
by svn＠coreboot.org 19 Dec '08

19 Dec '08

Author: myles Date: 2008-12-19 03:43:46 +0100 (Fri, 19 Dec 2008) New Revision: 1080 Modified: coreboot-v3/Kconfig coreboot-v3/mainboard/amd/Kconfig coreboot-v3/mainboard/amd/serengeti/defconfig coreboot-v3/mainboard/amd/serengeti/dts coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c Log: This patch makes the 8151 compile and adds it to the amd serengeti board. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: coreboot-v3/Kconfig =================================================================== --- coreboot-v3/Kconfig 2008-12-19 02:40:54 UTC (rev 1079) +++ coreboot-v3/Kconfig 2008-12-19 02:43:46 UTC (rev 1080) @@ -112,6 +112,8 @@ boolean config SOUTHBRIDGE_NVIDIA_MCP55 boolean +config SOUTHBRIDGE_AMD_AMD8151 + boolean config SOUTHBRIDGE_AMD_AMD8132 boolean config SOUTHBRIDGE_AMD_AMD8111 Modified: coreboot-v3/mainboard/amd/Kconfig =================================================================== --- coreboot-v3/mainboard/amd/Kconfig 2008-12-19 02:40:54 UTC (rev 1079) +++ coreboot-v3/mainboard/amd/Kconfig 2008-12-19 02:43:46 UTC (rev 1080) @@ -63,6 +63,7 @@ select NORTHBRIDGE_AMD_K8 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8132 + select SOUTHBRIDGE_AMD_AMD8151 select SUPERIO_WINBOND_W83627HF select IOAPIC help Modified: coreboot-v3/mainboard/amd/serengeti/defconfig =================================================================== --- coreboot-v3/mainboard/amd/serengeti/defconfig 2008-12-19 02:40:54 UTC (rev 1079) +++ coreboot-v3/mainboard/amd/serengeti/defconfig 2008-12-19 02:43:46 UTC (rev 1080) @@ -113,6 +113,7 @@ CONFIG_NORTHBRIDGE_AMD_K8=y CONFIG_SOUTHBRIDGE_AMD_AMD8111=y CONFIG_SOUTHBRIDGE_AMD_AMD8132=y +CONFIG_SOUTHBRIDGE_AMD_AMD8151=y CONFIG_SUPERIO_WINBOND_W83627HF=y # Modified: coreboot-v3/mainboard/amd/serengeti/dts =================================================================== --- coreboot-v3/mainboard/amd/serengeti/dts 2008-12-19 02:40:54 UTC (rev 1079) +++ coreboot-v3/mainboard/amd/serengeti/dts 2008-12-19 02:43:46 UTC (rev 1080) @@ -26,11 +26,24 @@ subsystem_device = "0x2b80"; cpus { }; apic@0 { + /config/("northbridge/amd/k8/apic"); }; domain@0 { /config/("northbridge/amd/k8/domain"); - pci0@18,0 { + pci@18,0 { /config/("northbridge/amd/k8/pci"); + pci_a@0,0 { + /config/("southbridge/amd/amd8132/pcix.dts"); + }; + pci_a@0,1 { + /config/("southbridge/amd/amd8132/apic.dts"); + }; + pci_a@1,0 { + /config/("southbridge/amd/amd8132/pcix.dts"); + }; + pci_a@1,1 { + /config/("southbridge/amd/amd8132/apic.dts"); + }; pci@0,0 { /config/("southbridge/amd/amd8111/pci.dts"); pci@0,0{ @@ -41,15 +54,21 @@ }; pci@0,2{ /config/("southbridge/amd/amd8111/usb2.dts"); - disable; + disabled; }; pci@1,0{ /config/("southbridge/amd/amd8111/nic.dts"); - disable; + disabled; }; }; pci@1,0 { /config/("southbridge/amd/amd8111/lpc.dts"); + ioport@2e { + /config/("superio/winbond/w83627hf/dts"); + kbenable = "1"; + com1enable = "1"; + hwmenable = "1"; + }; }; pci@1,1 { /config/("southbridge/amd/amd8111/ide.dts"); @@ -64,28 +83,34 @@ }; pci@1,5 { /config/("southbridge/amd/amd8111/ac97audio.dts"); + disabled; }; pci@1,6 { /config/("southbridge/amd/amd8111/ac97modem.dts"); + disabled; }; - pci@2,0 { - /config/("southbridge/amd/amd8132/pcix.dts"); + pci@1,7 { }; }; - pci1@18,0 { - /config/("northbridge/amd/k8/pci"); + pci@18,1 {}; + pci@18,2 {}; + pci@18,3 { + /config/("northbridge/amd/k8/mcf3"); }; - pci2@18,0 { + pci@19,0 { /config/("northbridge/amd/k8/pci"); }; - pci@18,1 {}; - pci@18,2 {}; - pci@18,3 {}; + pci@19,1 { + pci@0,0 { + /config/("southbridge/amd/amd8151/agpbridge.dts"); + }; + pci@1,0 { + /config/("southbridge/amd/amd8151/agpdev.dts"); + }; + }; + pci@19,2 {}; + pci@19,3 { + /config/("northbridge/amd/k8/mcf3"); + }; }; - ioport@2e { - /config/("superio/winbond/w83627hf/dts"); - kbenable = "1"; - com1enable = "1"; - hwmenable = "1"; - }; }; Modified: coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c =================================================================== --- coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c 2008-12-19 02:40:54 UTC (rev 1079) +++ coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c 2008-12-19 02:43:46 UTC (rev 1080) @@ -25,7 +25,6 @@ #include <device/pci_ids.h> #include <statictree.h> #include <config.h> -#include "mcp55.h" static void agp3bridge_init(struct device * dev) { @@ -45,7 +44,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_8151_AGP}}}, .constructor = default_device_constructor, - .phase3_scan = pci_scan_bridge + .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, @@ -80,7 +79,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_8151_SYSCTRL}}}, .constructor = default_device_constructor, - .phase4_enable_disable = agp3dev_enable, + .phase3_enable = agp3dev_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources,

1 0

r1079 - coreboot-v3/util/dtc
by svn＠coreboot.org 19 Dec '08

19 Dec '08

Author: myles Date: 2008-12-19 03:40:54 +0100 (Fri, 19 Dec 2008) New Revision: 1079 Modified: coreboot-v3/util/dtc/flattree.c Log: This patch removes the logic for multiple links. It would put siblings that were bridges as separate links. There isn't a board in v3 that needs multiple links yet. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: coreboot-v3/util/dtc/flattree.c =================================================================== --- coreboot-v3/util/dtc/flattree.c 2008-12-18 02:00:55 UTC (rev 1078) +++ coreboot-v3/util/dtc/flattree.c 2008-12-19 02:40:54 UTC (rev 1079) @@ -703,7 +703,7 @@ * There is a good chance we could expand the for loop to contain this first bit of code. * OTOH, the compiler can do it for us, and the initial conditions are clearer this way. */ - if ((! tree->linked) && is_bridge(tree)){ + if (is_bridge(tree)){ struct node *siblings; fprintf(f,"\t.link = {\n"); fprintf(f,"\t\t[%d] = {\n", linkcount); @@ -714,24 +714,6 @@ fprintf(f,"\t\t},\n"); /* now we need to handle our siblings. */ linkcount++; - for_all_siblings(tree, siblings) { - if (is_bridge(siblings) && (!siblings->linked)){ - fprintf(f,"\t\t[%d] = {\n", linkcount); - fprintf(f,"\t\t\t.dev = &dev_%s,\n", siblings->label); - fprintf(f,"\t\t\t.link = %d,\n", linkcount); - if (siblings->children) { - fprintf(f,"\t\t\t.children = &dev_%s\n", siblings->children->label); - siblings->children->linked = 1; - siblings->children->linknode = tree; - siblings->children->whichlink = linkcount; - } - fprintf(f,"\t\t},\n"); - siblings->linked = 1; - siblings->whichlink = linkcount; - siblings->linknode = tree; - linkcount++; - } - } fprintf(f,"\t},\n"); } fprintf(f,"\t.links = %d,\n", linkcount);

1 0

r3820 build service
by coreboot information 18 Dec '08

18 Dec '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "cozzie" checked in revision 3820 to the coreboot source repository and caused the following changes: Change Log: Fix the only implicit declaration before it becomes an error. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Build Log: Compilation of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3820&device=m2v-mx_se&vend… If something broke during this checkin please be a pain in cozzie's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3819 build service
by coreboot information 18 Dec '08

18 Dec '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "cozzie" checked in revision 3819 to the coreboot source repository and caused the following changes: Change Log: Fix implicit declaration in cn700/vt8237 code Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3819&device=m2v-mx_se&vend… If something broke during this checkin please be a pain in cozzie's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3820 - trunk/coreboot-v2/src/northbridge/intel/i82810
by svn＠coreboot.org 18 Dec '08

18 Dec '08

Author: cozzie Date: 2008-12-18 20:53:11 +0100 (Thu, 18 Dec 2008) New Revision: 3820 Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c Log: Fix the only implicit declaration before it becomes an error. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c 2008-12-18 19:37:11 UTC (rev 3819) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c 2008-12-18 19:53:11 UTC (rev 3820) @@ -27,6 +27,7 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> +#include <cpu/cpu.h> #include "chip.h" #include "northbridge.h" #include "i82810.h"

1 0

r3819 - in trunk/coreboot-v2/src: northbridge/via/cn700 southbridge/via/vt8237r
by svn＠coreboot.org 18 Dec '08

18 Dec '08

Author: cozzie Date: 2008-12-18 20:37:11 +0100 (Thu, 18 Dec 2008) New Revision: 3819 Modified: trunk/coreboot-v2/src/northbridge/via/cn700/vga.c trunk/coreboot-v2/src/northbridge/via/cn700/vgachip.h trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.c trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c Log: Fix implicit declaration in cn700/vt8237 code Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/northbridge/via/cn700/vga.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cn700/vga.c 2008-12-18 18:24:11 UTC (rev 3818) +++ trunk/coreboot-v2/src/northbridge/via/cn700/vga.c 2008-12-18 19:37:11 UTC (rev 3819) @@ -36,6 +36,7 @@ #include "chip.h" #include "northbridge.h" #include "cn700.h" +#include "vgachip.h" void write_protect_vgabios(void) { Modified: trunk/coreboot-v2/src/northbridge/via/cn700/vgachip.h =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cn700/vgachip.h 2008-12-18 18:24:11 UTC (rev 3818) +++ trunk/coreboot-v2/src/northbridge/via/cn700/vgachip.h 2008-12-18 19:37:11 UTC (rev 3819) @@ -27,4 +27,9 @@ int nothing; }; +void vga_enable_console(void); +void do_vgabios(void); +void setup_realmode_idt(void); +void write_protect_vgabios(void); + #endif /* _PC80_VGABIOS */ Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.c 2008-12-18 18:24:11 UTC (rev 3818) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.c 2008-12-18 19:37:11 UTC (rev 3819) @@ -21,7 +21,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <pc80/keyboard.h> #include "chip.h" /* Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2008-12-18 18:24:11 UTC (rev 3818) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2008-12-18 19:37:11 UTC (rev 3819) @@ -26,6 +26,7 @@ #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> #include <cpu/x86/lapic.h> +#include <pc80/keyboard.h> #include <stdlib.h> #include "vt8237r.h" #include "chip.h" @@ -46,6 +47,7 @@ #define INT (1 << 8) extern void dump_south(device_t dev); +extern void setup_i8259(void); static struct ioapicreg { u32 reg;

1 0

r3818 - in trunk/coreboot-v2/src: arch/i386/include/arch cpu/x86/lapic include/device northbridge/amd/amdk8 southbridge/amd/amd8111
by svn＠coreboot.org 18 Dec '08

18 Dec '08

Author: myles Date: 2008-12-18 19:24:11 +0100 (Thu, 18 Dec 2008) New Revision: 3818 Modified: trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c trunk/coreboot-v2/src/include/device/pci.h trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111.c trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_nic.c Log: This patch gets rid of all the implicit definition warnings for serengeti except get_nodes. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h 2008-12-18 02:18:45 UTC (rev 3817) +++ trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h 2008-12-18 18:24:11 UTC (rev 3818) @@ -317,6 +317,8 @@ unsigned long acpi_create_srat_lapics(unsigned long current); void acpi_create_srat(acpi_srat_t *srat); +void acpi_create_slit(acpi_slit_t *slit); + void acpi_create_hpet(acpi_hpet_t *hpet); void acpi_create_mcfg(acpi_mcfg_t *mcfg); Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2008-12-18 02:18:45 UTC (rev 3817) +++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2008-12-18 18:24:11 UTC (rev 3818) @@ -435,6 +435,8 @@ #if WAIT_BEFORE_CPUS_INIT==0 #define cpus_ready_for_init() do {} while(0) +#else + void cpus_ready_for_init(void); #endif #if HAVE_SMI_HANDLER Modified: trunk/coreboot-v2/src/include/device/pci.h =================================================================== --- trunk/coreboot-v2/src/include/device/pci.h 2008-12-18 02:18:45 UTC (rev 3817) +++ trunk/coreboot-v2/src/include/device/pci.h 2008-12-18 18:24:11 UTC (rev 3818) @@ -72,6 +72,10 @@ unsigned pci_find_capability(device_t dev, unsigned cap); struct resource *pci_get_resource(struct device *dev, unsigned long index); void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device); +void pci_dev_init(struct device *dev); +void pci_level_irq(unsigned char intNum); +void pci_assign_irqs(unsigned bus, unsigned slot, + const unsigned char pIntAtoD[4]); #define PCI_IO_BRIDGE_ALIGN 4096 #define PCI_MEM_BRIDGE_ALIGN (1024*1024) Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h 2008-12-18 02:18:45 UTC (rev 3817) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h 2008-12-18 18:24:11 UTC (rev 3818) @@ -521,6 +521,8 @@ #ifdef __ROMCC__ static void soft_reset(void); +#else +void hard_reset(void); #endif static void wait_all_core0_mem_trained(struct sys_info *sysinfo) Modified: trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111.c 2008-12-18 02:18:45 UTC (rev 3817) +++ trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111.c 2008-12-18 18:24:11 UTC (rev 3818) @@ -11,7 +11,7 @@ unsigned index; unsigned reg_old, reg; - /* See if we are on the behind the amd8111 pci bridge */ + /* See if we are on the bus behind the amd8111 pci bridge */ bus_dev = dev->bus->dev; if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) && (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) Modified: trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_nic.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_nic.c 2008-12-18 02:18:45 UTC (rev 3817) +++ trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_nic.c 2008-12-18 18:24:11 UTC (rev 3818) @@ -7,6 +7,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <arch/io.h> +#include <delay.h> #include "amd8111.h"

1 0

More v3 questions/issues
by Corey Osgood 18 Dec '08

18 Dec '08

Alright, the good is that memtest boots now. The bad: -Memtest thinks there's no memory, because... -None of the cn700 stage2 drivers are running -And any pci read/write operation in phase6 seems to lock up coreboot, maybe because of a lack of memory? I'm thinking the cn700 drivers are probably not running due to them not having their own dts files or entries in the mainboard dts. If that's the case, how do I represent d0f0, which acts as a PCI device, PCI domain, and CPU bus controller, and needs drivers for all 3? Thanks, Corey

5 27

r3817 - trunk/coreboot-v2/src/cpu/via/model_c7
by svn＠coreboot.org 18 Dec '08

18 Dec '08

Author: cozzie Date: 2008-12-18 03:18:45 +0100 (Thu, 18 Dec 2008) New Revision: 3817 Modified: trunk/coreboot-v2/src/cpu/via/model_c7/model_c7_init.c Log: Add another CPUID to the Via C7's table, the one on my Jetway J7F2. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: trunk/coreboot-v2/src/cpu/via/model_c7/model_c7_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/via/model_c7/model_c7_init.c 2008-12-17 02:14:24 UTC (rev 3816) +++ trunk/coreboot-v2/src/cpu/via/model_c7/model_c7_init.c 2008-12-18 02:18:45 UTC (rev 3817) @@ -217,6 +217,7 @@ static struct cpu_device_id cpu_table[] = { {X86_VENDOR_CENTAUR, 0x06A0}, // VIA C7 Esther + {X86_VENDOR_CENTAUR, 0x06A9}, // VIA C7 Esther {X86_VENDOR_CENTAUR, 0x06D0}, // VIA C7-M {0, 0}, };

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coreboot December 2008