coreboot December 2008

coreboot@coreboot.org

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330 discussions

Wiki (Add a ROM field which lists the BIOS chip type)
by Joseph Smith 20 Dec '08

20 Dec '08

Hello, I noticed the Supported Motherboards page was updated to list the flash info. Wouldn't it make more sense to put this info on the flashrom page??? Supported Motherboards page I can agree with a socked/non-socketed column. I think there should just be two columns. One with the flash vender/model info like we do with the northbridge, southbridge, superio, etc and one with socked/non-socketed. Everything else should go to flashrom. P.S. There are many dirrerent size PLCC packages. We may want to change this to PLCC32. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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r3828 build service
by coreboot information 20 Dec '08

20 Dec '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "cozzie" checked in revision 3828 to the coreboot source repository and caused the following changes: Change Log: Fix dell/s1850 broken in r3822, and prepare it for implicit declaration error patch. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Build Log: Compilation of dell:s1850 has been fixed If something broke during this checkin please be a pain in cozzie's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3828 - trunk/coreboot-v2/src/mainboard/dell/s1850
by svn＠coreboot.org 20 Dec '08

20 Dec '08

Author: cozzie Date: 2008-12-20 22:07:20 +0100 (Sat, 20 Dec 2008) New Revision: 3828 Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/reset.c Log: Fix dell/s1850 broken in r3822, and prepare it for implicit declaration error patch. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/reset.c =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/reset.c 2008-12-20 19:35:54 UTC (rev 3827) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/reset.c 2008-12-20 21:07:20 UTC (rev 3828) @@ -1,9 +1,9 @@ #include <arch/io.h> -#include <device/pci.h> + #include <device/pci_def.h> #include <device/pci_ids.h> #ifndef __ROMCC__ -#include <device/device.h> +#include <device/pci.h> #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) #define PCI_DEV_INVALID 0 @@ -12,6 +12,8 @@ { return dev_find_device(pci_id >> 16, pci_id & 0xffff, from); } +#else +#include <arch/romcc_io.h> #endif void soft_reset(void)

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[PATCH] superiotool: Add register dump map for NSC PC8739x
by Michał Mirosław 20 Dec '08

20 Dec '08

This adds register map based on NSC PC87392 datasheet. Tested on my laptop. rechot superiotool # ./superiotool superiotool r3784 Found NSC PC8739x (sid=0xea, srid=0x03) at 0x2e Signed-off-by: Michał Mirosław <mirq-linux(a)rere.qmqm.pl> Index: util/superiotool/nsc.c =================================================================== --- util/superiotool/nsc.c (wersja 3825) +++ util/superiotool/nsc.c (kopia robocza) @@ -308,6 +308,42 @@ /* SID[7..0]: family, SRID[7..5]: ID, SRID[4..0]: rev. */ {0xea, "PC8739x", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, + 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0xea,0x11,MISC,MISC,MISC,0x80,0x00,NANA,0x00,MISC, + 0x37,RSVD,RSVD,RSVD,RSVD,RSVD,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT}, + {0x00,0x03,0xf2,0x06,0x03,0x02,0x04,0x24,0x00,EOT}}, + {0x1, "Parallel port", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0x78,0x07,0x02,0x04,0x04,0xf2,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}}, + {0x3, "COM1", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}}, + {0x7, "GPIO", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2, + EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,0x44,0x01, + EOT}}, + {0xa, "Watchdog timer (WDT)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x02,EOT}}, + {0xb, "Game port", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0x01,0x00,0x03,0x04,0x04,0x00,EOT}}, + {0xc, "MIDI port", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x03,0x30,0x00,0x03,0x04,0x04,0x00,EOT}}, + {0xf, "X-Bus", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, {EOT}}}, {0xec, "PC87591x", { /* SRID[7..5]: 000=PC87591E, 001=PC87591S, 100=PC87591L */

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r3827 build service
by coreboot information 20 Dec '08

20 Dec '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "cozzie" checked in revision 3827 to the coreboot source repository and caused the following changes: Change Log: This adds register map based on NSC PC87392 datasheet. LDN#2 can be used for a SIR/FIR device. Signed-off-by: Michał Mirosław <mirq-linux(a)rere.qmqm.pl> Acked-by: Ulf Jordan <jordan(a)chalmers.se> Build Log: Compilation of dell:s1850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3827&device=s1850&vendor=d… If something broke during this checkin please be a pain in cozzie's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3827 - trunk/util/superiotool
by svn＠coreboot.org 20 Dec '08

20 Dec '08

Author: cozzie Date: 2008-12-20 20:35:54 +0100 (Sat, 20 Dec 2008) New Revision: 3827 Modified: trunk/util/superiotool/nsc.c Log: This adds register map based on NSC PC87392 datasheet. LDN#2 can be used for a SIR/FIR device. Signed-off-by: Micha?\197?\130 Miros?\197?\130aw <mirq-linux(a)rere.qmqm.pl> Acked-by: Ulf Jordan <jordan(a)chalmers.se> Modified: trunk/util/superiotool/nsc.c =================================================================== --- trunk/util/superiotool/nsc.c 2008-12-20 04:08:40 UTC (rev 3826) +++ trunk/util/superiotool/nsc.c 2008-12-20 19:35:54 UTC (rev 3827) @@ -308,6 +308,42 @@ /* SID[7..0]: family, SRID[7..5]: ID, SRID[4..0]: rev. */ {0xea, "PC8739x", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, + 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0xea,0x11,MISC,MISC,MISC,0x80,0x00,NANA,0x00,MISC, + 0x37,RSVD,RSVD,RSVD,RSVD,RSVD,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT}, + {0x00,0x03,0xf2,0x06,0x03,0x02,0x04,0x24,0x00,EOT}}, + {0x1, "Parallel port", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0x78,0x07,0x02,0x04,0x04,0xf2,EOT}}, + {0x2, "COM2 / FIR", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}}, + {0x3, "COM1", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}}, + {0x7, "GPIO", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2, + EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,0x44,0x01, + EOT}}, + {0xa, "Watchdog timer (WDT)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x02,EOT}}, + {0xb, "Game port", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0x01,0x00,0x03,0x04,0x04,0x00,EOT}}, + {0xc, "MIDI port", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x03,0x30,0x00,0x03,0x04,0x04,0x00,EOT}}, + {0xf, "X-Bus", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, {EOT}}}, {0xec, "PC87591x", { /* SRID[7..5]: 000=PC87591E, 001=PC87591S, 100=PC87591L */

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[PATCH 2/2] inteltool: Add support for dumping ICH5 registers
by Michał Mirosław 20 Dec '08

20 Dec '08

Intel ICH5 is very similar to its predecessor - ICH4. There are small differences are in power-management registers. Signed-off-by: Michał Mirosław <mirq-linux(a)rere.qmqm.pl> Index: util/inteltool/gpio.c =================================================================== --- util/inteltool/gpio.c (wersja 3826) +++ util/inteltool/gpio.c (kopia robocza) @@ -119,6 +119,7 @@ gpio_registers = ich7_gpio_registers; size = ARRAY_SIZE(ich7_gpio_registers); break; + case PCI_DEVICE_ID_INTEL_ICH5: case PCI_DEVICE_ID_INTEL_ICH4: case PCI_DEVICE_ID_INTEL_ICH4M: gpiobase = pci_read_word(sb, 0x58) & 0xfffc; Index: util/inteltool/inteltool.h =================================================================== --- util/inteltool/inteltool.h (wersja 3826) +++ util/inteltool/inteltool.h (kopia robocza) @@ -37,6 +37,7 @@ #define PCI_DEVICE_ID_INTEL_ICH2 0x2440 #define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 #define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc +#define PCI_DEVICE_ID_INTEL_ICH5 0x24d0 #define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 Index: util/inteltool/powermgt.c =================================================================== --- util/inteltool/powermgt.c (wersja 3826) +++ util/inteltool/powermgt.c (kopia robocza) @@ -21,6 +21,56 @@ #include <stdio.h> #include "inteltool.h" +static const io_register_t ich5_pm_registers[] = { + { 0x00, 2, "PM1_STS" }, + { 0x02, 2, "PM1_EN" }, + { 0x04, 4, "PM1_CNT" }, + { 0x08, 4, "PM1_TMR" }, + { 0x0c, 4, "RESERVED" }, + { 0x10, 4, "PROC_CNT" }, + { 0x14, 4, "RESERVED" }, + { 0x18, 4, "RESERVED" }, + { 0x1c, 4, "RESERVED" }, + { 0x20, 4, "RESERVED" }, + { 0x24, 4, "RESERVED" }, + { 0x28, 4, "GPE0_STS" }, + { 0x2C, 4, "GPE0_EN" }, + { 0x30, 4, "SMI_EN" }, + { 0x34, 4, "SMI_STS" }, + { 0x38, 2, "ALT_GP_SMI_EN" }, + { 0x3a, 2, "ALT_GP_SMI_STS" }, + { 0x3c, 4, "RESERVED" }, + { 0x40, 2, "MON_SMI" }, + { 0x42, 2, "RESERVED" }, + { 0x44, 2, "DEVACT_STS" }, + { 0x46, 2, "RESERVED" }, + { 0x48, 2, "DEVTRAP_EN" }, + { 0x4a, 2, "RESERVED" }, + { 0x4c, 4, "RESERVED" }, + { 0x50, 4, "RESERVED" }, + { 0x54, 4, "RESERVED" }, + { 0x58, 4, "RESERVED" }, + { 0x5c, 4, "RESERVED" }, + /* Here start the TCO registers */ + { 0x60, 1, "TCO_RLD" }, + { 0x61, 1, "TCO_TMR" }, + { 0x62, 1, "TCO_DAT_IN" }, + { 0x63, 1, "TCO_DAT_OUT" }, + { 0x64, 2, "TCO1_STS" }, + { 0x66, 2, "TCO2_STS" }, + { 0x68, 2, "TCO1_CNT" }, + { 0x6a, 2, "TCO2_CNT" }, + { 0x6c, 2, "TCO_MESSAGE" }, + { 0x6e, 1, "TCO_WDCNT" }, + { 0x6f, 1, "RESERVED" }, + { 0x70, 1, "SW_IRQ_GEN" }, + { 0x71, 1, "RESERVED" }, + { 0x72, 2, "RESERVED" }, + { 0x74, 4, "RESERVED" }, + { 0x78, 4, "RESERVED" }, + { 0x7c, 4, "RESERVED" }, +}; + static const io_register_t ich7_pm_registers[] = { { 0x00, 2, "PM1_STS" }, { 0x02, 2, "PM1_EN" }, @@ -154,6 +204,11 @@ printf("\n============= PMBASE ============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_ICH5: + pmbase = pci_read_word(sb, 0x40) & 0xfffc; + pm_registers = ich5_pm_registers; + size = ARRAY_SIZE(ich5_pm_registers); + break; case PCI_DEVICE_ID_INTEL_ICH7: case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: Index: util/inteltool/rootcmplx.c =================================================================== --- util/inteltool/rootcmplx.c (wersja 3826) +++ util/inteltool/rootcmplx.c (kopia robocza) @@ -42,6 +42,7 @@ case PCI_DEVICE_ID_INTEL_ICH0: case PCI_DEVICE_ID_INTEL_ICH4: case PCI_DEVICE_ID_INTEL_ICH4M: + case PCI_DEVICE_ID_INTEL_ICH5: printf("This southbridge does not have RCBA.\n"); return 1; default: Index: util/inteltool/inteltool.c =================================================================== --- util/inteltool/inteltool.c (wersja 3826) +++ util/inteltool/inteltool.c (kopia robocza) @@ -40,6 +40,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH5, "ICH5" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },

1 1

[PATCH 1/2] inteltool: Add support for dumping i865 registers
by Michał Mirosław 20 Dec '08

20 Dec '08

Intel 82865P/PE northbridge uses special device #6 (called Overflow Device in datasheet) for keeping the MCH registers. This device is usually hidden by BIOS and can be enabled by setting bit 1 (0x02) in PCI config register 0xF4 in device 00:00.0 (the NB device) and using fake-php to rescan PCI bus. Signed-off-by: Michał Mirosław <mirq-linux(a)rere.qmqm.pl> Index: util/inteltool/inteltool.h =================================================================== --- util/inteltool/inteltool.h (wersja 3826) +++ util/inteltool/inteltool.h (kopia robocza) @@ -44,6 +44,7 @@ #define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 #define PCI_DEVICE_ID_INTEL_82845 0x1a30 +#define PCI_DEVICE_ID_INTEL_82865P 0x2570 #define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 #define PCI_DEVICE_ID_INTEL_PM965 0x2a00 @@ -61,7 +62,7 @@ unsigned int cpuid(unsigned int op); int print_intel_core_msrs(void); -int print_mchbar(struct pci_dev *nb); +int print_mchbar(struct pci_dev *nb, struct pci_dev *d6); int print_pmbase(struct pci_dev *sb); int print_rcba(struct pci_dev *sb); int print_gpios(struct pci_dev *sb); Index: util/inteltool/pcie.c =================================================================== --- util/inteltool/pcie.c (wersja 3826) +++ util/inteltool/pcie.c (kopia robocza) @@ -42,7 +42,7 @@ epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; - case 0x1234: // Dummy for non-existent functionality + case PCI_DEVICE_ID_INTEL_82865P: printf("This northbrigde does not have EPBAR.\n"); return 1; default: @@ -88,7 +88,7 @@ dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; break; - case 0x1234: // Dummy for non-existent functionality + case PCI_DEVICE_ID_INTEL_82865P: printf("This northbrigde does not have DMIBAR.\n"); return 1; default: @@ -136,8 +136,8 @@ pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; - case 0x1234: // Dummy for non-existent functionality - printf("Error: This northbrigde does not have PCIEXBAR.\n"); + case PCI_DEVICE_ID_INTEL_82865P: + printf("This northbrigde does not have PCIEXBAR.\n"); return 1; default: printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n"); Index: util/inteltool/memory.c =================================================================== --- util/inteltool/memory.c (wersja 3826) +++ util/inteltool/memory.c (kopia robocza) @@ -25,7 +25,7 @@ /* * (G)MCH MMIO Config Space */ -int print_mchbar(struct pci_dev *nb) +int print_mchbar(struct pci_dev *nb, struct pci_dev *d6) { int i, size = (16 * 1024); volatile uint8_t *mchbar; @@ -43,6 +43,14 @@ mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; break; + case PCI_DEVICE_ID_INTEL_82865P: + if (!d6) { + printf("Can't dump MCHBAR as this northbrigde's device #6 was hidden by BIOS.\n"); + return 1; + } + mchbar_phys = pci_read_long(d6, 0x10) & 0xfffffffe; + size = 4 * 1024; + break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have MCHBAR.\n"); return 1; Index: util/inteltool/inteltool.c =================================================================== --- util/inteltool/inteltool.c (wersja 3826) +++ util/inteltool/inteltool.c (kopia robocza) @@ -30,6 +30,7 @@ char *name; } supported_chips_list[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865P, "i865P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" }, @@ -108,7 +110,7 @@ int main(int argc, char *argv[]) { struct pci_access *pacc; - struct pci_dev *sb, *nb; + struct pci_dev *sb, *nb, *d6; int i, opt, option_index = 0; unsigned int id; @@ -227,6 +229,10 @@ exit(1); } + d6 = pci_get_dev(pacc, 0, 0, 0x06, 0); + if (d6) + pci_fill_info(d6, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS); + id = cpuid(1); printf("Intel CPU: Family %x, Model %x\n", (id >> 8) & 0xf, (id >> 4) & 0xf); @@ -263,7 +269,7 @@ } if (dump_mchbar) { - print_mchbar(nb); + print_mchbar(nb, d6); printf("\n\n"); } @@ -288,6 +294,8 @@ } /* Clean up */ + if (d6) + pci_free_dev(d6); pci_free_dev(nb); pci_free_dev(sb); pci_cleanup(pacc);

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r85 - trunk/filo
by svn＠coreboot.org 20 Dec '08

20 Dec '08

Author: uwe Date: 2008-12-20 12:23:33 +0100 (Sat, 20 Dec 2008) New Revision: 85 Modified: trunk/filo/build.sh Log: Make build.sh executable (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Property changes on: trunk/filo/build.sh ___________________________________________________________________ Added: svn:executable + *

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r3826 build service
by coreboot information 20 Dec '08

20 Dec '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stuge" checked in revision 3826 to the coreboot source repository and caused the following changes: Change Log: This adds a mptable for the VIA pc2500e. I've tested with the devices in the VT8237R, and a card interrupting at Pin-A on either PCI slot. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of dell:s1850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3826&device=s1850&vendor=d… If something broke during this checkin please be a pain in stuge's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot December 2008