coreboot December 2008

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Trac reminder: list of new ticket(s)
by coreboot tracker 15 Dec '08

15 Dec '08

1 0

Interesting (part of) article.
by pk 15 Dec '08

15 Dec '08

Hi, Don't know if this is of any interest but I think the first part ("BIOS Ridiculousness...") relates somewhat of what you are trying to accomplish here. There really should be more interest from motherboard manufacturers in coreboot than there are... http://anandtech.com/mb/showdoc.aspx?i=3471 Best regards Peter Karlsson

9 21

Error Compiling Coreboot v1 for Acer WT300
by Holden Hao 15 Dec '08

15 Dec '08

Hello. I am trying to build a Coreboot v1 BIOS with an Etherboot payload for an Acer WT300 thin client. Somebody was already successful in running LinuxBIOS with etherboot on it. ( http://spritesmods.com/?art=wtcluster ). I have tried to contact the person on the website already but he has not replied to me. So I am trying out Coreboot myself. The Acer WT300 has a board similar in specifications to a Supertek ST3WT. The chips on the board are CS5530A and PC973717. My build system is Debian Etch and CentOS 5. I have tried building sample images using default config files but all my efforts failed. I was able to run the python script but I did not get far running make. I get the errors below: ---------------------- cp /home/holden/src/coreboot-v1/src/arch/i386/config/crt0.base crt0.S gcc -x assembler-with-cpp -DASSEMBLY -E ... crt0.S > crt0.s /bin/sh: -c: line 0: unexpected EOF while looking for matching `'' /bin/sh: -c: line 1: syntax error: unexpected end of file make: *** [crt0.s] Error 2 ---------------------- I get the same errors in Debian and CentOS for all config files I have tried. The error above is the same as the one reported on the link below: http://www.coreboot.org/pipermail/coreboot/2007-June/022422.html I hope somebody can help me with the problem. I have about 10 of the Acer WTs that I hope to use as Linux Thin Clients. The units will be used for our organization's (a LUG called DabaweGNU) computer lab. Regards, Holden

3 4

LPCflasher rename to Paraflasher
by Joseph Smith 15 Dec '08

15 Dec '08

Hello, I was thinking of renaming the LPCflasher Project to the Paraflasher Project. It will have the ability to flash more than just LPC chips so I think it should have a more generalized name hence the Paraflasher (Parallel Port Flasher) Project. What does everyone think? If no one strongly disagrees I will go ahead and change it. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

3 7

[PATCH] v2: ASUS P2B-DS support
by Uwe Hermann 15 Dec '08

15 Dec '08

See patch. This is a dual-CPU Intel 440BX board. The current patch boots fine into Linux _iff_ you use 'nosmp' or 'maxcpus=0'. I'm doing some stuff in coreboot to init the two CPUs, but I probably got some parts wrong or there is something missing. If I omit 'nosmp' the boot will hang at the poing where Linux tries to detect IDE drives. If you have any ideas how to debug or fix this, please let me know. Either way, as it boots into Linux I think this is ready to go into svn, further fixes will follow. See http://www.coreboot.org/ASUS_P2B-DS for the current board status. Bootlog attached. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

r3815 - in trunk/coreboot-v2: src/mainboard/asus src/mainboard/asus/p2b-ds targets/asus targets/asus/p2b-ds
by svn＠coreboot.org 15 Dec '08

15 Dec '08

Author: uwe Date: 2008-12-15 13:15:49 +0100 (Mon, 15 Dec 2008) New Revision: 3815 Added: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Config.lb trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b-ds/auto.c trunk/coreboot-v2/src/mainboard/asus/p2b-ds/chip.h trunk/coreboot-v2/src/mainboard/asus/p2b-ds/irq_tables.c trunk/coreboot-v2/src/mainboard/asus/p2b-ds/mainboard.c trunk/coreboot-v2/src/mainboard/asus/p2b-ds/mptable.c trunk/coreboot-v2/targets/asus/p2b-ds/ trunk/coreboot-v2/targets/asus/p2b-ds/Config.lb Log: Add initial support for the ASUS P2B-DS (dual-CPU) mainboard. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Config.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Config.lb 2008-12-15 12:15:49 UTC (rev 3815) @@ -0,0 +1,144 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +dir /pc80 +config chip.h + +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 1 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.9 on # GPIO 3 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 4.1 on end # IDE + device pci 4.2 on end # USB + device pci 4.3 on end # ACPI + device pci 6.0 on end # Onboard SCSI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "1" + register "ide0_drive1_udma33_enable" = "1" + register "ide1_drive0_udma33_enable" = "1" + register "ide1_drive1_udma33_enable" = "1" + end + end +end Added: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb 2008-12-15 12:15:49 UTC (rev 3815) @@ -0,0 +1,106 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses COREBOOT_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_PRECOMPRESSED_PAYLOAD +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses CONFIG_SMP +uses CONFIG_MAX_CPUS +uses CONFIG_IOAPIC + +default ROM_SIZE = 256 * 1024 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 1 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default HAVE_OPTION_TABLE = 0 +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CONFIG_SMP = 1 +default CONFIG_MAX_CPUS = 2 +default CONFIG_IOAPIC = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 9 +default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_CONSOLE_VGA = 1 +default CONFIG_PCI_ROM_RUN = 1 + +end Added: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/auto.c 2008-12-15 12:15:49 UTC (rev 3815) @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include <stdlib.h> +#include <cpu/x86/lapic.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "northbridge/intel/i440bx/raminit.h" +#include "lib/debug.c" +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "superio/winbond/w83977tf/w83977tf_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i440bx/raminit.c" +#include "northbridge/intel/i440bx/debug.c" + +static void main(unsigned long bist) +{ + if (bist == 0) { + early_mtrr_init(); + enable_lapic(); /* FIXME? */ + } + + w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + report_bist_failure(bist); + enable_smbus(); + /* dump_spd_registers(); */ + sdram_set_registers(); + sdram_set_spd_registers(); + sdram_enable(); + /* ram_check(0, 640 * 1024); */ +} Added: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/chip.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/chip.h 2008-12-15 12:15:49 UTC (rev 3815) @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_asus_p2b_ds_ops; +struct mainboard_asus_p2b_ds_config {}; Added: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/irq_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/irq_tables.c 2008-12-15 12:15:49 UTC (rev 3815) @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x04 << 3) | 0x0, /* Interrupt router device */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x36, /* Checksum */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0}, + {0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0}, + {0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0}, + {0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0}, + {0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, + {0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, + {0x00, (0x06 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/mainboard.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/mainboard.c 2008-12-15 12:15:49 UTC (rev 3815) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_asus_p2b_ds_ops = { + CHIP_NAME("ASUS P2B-DS Mainboard") +}; Added: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/mptable.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/mptable.c 2008-12-15 12:15:49 UTC (rev 3815) @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "COREBOOT"; + static const char productid[12] = "ASUS P2B-DS "; + struct mp_config_table *mc; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + /* Bus: Bus ID Type */ + smp_write_bus(mc, 0, "PCI "); + smp_write_bus(mc, 1, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + { + device_t dev; + struct resource *res; + + dev = dev_find_slot(1, PCI_DEVFN(0x1e, 0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) + smp_write_ioapic(mc, 3, 0x20, res->base); + } + dev = dev_find_slot(1, PCI_DEVFN(0x1c, 0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) + smp_write_ioapic(mc, 4, 0x20, res->base); + } + dev = dev_find_slot(4, PCI_DEVFN(0x1e, 0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) + smp_write_ioapic(mc, 5, 0x20, res->base); + } + dev = dev_find_slot(4, PCI_DEVFN(0x1c, 0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) + smp_write_ioapic(mc, 8, 0x20, res->base); + } + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1, + 0x0, 0x2, 0x0); + smp_write_intsrc(mc, mp_INT, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1, + 0x1, 0x2, 0x1); + smp_write_intsrc(mc, mp_INT, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1, + 0x0, 0x2, 0x2); + smp_write_intsrc(mc, mp_INT, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1, + 0x3, 0x2, 0x3); + smp_write_intsrc(mc, mp_INT, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1, + 0x4, 0x2, 0x4); + smp_write_intsrc(mc, mp_INT, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1, + 0x5, 0x2, 0x5); + smp_write_intsrc(mc, mp_INT, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1, + 0x6, 0x2, 0x6); + smp_write_intsrc(mc, mp_INT, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1, + 0x7, 0x2, 0x7); + smp_write_intsrc(mc, mp_INT, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1, + 0x8, 0x2, 0x8); + smp_write_intsrc(mc, mp_INT, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1, + 0x9, 0x2, 0x9); + smp_write_intsrc(mc, mp_INT, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1, + 0xc, 0x2, 0xc); + smp_write_intsrc(mc, mp_INT, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1, + 0xe, 0x2, 0xe); + smp_write_intsrc(mc, mp_INT, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1, + 0xf, 0x2, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + 0x0, 0x13, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + 0x0, 0x18, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + 0x0, 0x30, 0x2, 0x10); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0, + MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, + 0x1, 0x0, MP_APIC_ALL, 0x1); + + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = + smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} Added: trunk/coreboot-v2/targets/asus/p2b-ds/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asus/p2b-ds/Config.lb (rev 0) +++ trunk/coreboot-v2/targets/asus/p2b-ds/Config.lb 2008-12-15 12:15:49 UTC (rev 3815) @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target p2b-ds +mainboard asus/p2b-ds + +option ROM_SIZE = 256 * 1024 + +option MAINBOARD_VENDOR = "ASUS" +option MAINBOARD_PART_NUMBER = "P2B-DS" + +option IRQ_SLOT_COUNT = 7 + +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 + +option CONFIG_CONSOLE_VGA = 1 +option CONFIG_PCI_ROM_RUN = 1 + +romimage "normal" + option USE_FALLBACK_IMAGE = 0 + option COREBOOT_EXTRA_VERSION = ".0Normal" + payload ../payload.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option COREBOOT_EXTRA_VERSION = ".0Fallback" + payload ../payload.elf +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"

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[flashrom] verified mainboard/chipset MSI694DPro2/VIA-VT82686ABC
by Gsellmann Peter 15 Dec '08

15 Dec '08

I tested flashrom on this board; BIOS file on MSI-site despite extension .exe is a zip-file. TODO: update tables in http://www.coreboot.org/Flashrom Manufacturer: Micro-star international Product: MSI 694D Pro2 Link to manufacturers description: http://global.msi.com.tw/index.php?func=downloaddetail&type=bios&maincat_no… used version of flashrom and chipset info: $ svn info flashrom Path: flashrom URL: https://coreboot.org/repos/trunk/util/flashrom Repository Root: https://coreboot.org/repos Repository UUID: 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 Revision: 3811 Node Kind: directory Schedule: normal Last Changed Author: hailfinger Last Changed Rev: 3809 Last Changed Date: 2008-12-10 11:32:05 +0100 (Wed, 10 Dec 2008) $ sudo /usr/local/sbin/flashrom Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT82C686A/B", enabling flash write... OK. Found chip "EON EN29F002(A)(N)T" (256 KB) at physical address 0xfffc0000. No operations were specified. $ lspci 00:00.0 Host bridge: VIA Technologies, Inc. VT82C693A/694x [Apollo PRO133x] (rev c4) 00:01.0 PCI bridge: VIA Technologies, Inc. VT82C598/694x [Apollo MVP3/Pro133x AGP] 00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South] (rev 40) 00:07.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06) 00:07.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 16) 00:07.3 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 16) 00:07.4 Host bridge: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] (rev 40) 00:0c.0 RAID bus controller: Promise Technology, Inc. PDC20265 (FastTrak100 Lite/Ultra100) (rev 02) 00:0d.0 FireWire (IEEE 1394): Texas Instruments TSB12LV26 IEEE-1394 Controller (Link) 00:0e.0 Ethernet controller: Lite-On Communications Inc LNE100TX (rev 20) 00:0f.0 USB Controller: NEC Corporation USB (rev 43) 00:0f.1 USB Controller: NEC Corporation USB (rev 43) 00:0f.2 USB Controller: NEC Corporation USB 2.0 (rev 04) 00:10.0 Multimedia audio controller: Ensoniq ES1371 [AudioPCI-97] (rev 08) 00:11.0 Communication controller: PLX Technology, Inc. PCI <-> IOBus Bridge (rev 01) 00:12.0 Ethernet controller: VIA Technologies, Inc. VT6102 [Rhine-II] (rev 42) 01:00.0 VGA compatible controller: ATI Technologies Inc Radeon RV100 QY [Radeon 7000/VE] -------- Mit freundlichen Grüßen / With kind regards Peter Gsellmann

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[PATCH] flashrom: generate OPCODES improved
by FENG Yu Ning 15 Dec '08

15 Dec '08

* add a generic preop-opcode-pair table. * rename ich_check_opcodes to ich_init_opcodes. * let ich_init_opcodes do not need to access flashchip structure: . move the definition of struct preop_opcode_pair to a better place . remove preop_opcode_pairs from 'struct flashchip' . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure * call ich_init_opcodes in related ich functions(chip-read, chip-write and direct command), so that the OPCODES generation mechanism finally works. * fix a coding style mistake. Signed-off-by: FENG yu ning <fengyuning1984(a)gmail.com> Index: flashrom/flash.h =================================================================== --- flashrom/flash.h (revision 3809) +++ flashrom/flash.h (working copy) @@ -51,12 +51,6 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -/* for pairing opcodes with their required preop */ -struct preop_opcode_pair { - uint8_t preop; - uint8_t opcode; -}; - struct flashchip { const char *vendor; const char *name; @@ -82,8 +76,6 @@ int (*write) (struct flashchip *flash, uint8_t *buf); int (*read) (struct flashchip *flash, uint8_t *buf); - struct preop_opcode_pair *preop_opcode_pairs; - /* Some flash devices have an additional register space. */ volatile uint8_t *virtual_memory; volatile uint8_t *virtual_registers; Index: flashrom/ichspi.c =================================================================== --- flashrom/ichspi.c (revision 3809) +++ flashrom/ichspi.c (working copy) @@ -152,9 +152,9 @@ /* Common SPI functions */ static inline int find_opcode(OPCODES *op, uint8_t opcode); static inline int find_preop(OPCODES *op, uint8_t preop); -static int generate_opcodes(struct flashchip * flash, OPCODES * op); +static int generate_opcodes(OPCODES * op); static int program_opcodes(OPCODES * op); -int ich_check_opcodes(struct flashchip * flash); +int ich_init_opcodes(); static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, @@ -162,6 +162,23 @@ static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, int offset, int maxdata); +/* for pairing opcodes with their required preop */ +struct preop_opcode_pair { + uint8_t preop; + uint8_t opcode; +}; + +struct preop_opcode_pair pops[] = { + {JEDEC_WREN, JEDEC_BYTE_PROGRAM}, + {JEDEC_WREN, JEDEC_SE}, /* sector erase */ + {JEDEC_WREN, JEDEC_BE_52}, /* block erase */ + {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */ + {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */ + {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */ + {JEDEC_EWSR, JEDEC_WRSR}, + {0,} +}; + OPCODES O_ST_M25P = { { JEDEC_WREN, @@ -204,12 +221,11 @@ return -1; } -static int generate_opcodes(struct flashchip * flash, OPCODES * op) +static int generate_opcodes(OPCODES * op) { - int a, b, i; + int a, b, i; uint16_t preop, optype; uint32_t opmenu[2]; - struct preop_opcode_pair *pair; if (op == NULL) { printf_debug("\n%s: null OPCODES pointer!\n", __FUNCTION__); @@ -257,14 +273,11 @@ for (a = 4; a < 8; a++) op->opcode[a].atomic = 0; - pair = flash->preop_opcode_pairs; - if (pair) { - for (i = 0; pair[i].opcode; i++) { - a = find_opcode(op, pair[i].opcode); - b = find_preop(op, pair[i].preop); - if ((a != -1) && (b != -1)) - op->opcode[a].atomic = (uint8_t) ++b; - } + for (i = 0; pops[i].opcode; i++) { + a = find_opcode(op, pops[i].opcode); + b = find_preop(op, pops[i].preop); + if ((a != -1) && (b != -1)) + op->opcode[a].atomic = (uint8_t) ++b; } return 0; @@ -329,7 +342,7 @@ * It should be called in the ICH7/ICH9/VIA part of each operation driver(i.e. * probe, read, erase, write, etc.) before any command is sent. */ -int ich_check_opcodes(struct flashchip * flash) +int ich_init_opcodes() { int rc = 0; OPCODES *curopcodes_done; @@ -340,7 +353,7 @@ if (ichspi_lock) { printf_debug("Generating OPCODES... "); curopcodes_done = &O_EXISTING; - rc = generate_opcodes(flash, curopcodes_done); + rc = generate_opcodes(curopcodes_done); } else { printf_debug("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; @@ -686,6 +699,8 @@ int page_size = flash->page_size; int maxdata = 64; + ich_init_opcodes(); + if (flashbus == BUS_TYPE_VIA_SPI) { maxdata = 16; } @@ -708,6 +723,8 @@ spi_disable_blockprotect(); + ich_init_opcodes(); + printf("Programming page: \n"); for (i = 0; i < total_size / erase_size; i++) { @@ -747,13 +764,7 @@ uint8_t *data; int count; - /* program opcodes if not already done */ - if (curopcodes == NULL) { - printf_debug("Programming OPCODES... "); - curopcodes = &O_ST_M25P; - program_opcodes(curopcodes); - printf_debug("done\n"); - } + ich_init_opcodes(); /* find cmd in opcodes-table */ for (a = 0; a < 8; a++) {

2 6

r3814 - trunk/util/flashrom
by svn＠coreboot.org 15 Dec '08

15 Dec '08

Author: stuge Date: 2008-12-15 03:32:11 +0100 (Mon, 15 Dec 2008) New Revision: 3814 Modified: trunk/util/flashrom/chipset_enable.c trunk/util/flashrom/flash.h trunk/util/flashrom/ichspi.c Log: * add a generic preop-opcode-pair table. * rename ich_check_opcodes to ich_init_opcodes. * let ich_init_opcodes do not need to access flashchip structure: . move the definition of struct preop_opcode_pair to a better place . remove preop_opcode_pairs from 'struct flashchip' . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure * call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works. * fix a coding style mistake. Signed-off-by: FENG yu ning <fengyuning1984(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2008-12-14 00:01:04 UTC (rev 3813) +++ trunk/util/flashrom/chipset_enable.c 2008-12-15 02:32:11 UTC (rev 3814) @@ -339,6 +339,7 @@ printf("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + ich_init_opcodes(); break; case BUS_TYPE_ICH9_SPI: tmp2 = *(uint16_t *) (spibar + 0); Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-12-14 00:01:04 UTC (rev 3813) +++ trunk/util/flashrom/flash.h 2008-12-15 02:32:11 UTC (rev 3814) @@ -51,12 +51,6 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -/* for pairing opcodes with their required preop */ -struct preop_opcode_pair { - uint8_t preop; - uint8_t opcode; -}; - struct flashchip { const char *vendor; const char *name; @@ -82,8 +76,6 @@ int (*write) (struct flashchip *flash, uint8_t *buf); int (*read) (struct flashchip *flash, uint8_t *buf); - struct preop_opcode_pair *preop_opcode_pairs; - /* Some flash devices have an additional register space. */ volatile uint8_t *virtual_memory; volatile uint8_t *virtual_registers; @@ -537,6 +529,7 @@ int write_en29f002a(struct flashchip *flash, uint8_t *buf); /* ichspi.c */ +int ich_init_opcodes(); int ich_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t * buf); Modified: trunk/util/flashrom/ichspi.c =================================================================== --- trunk/util/flashrom/ichspi.c 2008-12-14 00:01:04 UTC (rev 3813) +++ trunk/util/flashrom/ichspi.c 2008-12-15 02:32:11 UTC (rev 3814) @@ -152,9 +152,8 @@ /* Common SPI functions */ static inline int find_opcode(OPCODES *op, uint8_t opcode); static inline int find_preop(OPCODES *op, uint8_t preop); -static int generate_opcodes(struct flashchip * flash, OPCODES * op); +static int generate_opcodes(OPCODES * op); static int program_opcodes(OPCODES * op); -int ich_check_opcodes(struct flashchip * flash); static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, @@ -162,6 +161,23 @@ static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, int offset, int maxdata); +/* for pairing opcodes with their required preop */ +struct preop_opcode_pair { + uint8_t preop; + uint8_t opcode; +}; + +struct preop_opcode_pair pops[] = { + {JEDEC_WREN, JEDEC_BYTE_PROGRAM}, + {JEDEC_WREN, JEDEC_SE}, /* sector erase */ + {JEDEC_WREN, JEDEC_BE_52}, /* block erase */ + {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */ + {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */ + {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */ + {JEDEC_EWSR, JEDEC_WRSR}, + {0,} +}; + OPCODES O_ST_M25P = { { JEDEC_WREN, @@ -204,12 +220,11 @@ return -1; } -static int generate_opcodes(struct flashchip * flash, OPCODES * op) +static int generate_opcodes(OPCODES * op) { - int a, b, i; + int a, b, i; uint16_t preop, optype; uint32_t opmenu[2]; - struct preop_opcode_pair *pair; if (op == NULL) { printf_debug("\n%s: null OPCODES pointer!\n", __FUNCTION__); @@ -257,14 +272,11 @@ for (a = 4; a < 8; a++) op->opcode[a].atomic = 0; - pair = flash->preop_opcode_pairs; - if (pair) { - for (i = 0; pair[i].opcode; i++) { - a = find_opcode(op, pair[i].opcode); - b = find_preop(op, pair[i].preop); - if ((a != -1) && (b != -1)) - op->opcode[a].atomic = (uint8_t) ++b; - } + for (i = 0; pops[i].opcode; i++) { + a = find_opcode(op, pops[i].opcode); + b = find_preop(op, pops[i].preop); + if ((a != -1) && (b != -1)) + op->opcode[a].atomic = (uint8_t) ++b; } return 0; @@ -323,13 +335,12 @@ return 0; } -/* This function generates OPCODES from or programs OPCODES to the chipset - * according to its SPI configuration lock. +/* This function generates OPCODES from or programs OPCODES to ICH according to + * the chipset's SPI configuration lock. * - * It should be called in the ICH7/ICH9/VIA part of each operation driver(i.e. - * probe, read, erase, write, etc.) before any command is sent. + * It should be called before ICH sends any spi command. */ -int ich_check_opcodes(struct flashchip * flash) +int ich_init_opcodes() { int rc = 0; OPCODES *curopcodes_done; @@ -340,7 +351,7 @@ if (ichspi_lock) { printf_debug("Generating OPCODES... "); curopcodes_done = &O_EXISTING; - rc = generate_opcodes(flash, curopcodes_done); + rc = generate_opcodes(curopcodes_done); } else { printf_debug("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; @@ -747,14 +758,6 @@ uint8_t *data; int count; - /* program opcodes if not already done */ - if (curopcodes == NULL) { - printf_debug("Programming OPCODES... "); - curopcodes = &O_ST_M25P; - program_opcodes(curopcodes); - printf_debug("done\n"); - } - /* find cmd in opcodes-table */ for (a = 0; a < 8; a++) { if ((curopcodes->opcode[a]).opcode == cmd) {

1 0

r3813 build service
by coreboot information 14 Dec '08

14 Dec '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3813 to the coreboot source repository and caused the following changes: Change Log: oops. there went a new mainboard into the tree and i missed it. Add mainboard specific changes based on the DBM690T code. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:pistachio has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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