coreboot November 2008

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490 discussions

r3723 build service
by coreboot information 03 Nov '08

03 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "hailfinger" checked in revision 3723 to the coreboot source repository and caused the following changes: Change Log: Dump ICH8/ICH9/ICH10 SPI registers in flashrom. This helps a lot if we have to track down configuration weirdnesses. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of bcom:winnetp680 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3723&device=winnetp680&ven… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] flashrom: Dump ICH9 SPI registers
by Carl-Daniel Hailfinger 03 Nov '08

03 Nov '08

Dump ICH9 SPI registers in flashrom. This helps a lot if we have to track down configuration weirdnesses. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich9/chipset_enable.c =================================================================== --- flashrom-ich9/chipset_enable.c (Revision 3698) +++ flashrom-ich9/chipset_enable.c (Arbeitskopie) @@ -232,9 +232,11 @@ { int ret, i; uint8_t old, new, bbs, buc; - uint16_t spibar_offset; + uint16_t spibar_offset, tmp2; uint32_t tmp, gcs; void *rcrb; + //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line + //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" }; static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" }; /* Enable Flash Writes */ @@ -334,10 +336,48 @@ } break; case BUS_TYPE_ICH9_SPI: - /* TODO: Add dumping function for ICH8/ICH9, or drop the - * whole SPIBAR dumping from chipset_enable.c - There's - * inteltool for this task already. - */ + tmp2 = *(uint16_t *) (spibar + 0); + printf_debug("0x00: 0x%04x (HSFS)\n", tmp2); + printf_debug("FLOCKDN %i, ", (tmp >> 15 & 1)); + printf_debug("FDV %i, ", (tmp >> 14) & 1); + printf_debug("FDOPSS %i, ", (tmp >> 13) & 1); + printf_debug("SCIP %i, ", (tmp >> 5) & 1); + printf_debug("BERASE %i, ", (tmp >> 3) & 3); + printf_debug("AEL %i, ", (tmp >> 2) & 1); + printf_debug("FCERR %i, ", (tmp >> 1) & 1); + printf_debug("FDONE %i\n", (tmp >> 0) & 1); + + tmp = *(uint32_t *) (spibar + 0x50); + printf_debug("0x50: 0x%08x (FRAP)\n", tmp); + printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff); + printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff); + printf_debug("BRWA %i, ", (tmp >> 8) & 0xff); + printf_debug("BRRA %i\n", (tmp >> 0) & 0xff); + + printf_debug("0x54: 0x%08x (FREG0)\n", + *(uint32_t *) (spibar + 0x54)); + printf_debug("0x58: 0x%08x (FREG1)\n", + *(uint32_t *) (spibar + 0x58)); + printf_debug("0x5C: 0x%08x (FREG2)\n", + *(uint32_t *) (spibar + 0x5C)); + printf_debug("0x60: 0x%08x (FREG3)\n", + *(uint32_t *) (spibar + 0x60)); + printf_debug("0x64: 0x%08x (FREG4)\n", + *(uint32_t *) (spibar + 0x64)); + printf_debug("0x74: 0x%08x (PR0)\n", + *(uint32_t *) (spibar + 0x74)); + printf_debug("0x78: 0x%08x (PR1)\n", + *(uint32_t *) (spibar + 0x78)); + printf_debug("0x7C: 0x%08x (PR2)\n", + *(uint32_t *) (spibar + 0x7C)); + printf_debug("0x80: 0x%08x (PR3)\n", + *(uint32_t *) (spibar + 0x80)); + printf_debug("0x84: 0x%08x (PR4)\n", + *(uint32_t *) (spibar + 0x84)); + /* printf_debug("0xA0: 0x%08x (BBAR)\n", + *(uint32_t *) (spibar + 0xA0)); ICH10 only? */ + printf_debug("0xB0: 0x%08x (FDOC)\n", + *(uint32_t *) (spibar + 0xB0)); break; default: /* Nothing */ -- http://www.hailfinger.org/

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r3723 - trunk/util/flashrom
by svn＠coreboot.org 03 Nov '08

03 Nov '08

Author: hailfinger Date: 2008-11-03 01:20:22 +0100 (Mon, 03 Nov 2008) New Revision: 3723 Modified: trunk/util/flashrom/chipset_enable.c Log: Dump ICH8/ICH9/ICH10 SPI registers in flashrom. This helps a lot if we have to track down configuration weirdnesses. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2008-11-03 00:02:11 UTC (rev 3722) +++ trunk/util/flashrom/chipset_enable.c 2008-11-03 00:20:22 UTC (rev 3723) @@ -232,9 +232,11 @@ { int ret, i; uint8_t old, new, bbs, buc; - uint16_t spibar_offset; + uint16_t spibar_offset, tmp2; uint32_t tmp, gcs; void *rcrb; + //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line + //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" }; static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" }; /* Enable Flash Writes */ @@ -334,10 +336,48 @@ } break; case BUS_TYPE_ICH9_SPI: - /* TODO: Add dumping function for ICH8/ICH9, or drop the - * whole SPIBAR dumping from chipset_enable.c - There's - * inteltool for this task already. - */ + tmp2 = *(uint16_t *) (spibar + 0); + printf_debug("0x00: 0x%04x (HSFS)\n", tmp2); + printf_debug("FLOCKDN %i, ", (tmp >> 15 & 1)); + printf_debug("FDV %i, ", (tmp >> 14) & 1); + printf_debug("FDOPSS %i, ", (tmp >> 13) & 1); + printf_debug("SCIP %i, ", (tmp >> 5) & 1); + printf_debug("BERASE %i, ", (tmp >> 3) & 3); + printf_debug("AEL %i, ", (tmp >> 2) & 1); + printf_debug("FCERR %i, ", (tmp >> 1) & 1); + printf_debug("FDONE %i\n", (tmp >> 0) & 1); + + tmp = *(uint32_t *) (spibar + 0x50); + printf_debug("0x50: 0x%08x (FRAP)\n", tmp); + printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff); + printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff); + printf_debug("BRWA %i, ", (tmp >> 8) & 0xff); + printf_debug("BRRA %i\n", (tmp >> 0) & 0xff); + + printf_debug("0x54: 0x%08x (FREG0)\n", + *(uint32_t *) (spibar + 0x54)); + printf_debug("0x58: 0x%08x (FREG1)\n", + *(uint32_t *) (spibar + 0x58)); + printf_debug("0x5C: 0x%08x (FREG2)\n", + *(uint32_t *) (spibar + 0x5C)); + printf_debug("0x60: 0x%08x (FREG3)\n", + *(uint32_t *) (spibar + 0x60)); + printf_debug("0x64: 0x%08x (FREG4)\n", + *(uint32_t *) (spibar + 0x64)); + printf_debug("0x74: 0x%08x (PR0)\n", + *(uint32_t *) (spibar + 0x74)); + printf_debug("0x78: 0x%08x (PR1)\n", + *(uint32_t *) (spibar + 0x78)); + printf_debug("0x7C: 0x%08x (PR2)\n", + *(uint32_t *) (spibar + 0x7C)); + printf_debug("0x80: 0x%08x (PR3)\n", + *(uint32_t *) (spibar + 0x80)); + printf_debug("0x84: 0x%08x (PR4)\n", + *(uint32_t *) (spibar + 0x84)); + /* printf_debug("0xA0: 0x%08x (BBAR)\n", + *(uint32_t *) (spibar + 0xA0)); ICH10 only? */ + printf_debug("0xB0: 0x%08x (FDOC)\n", + *(uint32_t *) (spibar + 0xB0)); break; default: /* Nothing */

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[PATCH] flashrom: More SPI erase functions
by Carl-Daniel Hailfinger 03 Nov '08

03 Nov '08

As promised to Stefan, here's the flashrom patch I've been talking about. Add additional SPI sector erase and chip erase command functions to flashrom. Not all chips support all commands, so allow the implementer to select the matching function. Fix a layering violation in ICH SPI code to be less bad. Still not perfect, but the new code is shorter, more generic and architecturally more sound. TODO (in a separate patch): - move the generic sector erase code to spi.c - decide which erase command to use based on info about the chip - create a generic spi_erase_all_sectors function which calls the generic sector erase function Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_erase/flash.h =================================================================== --- flashrom-spi_erase/flash.h (Revision 3471) +++ flashrom-spi_erase/flash.h (Arbeitskopie) @@ -417,7 +417,10 @@ int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); void spi_write_enable(); void spi_write_disable(); +int spi_chip_erase_60(struct flashchip *flash); int spi_chip_erase_c7(struct flashchip *flash); +int spi_block_erase_52(const struct flashchip *flash, unsigned long addr); +int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr); int spi_chip_write(struct flashchip *flash, uint8_t *buf); int spi_chip_read(struct flashchip *flash, uint8_t *buf); uint8_t spi_read_status_register(); Index: flashrom-spi_erase/spi.c =================================================================== --- flashrom-spi_erase/spi.c (Revision 3471) +++ flashrom-spi_erase/spi.c (Arbeitskopie) @@ -266,6 +266,22 @@ } } +int spi_chip_erase_60(struct flashchip *flash) +{ + const unsigned char cmd[JEDEC_CE_60_OUTSIZE] = {JEDEC_CE_60}; + + spi_disable_blockprotect(); + spi_write_enable(); + /* Send CE (Chip Erase) */ + spi_command(sizeof(cmd), 0, cmd, NULL); + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 1-85 s, so wait in 1 s steps. + */ + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + sleep(1); + return 0; +} + int spi_chip_erase_c7(struct flashchip *flash) { const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = {JEDEC_CE_C7}; @@ -282,6 +298,24 @@ return 0; } +int spi_block_erase_52(const struct flashchip *flash, unsigned long addr) +{ + unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52}; + + cmd[1] = (addr & 0x00ff0000) >> 16; + cmd[2] = (addr & 0x0000ff00) >> 8; + cmd[3] = (addr & 0x000000ff); + spi_write_enable(); + /* Send BE (Block Erase) */ + spi_command(sizeof(cmd), 0, cmd, NULL); + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + usleep(100 * 1000); + return 0; +} + /* Block size is usually * 64k for Macronix * 32k for SST Index: flashrom-spi_erase/ichspi.c =================================================================== --- flashrom-spi_erase/ichspi.c (Revision 3471) +++ flashrom-spi_erase/ichspi.c (Arbeitskopie) @@ -452,17 +452,8 @@ static int ich_spi_erase_block(struct flashchip *flash, int offset) { - printf_debug("ich_spi_erase_block: offset=%d, sectors=%d\n", - offset, 1); - - if (run_opcode(2, curopcodes->opcode[2], offset, 0, NULL) != 0) { - printf_debug("Error erasing sector at 0x%x", offset); - return -1; - } - - printf("DONE BLOCK 0x%x\n", offset); - - return 0; + /* FIMXE: call the chip-specific spi_block_erase_XX instead. */ + return spi_block_erase_d8(flash, offset); } static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset, int maxdata) -- http://www.hailfinger.org/

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r3722 - trunk/util/flashrom
by svn＠coreboot.org 03 Nov '08

03 Nov '08

Author: hailfinger Date: 2008-11-03 01:02:11 +0100 (Mon, 03 Nov 2008) New Revision: 3722 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/ichspi.c trunk/util/flashrom/spi.c Log: Add additional SPI sector erase and chip erase command functions to flashrom. Not all chips support all commands, so allow the implementer to select the matching function. Fix a layering violation in ICH SPI code to be less bad. Still not perfect, but the new code is shorter, more generic and architecturally more sound. TODO (in a separate patch): - move the generic sector erase code to spi.c - decide which erase command to use based on info about the chip - create a generic spi_erase_all_sectors function which calls the generic sector erase function Thanks to Stefan for reviewing and commenting. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-11-02 19:51:50 UTC (rev 3721) +++ trunk/util/flashrom/flash.h 2008-11-03 00:02:11 UTC (rev 3722) @@ -424,8 +424,11 @@ const unsigned char *writearr, unsigned char *readarr); void spi_write_enable(); void spi_write_disable(); +int spi_chip_erase_60(struct flashchip *flash); int spi_chip_erase_c7(struct flashchip *flash); int spi_chip_erase_d8(struct flashchip *flash); +int spi_block_erase_52(const struct flashchip *flash, unsigned long addr); +int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr); int spi_chip_write(struct flashchip *flash, uint8_t *buf); int spi_chip_read(struct flashchip *flash, uint8_t *buf); uint8_t spi_read_status_register(); Modified: trunk/util/flashrom/ichspi.c =================================================================== --- trunk/util/flashrom/ichspi.c 2008-11-02 19:51:50 UTC (rev 3721) +++ trunk/util/flashrom/ichspi.c 2008-11-03 00:02:11 UTC (rev 3722) @@ -154,7 +154,6 @@ int offset, int maxdata); static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, int offset, int maxdata); -static int ich_spi_erase_block(struct flashchip *flash, int offset); OPCODES O_ST_M25P = { { @@ -479,20 +478,6 @@ return -1; } -static int ich_spi_erase_block(struct flashchip *flash, int offset) -{ - printf_debug("ich_spi_erase_block: offset=%d, sectors=%d\n", offset, 1); - - if (run_opcode(curopcodes->opcode[2], offset, 0, NULL) != 0) { - printf_debug("Error erasing sector at 0x%x", offset); - return -1; - } - - printf("DONE BLOCK 0x%x\n", offset); - - return 0; -} - static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset, int maxdata) { @@ -596,7 +581,11 @@ printf("Programming page: \n"); for (i = 0; i < total_size / erase_size; i++) { - rc = ich_spi_erase_block(flash, i * erase_size); + /* FIMXE: call the chip-specific spi_block_erase_XX instead. + * For this, we need to add a block erase function to + * struct flashchip. + */ + rc = spi_block_erase_d8(flash, i * erase_size); if (rc) { printf("Error erasing block at 0x%x\n", i); break; Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2008-11-02 19:51:50 UTC (rev 3721) +++ trunk/util/flashrom/spi.c 2008-11-03 00:02:11 UTC (rev 3722) @@ -271,6 +271,22 @@ } } +int spi_chip_erase_60(struct flashchip *flash) +{ + const unsigned char cmd[JEDEC_CE_60_OUTSIZE] = {JEDEC_CE_60}; + + spi_disable_blockprotect(); + spi_write_enable(); + /* Send CE (Chip Erase) */ + spi_command(sizeof(cmd), 0, cmd, NULL); + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 1-85 s, so wait in 1 s steps. + */ + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + sleep(1); + return 0; +} + int spi_chip_erase_c7(struct flashchip *flash) { const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = { JEDEC_CE_C7 }; @@ -287,6 +303,24 @@ return 0; } +int spi_block_erase_52(const struct flashchip *flash, unsigned long addr) +{ + unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52}; + + cmd[1] = (addr & 0x00ff0000) >> 16; + cmd[2] = (addr & 0x0000ff00) >> 8; + cmd[3] = (addr & 0x000000ff); + spi_write_enable(); + /* Send BE (Block Erase) */ + spi_command(sizeof(cmd), 0, cmd, NULL); + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + usleep(100 * 1000); + return 0; +} + /* Block size is usually * 64k for Macronix * 32k for SST

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Thoughts for call for help in Ubuntu forum
by Paul Menzel 03 Nov '08

03 Nov '08

Dear list, lately some message came to the list in reaction to the post You can help out Coreboot! in the Ubuntu forums [1]. I do not know if one of you posted this, but I am wondering if maybe also the flashrom information would be useful? Also in February Carl-Daniel posted a script for this purpose, which was never acked or commited to the repository [2][3]. If information is still needed maybe the script can be checked in, the proposed e-mail-addresses be setup and a page in the Wiki be created. Maybe it is also beneficial to suggest a common subject, so that the messages can be searched better. Thanks, Paul [1] http://ubuntuforums.org/showthread.php?t=961975 [2] http://www.coreboot.org/pipermail/coreboot/2008-February/031507.html [3] http://www.coreboot.org/pipermail/coreboot/2008-March/031658.html

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coreboot.v2+seabios on 440bx: option roms not found
by Andriy Gapon 03 Nov '08

03 Nov '08

In northbridge/intel/i440bx/raminit.c:sdram_set_spd_registers all PAM registers are programmed for RAM R/W access (0x33). When SeaBIOS searches for option ROMs (including VGA ROM) it doesn't do anything about PAM, so it sees empty memory instead of the ROMs. I am not sure what is the best solution here. It is debatable how coreboot should set PAM register, and it is not right to make SeaBIOS too hardware dependent. Maybe coreboot could somehow export functions for setting access to option ROM space (aka legacy memory segments) and SeaBIOS could call them. -- Andriy Gapon

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Re: [coreboot] r975 - in coreboot-v3: arch/x86 mainboard/via mainboard/via/epia-cn
by Stefan Reinauer 03 Nov '08

03 Nov '08

svn(a)coreboot.org schrieb: > Author: rminnich > Date: 2008-10-31 23:43:02 +0100 (Fri, 31 Oct 2008) > New Revision: 975 > > Modified: > coreboot-v3/arch/x86/Makefile > coreboot-v3/mainboard/via/Kconfig > coreboot-v3/mainboard/via/epia-cn/cmos.layout > Log: > no PIRQ table > Make cmos.layout work with incomprehensible tool -- just turn off checksums. Which tool are you referring to?

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Fwd: Flashrom problem
by Collin Gregory 02 Nov '08

02 Nov '08

The problem is still unsolved, does ainyone have got an idear ? Could it be a kernel configuration problem ? ---------- Forwarded message ---------- From: Collin Gregory <collin.gregory(a)gmail.com> Date: 2008/10/31 Subject: Re: [coreboot] Flashrom problem To: Myles Watson <mylesgw(a)gmail.com> Hello Myles, Thanks for your quick answer. Here is my command line that i typed : ./flashrom -r test Here is what ./flashrom -r test -V gives : Calibrating Delay loop... 797M loops per second, 100 myus = 201 us, OK. Can't mmap memory using /dev/mem : Invalid Argument. That's for it. The version of flashrom is the r3708. 2008/10/31 Myles Watson <mylesgw(a)gmail.com> From the comment in flashrom.c, it looks like flashrom is trying to > allocate memory smaller than a page, and failing. It would be helpful if > you posted your command line and the complete output. Probably the output > of ./flashrom –V too. > > > > Thanks, > > Myles > > > ------------------------------ > > *From:* coreboot-bounces(a)coreboot.org [mailto: > coreboot-bounces(a)coreboot.org] *On Behalf Of *Collin Gregory > *Sent:* Friday, October 31, 2008 2:17 PM > *To:* coreboot(a)coreboot.org > *Subject:* [coreboot] Flashrom problem > > > > Hello everyone, > > I'm a newbies in coreboot installation but not in linux, hopefully :) > When i'm launching flashrom, i get this error message : > > Can't mmap memory using /dev/mem : Invalid ARgument ... > > Does anyone knows what does it means ? > > My motherboard is the D945gclf with these technical informations : > > - Soldered-down Intel(R) Atom(R) processor 230 with a 533 MHz system bus > - Intel(R) 945GC Chipset, consisting of: > > • Intel(R) 82945GC Graphics Memory Controller Hub (GMCH) > > • Intel(R) 82801GB I/O Controller Hub (ICH7) > > - Realtek* ALC662 for the sound chipset > - Intel(R) GMA950 onboard graphics subsystem Video > - SMSC LPC47M997 based Legacy I/O controller for hardware management, > serial, parallel, and PS/2* ports > - Realtek RTL8102EL LAN adapter device > > Thanks for your help !!!! > > Greg >

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[PATCH] v2: Trim i82801xx driver to only a sensible subset
by Uwe Hermann 02 Nov '08

02 Nov '08

See patch. ICH0-ICH6 make sense for this driver, ICH7 and higher will be in a different driver/directory. AFAIK Stefan has been (or still is) working on a (yet to be released) ICH7 driver which is totally different from the other i82801xx stuff so it makes perfect sense to put it in a different driver/directory. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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coreboot November 2008