coreboot November 2008

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r3718 - trunk/coreboot-v2/src/southbridge/intel/i82801xx
by svn＠coreboot.org 02 Nov '08

02 Nov '08

Author: uwe Date: 2008-11-02 15:33:51 +0100 (Sun, 02 Nov 2008) New Revision: 3718 Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_ac97.c trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_nic.c trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_smbus.c trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_usb.c Log: Trim down the list of southbridges supported by the i82801xx driver to only a set of reasonably similar ones, namely (for now) ICH0* - ICH6*, and C-ICH. All later ICH* southbridges (ICH7-ICH10) are _very_ different and were surely not working with this driver anyway (and there's no chance to support them reasonably with this driver without ending up in #ifdef hell). ICH7 now has an extra driver in svn, whether ICH8-ICH10 are similar enough to be supported by that ICH7 driver remains to be seen. This patch was informally acked by Stefan Reinauer <stepan(a)coresystems.de> on IRC. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_ac97.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_ac97.c 2008-11-02 14:25:11 UTC (rev 3717) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_ac97.c 2008-11-02 14:33:51 UTC (rev 3718) @@ -126,19 +126,3 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801FB_AC97_MODEM, }; - -/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ -/* Note: 82801GU (ICH7-U) doesn't have AC97 audio/modem. */ -static const struct pci_driver i82801gb_ac97_audio __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801GB_AC97_AUDIO, -}; - -static const struct pci_driver i82801gb_ac97_modem __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801GB_AC97_MODEM, -}; - -/* Note: There's no AC97 audio/modem on ICH8/ICH9/C-ICH. */ Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_nic.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_nic.c 2008-11-02 14:25:11 UTC (rev 3717) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_nic.c 2008-11-02 14:33:51 UTC (rev 3718) @@ -63,28 +63,6 @@ .device = PCI_DEVICE_ID_INTEL_82801FB_LAN, }; -/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ -/* Note: 82801GU (ICH7-U) doesn't have a NIC. */ -static const struct pci_driver i82801gb_nic __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801GB_LAN, -}; - -/* 82801HB/HR/HDH/HDO/HBM/HEM (ICH8/ICH8R/ICH8DH/ICH8DO/ICH8M/ICH8M-E) */ -static const struct pci_driver i82801hb_nic __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801HB_LAN, -}; - -/* 82801IB/IR/IH/IO (ICH9/ICH9R/ICH9DH/ICH9DO) */ -static const struct pci_driver i82801ib_nic __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801IB_LAN, -}; - /* 82801E (C-ICH) */ static const struct pci_driver i82801e_nic1 __pci_driver = { .ops = &nic_ops, Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_smbus.c 2008-11-02 14:25:11 UTC (rev 3717) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_smbus.c 2008-11-02 14:33:51 UTC (rev 3718) @@ -101,27 +101,6 @@ .device = PCI_DEVICE_ID_INTEL_82801FB_SMB, }; -/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */ -static const struct pci_driver i82801gb_smb __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801GB_SMB, -}; - -/* 82801HB/HR/HDH/HDO/HBM/HEM (ICH8/ICH8R/ICH8DH/ICH8DO/ICH8M/ICH8M-E) */ -static const struct pci_driver i82801hb_smb __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801HB_LAN, -}; - -/* 82801IB/IR/IH/IO (ICH9/ICH9R/ICH9DH/ICH9DO) */ -static const struct pci_driver i82801ib_smb __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801IB_SMB, -}; - /* 82801E (C-ICH) */ static const struct pci_driver i82801e_smb __pci_driver = { .ops = &smbus_ops, Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_usb.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_usb.c 2008-11-02 14:25:11 UTC (rev 3717) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_usb.c 2008-11-02 14:33:51 UTC (rev 3718) @@ -155,99 +155,6 @@ .device = PCI_DEVICE_ID_INTEL_82801FB_USB4, }; -/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */ -static const struct pci_driver i82801gb_usb1 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801GB_USB1, -}; - -static const struct pci_driver i82801gb_usb2 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801GB_USB2, -}; - -static const struct pci_driver i82801gb_usb3 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801GB_USB3, -}; - -static const struct pci_driver i82801gb_usb4 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801GB_USB4, -}; - -/* 82801HB/HR/HDH/HDO/HBM/HEM (ICH8/ICH8R/ICH8DH/ICH8DO/ICH8M/ICH8M-E) */ -static const struct pci_driver i82801hb_usb1 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801HB_USB1, -}; - -static const struct pci_driver i82801hb_usb2 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801HB_USB2, -}; - -static const struct pci_driver i82801hb_usb3 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801HB_USB3, -}; - -static const struct pci_driver i82801hb_usb4 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801HB_USB4, -}; - -static const struct pci_driver i82801hb_usb5 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801HB_USB5, -}; - -/* 82801IB/IR/IH/IO (ICH9/ICH9R/ICH9DH/ICH9DO) */ -static const struct pci_driver i82801ib_usb1 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801IB_USB1, -}; - -static const struct pci_driver i82801ib_usb2 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801IB_USB2, -}; - -static const struct pci_driver i82801ib_usb3 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801IB_USB3, -}; - -static const struct pci_driver i82801ib_usb4 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801IB_USB4, -}; - -static const struct pci_driver i82801ib_usb5 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801IB_USB5, -}; - -static const struct pci_driver i82801ib_usb6 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801IB_USB6, -}; - /* 82801E (C-ICH) */ static const struct pci_driver i82801e_usb __pci_driver = { .ops = &usb_ops,

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assistance with updating my bios
by Elia Yehuda 02 Nov '08

02 Nov '08

Hi all, I'm trying to play with coreboot to flash my bios on my PC, with no success. here are the computer hardware information followed by the commands I'm trying to execute. <INFO BEGIN> cpu: Socket370 Intel Pentium III Celeron northbridge: Intel 82810E southbridge: Intel 8281AA mainboard: 810 R 4.1 with lan super i/o: Winbond W8362F-AW bios device: ST M50FW002 lspci ooutput: 00:00.0 Host bridge: Intel Corporation 82810E DC-133 (GMCH) Graphics Memory Controller Hub (rev 03) 00:01.0 VGA compatible controller: Intel Corporation 82810E DC-133 (CGC) Chipset Graphics Controller (rev 03) 00:1e.0 PCI bridge: Intel Corporation 82801AA PCI Bridge (rev 02) 00:1f.0 ISA bridge: Intel Corporation 82801AA ISA Bridge (LPC) (rev 02) 00:1f.1 IDE interface: Intel Corporation 82801AA IDE Controller (rev 02) 00:1f.2 USB Controller: Intel Corporation 82801AA USB Controller (rev 02) 00:1f.3 SMBus: Intel Corporation 82801AA SMBus Controller (rev 02) 00:1f.5 Multimedia audio controller: Intel Corporation 82801AA AC'97 Audio Controller (rev 02) 01:05.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) <INFO END> $ flashrom -f -r -c M50FW016 mydump Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH", enabling flash write... OK. No EEPROM/flash device found. Force read (-f -r -c) requested, forcing chip probe success: Found chip "ST M50FW016" (2048 KB) at physical address 0xffe00000. Force reading flash...done $ flashrom -f -w -c M50FW016 mydump Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH", enabling flash write... OK. No EEPROM/flash device found. I'd appreciate any assistance as all this flashing stuff is new to me. Basically what i'm trying to accomplish is having my linux system running as the payload, but i'm stuck with even re-writing the same bios-dump i've just read from the bios... I'll post any further information required to diagnose this further. thanks in advance, Elia Yehuda.

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r3717 - trunk/util/flashrom
by svn＠coreboot.org 02 Nov '08

02 Nov '08

Author: hailfinger Date: 2008-11-02 15:25:11 +0100 (Sun, 02 Nov 2008) New Revision: 3717 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c Log: Add support for the ST M50FW002 chip to flashrom. Identification only, erase/write are not implemented. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> tested and Acked-by: Elia Yehuda <z4ziggy(a)gmail.com> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-11-02 11:11:40 UTC (rev 3716) +++ trunk/util/flashrom/flash.h 2008-11-02 14:25:11 UTC (rev 3717) @@ -317,6 +317,7 @@ #define ST_M50FLW040B 0x28 #define ST_M50FLW080A 0x80 #define ST_M50FLW080B 0x81 +#define ST_M50FW002 0x29 #define ST_M50FW040 0x2C #define ST_M50FW080 0x2D #define ST_M50FW016 0x2E Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-11-02 11:11:40 UTC (rev 3716) +++ trunk/util/flashrom/flashchips.c 2008-11-02 14:25:11 UTC (rev 3717) @@ -121,6 +121,7 @@ {"ST", "M50FLW040B", ST_ID, ST_M50FLW040B, 512, 64 * 1024, TEST_UNTESTED, probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x}, {"ST", "M50FLW080A", ST_ID, ST_M50FLW080A, 1024, 64 * 1024, TEST_OK_PREW, probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x}, {"ST", "M50FLW080B", ST_ID, ST_M50FLW080B, 1024, 64 * 1024, TEST_UNTESTED, probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x}, + {"ST", "M50FW002", ST_ID, ST_M50FW002, 256, 64 * 1024, TEST_UNTESTED, probe_49lfxxxc, NULL, NULL}, {"ST", "M50FW016", ST_ID, ST_M50FW016, 2048, 64 * 1024, TEST_UNTESTED, probe_82802ab, erase_82802ab, write_82802ab}, {"ST", "M50FW040", ST_ID, ST_M50FW040, 512, 64 * 1024, TEST_OK_PREW, probe_82802ab, erase_82802ab, write_82802ab}, {"ST", "M50FW080", ST_ID, ST_M50FW080, 1024, 64 * 1024, TEST_UNTESTED, probe_82802ab, erase_82802ab, write_82802ab},

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r3716 - trunk/util/inteltool
by svn＠coreboot.org 02 Nov '08

02 Nov '08

Author: stepan Date: 2008-11-02 12:11:40 +0100 (Sun, 02 Nov 2008) New Revision: 3716 Modified: trunk/util/inteltool/inteltool.c trunk/util/inteltool/inteltool.h trunk/util/inteltool/memory.c trunk/util/inteltool/pcie.c Log: inteltool 82945G/GZ/P/PL Support (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/inteltool/inteltool.c =================================================================== --- trunk/util/inteltool/inteltool.c 2008-10-31 18:41:09 UTC (rev 3715) +++ trunk/util/inteltool/inteltool.c 2008-11-02 11:11:40 UTC (rev 3716) @@ -31,6 +31,7 @@ char *name; } supported_chips_list[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" }, Modified: trunk/util/inteltool/inteltool.h =================================================================== --- trunk/util/inteltool/inteltool.h 2008-10-31 18:41:09 UTC (rev 3715) +++ trunk/util/inteltool/inteltool.h 2008-11-02 11:11:40 UTC (rev 3716) @@ -35,6 +35,7 @@ #define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd #define PCI_DEVICE_ID_INTEL_82845 0x1a30 +#define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) Modified: trunk/util/inteltool/memory.c =================================================================== --- trunk/util/inteltool/memory.c 2008-10-31 18:41:09 UTC (rev 3715) +++ trunk/util/inteltool/memory.c 2008-11-02 11:11:40 UTC (rev 3716) @@ -37,6 +37,7 @@ switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: + case PCI_DEVICE_ID_INTEL_82945P: mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; break; case 0x1234: // Dummy for non-existent functionality Modified: trunk/util/inteltool/pcie.c =================================================================== --- trunk/util/inteltool/pcie.c 2008-10-31 18:41:09 UTC (rev 3715) +++ trunk/util/inteltool/pcie.c 2008-11-02 11:11:40 UTC (rev 3716) @@ -36,6 +36,7 @@ switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: + case PCI_DEVICE_ID_INTEL_82945P: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; break; case 0x1234: // Dummy for non-existent functionality @@ -77,6 +78,7 @@ switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: + case PCI_DEVICE_ID_INTEL_82945P: dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; case 0x1234: // Dummy for non-existent functionality @@ -120,6 +122,7 @@ switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: + case PCI_DEVICE_ID_INTEL_82945P: pciexbar_reg = pci_read_long(nb, 0x48); break; case 0x1234: // Dummy for non-existent functionality

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Re: [coreboot] assistance with updating my bios
by z4ziggy＠gmail.com 02 Nov '08

02 Nov '08

sorry for the delay. the patch works - flashrom informs "Found chip 'ST M50FW002' (256KB) at physical address 0xfffc0000" whats next? :) On Nov 2, 2008 1:20am, Carl-Daniel Hailfinger <cd.hailfinger.devel.2006(a)gmx.net> wrote: > Hi Elia, > > > > On 30.10.2008 11:45, Elia Yehuda wrote: > > > I'm trying to play with coreboot to flash my bios on my PC, with no success. > > > here are the computer hardware information followed by the commands I'm > > > trying to execute. > > > > > > cpu: Socket370 Intel Pentium III Celeron > > > northbridge: Intel 82810E > > > southbridge: Intel 8281AA > > > bios device: ST M50FW002 > > > > > > > Can you try the following flashrom patch? It should find the chip and > > allow you to read it. Erase and write will NOT work and may crash. > > > > Attached if gmail mangles the inline patch. > > > > Add support for the ST M50FW002 chip to flashrom. Identification only, > > erase/write are not implemented. > > > > Signed-off-by: Carl-Daniel Hailfinger > > > > Index: flashrom-M50FW002/flash.h > > =================================================================== > > --- flashrom-M50FW002/flash.h (Revision 3715) > > +++ flashrom-M50FW002/flash.h (Arbeitskopie) > > @@ -317,6 +317,7 @@ > > #define ST_M50FLW040B 0x28 > > #define ST_M50FLW080A 0x80 > > #define ST_M50FLW080B 0x81 > > +#define ST_M50FW002 0x29 > > #define ST_M50FW040 0x2C > > #define ST_M50FW080 0x2D > > #define ST_M50FW016 0x2E > > Index: flashrom-M50FW002/flashchips.c > > =================================================================== > > --- flashrom-M50FW002/flashchips.c (Revision 3715) > > +++ flashrom-M50FW002/flashchips.c (Arbeitskopie) > > @@ -121,6 +121,7 @@ > > {"ST", "M50FLW040B", ST_ID, ST_M50FLW040B, 512, 64 * 1024, TEST_UNTESTED, probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x}, > > {"ST", "M50FLW080A", ST_ID, ST_M50FLW080A, 1024, 64 * 1024, TEST_OK_PREW, probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x}, > > {"ST", "M50FLW080B", ST_ID, ST_M50FLW080B, 1024, 64 * 1024, TEST_UNTESTED, probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x}, > > + {"ST", "M50FW002", ST_ID, ST_M50FW002, 256, 64 * 1024, TEST_UNTESTED, probe_49lfxxxc, NULL, NULL}, > > {"ST", "M50FW016", ST_ID, ST_M50FW016, 2048, 64 * 1024, TEST_UNTESTED, probe_82802ab, erase_82802ab, write_82802ab}, > > {"ST", "M50FW040", ST_ID, ST_M50FW040, 512, 64 * 1024, TEST_OK_PREW, probe_82802ab, erase_82802ab, write_82802ab}, > > {"ST", "M50FW080", ST_ID, ST_M50FW080, 1024, 64 * 1024, TEST_UNTESTED, probe_82802ab, erase_82802ab, write_82802ab}, > > > > > > -- > > http://www.hailfinger.org/ > > >

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Coreboot Tech Talk @ Google, October 30 2008
by David Hendricks 01 Nov '08

01 Nov '08

Hey everyone, Just thought I'd post a link to the tech talk Stefan, Peter and Ron gave at Google a couple days ago: http://www.youtube.com/watch?v=X72LgcMpM9k . The format goes: 1) Ron Minnich, project founder: What is Coreboot, motivation, and principles of operation. 2) Peter Stuge, long-time contributor: Details, system management mode (SMM) and ACPI, and of course some of the coolest demos of all time. 3) Stefan Reinauer, primary maintainer: Testing infrastructure Enjoy!

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Re: [coreboot] assistance with updating my bios
by z4ziggy＠gmail.com 01 Nov '08

01 Nov '08

Since i have no idea what are you two talking about, im attaching the link to the current BIOS datasheet (which shows the current BIOS has a 2MB flash size, if i understand this correctly) : http://www.datasheetcatalog.org/datasheet/stmicroelectronics/8499.pdf On Nov 1, 2008 1:53am, Corey Osgood <corey.osgood(a)gmail.com> wrote: > > cpu: Socket370 Intel Pentium III Celeron > > > northbridge: Intel 82810E > > > southbridge: Intel 8281AA > > > mainboard: 810 R 4.1 with lan > > > super i/o: Winbond W8362F-AW > > > bios device: ST M50FW002 > > > > Are you sure it's SPI? > > > > -Corey > > > > On 10/31/08, Elia Yehuda wrote: > > > many thanks. i will try the patch tomorrow night when i'm back at home and > > > report back. > > > > > > On Fri, Oct 31, 2008 at 8:38 PM, Peter Stuge wrote: > > > > > >> Hi, > > >> > > >> z4ziggy(a)gmail.com wrote: > > >> > No EEPROM/flash device found. > > >> > If you know which flash chip you have, and if this version of flashrom > > >> > supports a similar flash chip, you can try to force read your chip. Run: > > >> > flashrom -f -r -c similar_supported_flash_chip filename > > >> > > > >> > Note: flashrom can never write when the flash chip isn't found > > >> > automatically. > > >> > > >> The above note is sadly not a joke. > > >> > > >> > > >> Corey Osgood wrote: > > >> > AFAIK, flashrom is broken for most ICHx. > > >> > > >> Not so, it works very well on a whole bunch of them. > > >> > > >> > > >> Carl-Daniel Hailfinger wrote: > > >> > On 30.10.2008 16:57, z4ziggy(a)gmail.com wrote: > > >> > > any plans on fixing the issue or using alternative? is there a > > >> > > way i can assist? > > >> > > > >> > Your flash chip is not supported. I'll add code for it. > > >> > > >> Some info Carl-Daniel didn't post, maybe it is informative; > > >> > > >> It seems that the system has a Winbond W25B40 or W25B40A flash chip. > > >> This is an SPI flash chip, but it seems to behave just like a FWH > > >> type chip. > > >> > > >> While waiting for Carl-Daniel you can try the attached patch. I doubt > > >> it will work but you never know. > > >> > > >> > > >> //Peter > > >> > > >> -- > > >> coreboot mailing list: coreboot(a)coreboot.org > > >> http://www.coreboot.org/mailman/listinfo/coreboot > > >> > > > >

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r977 - coreboot-v3/mainboard/jetway
by svn＠coreboot.org 01 Nov '08

01 Nov '08

Author: cozzie Date: 2008-11-01 05:33:36 +0100 (Sat, 01 Nov 2008) New Revision: 977 Modified: coreboot-v3/mainboard/jetway/Kconfig Log: Minor patch to fix a Kconfig warning (trivial) Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: coreboot-v3/mainboard/jetway/Kconfig =================================================================== --- coreboot-v3/mainboard/jetway/Kconfig 2008-11-01 00:53:01 UTC (rev 976) +++ coreboot-v3/mainboard/jetway/Kconfig 2008-11-01 04:33:36 UTC (rev 977) @@ -66,8 +66,8 @@ bool "256 MB" help Choose this option to use 256MB of system memory for onboard video. +endchoice - config CN700_VIDEO_MB int default 0 if CN700_VIDEO_MB_NONE @@ -78,7 +78,6 @@ help Map the config names to an integer. -endchoice config MAINBOARD_DIR string

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via epia-cn and v3
by ron minnich 01 Nov '08

01 Nov '08

coreboot-3.0.974 Fri Oct 31 15:11:04 PDT 2008 starting... (console_loglevel=8) Choosing fallback boot. LAR: Attempting to open 'fallback/initram/segment0'. LAR: Start 0xfffc0000 len 0x40000 LAR: seen member normal/option_table@0xfffc0000, size 1008 LAR: seen member normal/initram/segment0@0xfffc0440, size 8876 LAR: seen member normal/stage2/segment0@0xfffc2740, size 1 LAR: seen member normal/stage2/segment1@0xfffc27a0, size 17676 LAR: seen member normal/stage2/segment2@0xfffc6d00, size 579 LAR: seen member bootblock@0xffffafc0, size 20480 LAR: File not found! LAR: Run file fallback/initram/segment0 failed: No such file. Fallback failed. Try normal boot LAR: Attempting to open 'normal/initram/segment0'. LAR: Start 0xfffc0000 len 0x40000 LAR: seen member normal/option_table@0xfffc0000, size 1008 LAR: seen member normal/initram/segment0@0xfffc0440, size 8876 LAR: CHECK normal/initram/segment0 @ 0xfffc0440 start 0xfffc0490 len 8876 reallen 8876 compression 0 entry 0x00001475 loadaddre0 Entry point is 0xfffc1905 In initram.c main() Enabling Via V-Link pci_conf1_find_on_bus: bus 0, find 0x1106:3227 pci_conf1_find_on_bus: bus 1, find 0x1106:3227 pci_conf1_find_on_bus: bus 0, find 0x1106:0571 pci_conf1_find_on_bus: bus 1, find 0x1106:0571 Enabling shadow ram pci_conf1_find_on_bus: bus 0, find 0x1106:3227 pci_conf1_find_on_bus: bus 1, find 0x1106:3227 VT8237R Power management controller found at 0x8800 SMBus Ready/Completed Successfully Configuring DRAM Bank 0 SMBus Read from DIMM 80 at address 0x1f SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x80 SMBus Ready/Completed Successfully Found 512MB module in slot 0 Setting Top of Usable DRAM to 512MB Calculating tWR and tRFC SMBus Read from DIMM 80 at address 0x24 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x3c SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x2a SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x69 SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x28 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x0 SMBus Ready/Completed Successfully Calculating tRAS and CAS SMBus Read from DIMM 80 at address 0x1e SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x27 SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x12 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x38 SMBus Ready/Completed Successfully Calculating tRRD, tRTP, and tWTR SMBus Read from DIMM 80 at address 0x1c SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x1e SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x26 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x1e SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x25 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x1e SMBus Ready/Completed Successfully Calculating tRCD and tRP SMBus Read from DIMM 80 at address 0x1d SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x3c SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x1b SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x3c SMBus Ready/Completed Successfully calculating MA map SMBus Read from DIMM 80 at address 0x5 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x60 SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x4 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0xa SMBus Ready/Completed Successfully Setting Memory Address Map type to 0x1 Configuring DRAM Bank 1 SMBus Read from DIMM 0 at address 0x1f SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready Device error Read: 0x0 SMBus Ready/Completed Successfully No memory in slot 1 RAM Enable 1: Apply NOP Sending RAM command 'No-op' to 0x0 RAM Enable 2: Precharge all Sending RAM command 'Precharge' to 0x0 RAM Enable 3: Mode register set (DLL Reset) Sending RAM command 'MRS' to 0x12000 RAM Enable 4: Precharge all Sending RAM command 'Precharge' to 0x0 RAM Enable 5: CBR Sending RAM command 'CBR' to 0x0 RAM Enable 6: Mode register set (OCD Calibration) Mode Register Set (MRS) value is 0x1001d8 Sending RAM command 'MRS' to 0x1001d8 RAM Enable 7: Normal operation Sending RAM command 'Normal' to 0x0 Sending RAM command 'Normal' to 0x30 run_file returns with 0 Done RAM init code In hardware_stage1() resets at this point and restarts. Very slow, as though it were not caching ROM? ron

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r976 - in coreboot-v3: arch/x86 arch/x86/via mainboard/via/epia-cn
by svn＠coreboot.org 01 Nov '08

01 Nov '08

Author: rminnich Date: 2008-11-01 01:53:01 +0100 (Sat, 01 Nov 2008) New Revision: 976 Modified: coreboot-v3/arch/x86/stage1_mtrr.c coreboot-v3/arch/x86/via/stage1.c coreboot-v3/mainboard/via/epia-cn/Makefile coreboot-v3/mainboard/via/epia-cn/stage1.c Log: Get via to use standard mtrr init functions. Start to document them. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/stage1_mtrr.c =================================================================== --- coreboot-v3/arch/x86/stage1_mtrr.c 2008-10-31 22:43:02 UTC (rev 975) +++ coreboot-v3/arch/x86/stage1_mtrr.c 2008-11-01 00:53:01 UTC (rev 976) @@ -106,6 +106,10 @@ } +/** + * Call this function early in stage1 to enable mtrrs, which will ensure + * caching of ROM + */ void early_mtrr_init(void) { static const unsigned long mtrr_msrs[] = { Modified: coreboot-v3/arch/x86/via/stage1.c =================================================================== --- coreboot-v3/arch/x86/via/stage1.c 2008-10-31 22:43:02 UTC (rev 975) +++ coreboot-v3/arch/x86/via/stage1.c 2008-11-01 00:53:01 UTC (rev 976) @@ -30,22 +30,7 @@ #include <mtrr.h> #include <via_c7.h> -#ifdef NO_IDEA_WHETHER_THIS_IS_RELEVANT_ON_C7 /** - * Set the MTRR for initial ram access. - * be warned, this will be used by core other than core 0/node 0 or core0/node0 when cpu_reset. - * This warning has some significance I don't yet understand. - */ -void set_init_ram_access(void) -{ - set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, MTRR_TYPE_WRBACK); -} -#endif - -#define __stringify_1(x) #x -#define __stringify(x) __stringify_1(x) - -/** * Disable Cache As RAM (CAR) after memory is setup. */ void disable_car(void) Modified: coreboot-v3/mainboard/via/epia-cn/Makefile =================================================================== --- coreboot-v3/mainboard/via/epia-cn/Makefile 2008-10-31 22:43:02 UTC (rev 975) +++ coreboot-v3/mainboard/via/epia-cn/Makefile 2008-11-01 00:53:01 UTC (rev 976) @@ -18,7 +18,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c +STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \ + $(src)/arch/x86/stage1_mtrr.c \ + $(src)/mainboard/$(MAINBOARDDIR)/stage1.c INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/via/cn700/initram.c \ Modified: coreboot-v3/mainboard/via/epia-cn/stage1.c =================================================================== --- coreboot-v3/mainboard/via/epia-cn/stage1.c 2008-10-31 22:43:02 UTC (rev 975) +++ coreboot-v3/mainboard/via/epia-cn/stage1.c 2008-11-01 00:53:01 UTC (rev 976) @@ -36,10 +36,15 @@ void hardware_stage1(void) { + void early_mtrr_init(void); void vt1211_enable_serial(u8 dev, u8 serial, u16 iobase); u32 dev; post_code(POST_START_OF_MAIN); + + /* do this or watch the system run slowly */ + early_mtrr_init(); + vt1211_enable_serial(0x2e, 2, 0x3f8); /* Enable multifunction for northbridge. */

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coreboot November 2008