coreboot November 2008

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r3726 - trunk/coreboot-v2/src/cpu/amd/model_fxx
by svn＠coreboot.org 03 Nov '08

03 Nov '08

Author: mjones Date: 2008-11-03 22:39:03 +0100 (Mon, 03 Nov 2008) New Revision: 3726 Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/fidvid.c Log: Update K8 FID/VID setup. Add support for 100MHz FIDs (revG). Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/fidvid.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/fidvid.c 2008-11-03 16:55:22 UTC (rev 3725) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/fidvid.c 2008-11-03 21:39:03 UTC (rev 3726) @@ -97,36 +97,43 @@ } #endif -static unsigned set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) +static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) { - /* for (cur, new) there is one <1600MHz x8 to find out next_fid */ - static const uint8_t next_fid_a[] = { - /* x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 */ -/* x4 */ 0, 9, 9, 8, 9, 9, 9, 9, 9, 9, 9, 9, -/* x5 */ 9, 0, 11, 11, 9, 9, 10, 11, 11, 11, 11, 11, -/* x6 */ 11, 11, 0, 13, 11, 11, 11, 11, 12, 13, 13, 13, -/* x7 */ 13, 13, 13, 0, 13, 13, 13, 13, 13, 13, 14, 15, -/* x8 */ 4, 9, 9, 9, 0, 9, 9, 9, 9, 9, 9, 9, -/* x9 */ 4, 5, 10, 10, 8, 0, 0, 0, 0, 0, 0, 0, -/*x10 */ 9, 5, 11, 11, 9, 0, 0, 0, 0, 0, 0, 0, -/*x11 */ 10, 5, 6, 12, 10, 0, 0, 0, 0, 0, 0, 0, -/*x12 */ 11, 11, 6, 13, 11, 0, 0, 0, 0, 0, 0, 0, -/*x13 */ 12, 12, 6, 7, 12, 0, 0, 0, 0, 0, 0, 0, -/*x14 */ 13, 13, 13, 7, 13, 0, 0, 0, 0, 0, 0, 0, -/*x15 */ 14, 14, 14, 7, 14, 0, 0, 0, 0, 0, 0, 0, -/* 0:x4, 2:x5....BASE=4, MIN=4, MAX=25, INC=2 result = (xX-BASE)*INC */ + +/* CurrentFID--> 4x(00h) 5x(02h) 6x(04h) 7x(06h) ... + * -------------------------------------- + * TargetFID | Next_FID, Next_FID, Next_FID, Next_FID ... + * | | Next_FID, Next_FID, Next_FID, Next_FID ... + * \|/ | Next_FID, Next_FID, Next_FID, Next_FID ... + */ + static const u8 next_fid_200[] = { +/* x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 */ +/* x4 */ 0, -1, -1, -1, 0, 0, 9, 10, 11, 12, 13, 14, 15, /* 800 */ +/* x5 */ -1, 0, -1, -1, -1, 5, 5, 5, 11, 12, 13, 14, 15, /* 1000 */ +/* x6 */ -1, -1, 0, -1, -1, -1, -1, 6, 6, 6, 13, 14, 15, /* 1200 */ +/* x7 */ -1, -1, -1, 0, -1, -1, -1, -1, -1, 7, 7, 7, 15, /* 1400 */ +/* lower table to upper table boarder (table 70 and 71 in BKDG) */ +/* x8 */ 8, -1, -1, -1, 0, 8, 9, 10, 11, 12, 13, 14, 15, /* 1600 */ +/* x9 */ 9, 9, -1, -1, 9, 0, 9, 10, 11, 12, 13, 14, 15, /* 1800 */ +/*x10 */ 9, 10, -1, -1, 9, 10, 0, 10, 11, 12, 13, 14, 15, /* 2000 */ +/*x11 */ 9, 11, 11, -1, 9, 10, 11, 0, 11, 12, 13, 14, 15, /* 2200 */ +/*x12 */ 9, 11, 12, -1, 9, 10, 11, 12, 0, 12, 13, 14, 15, /* 2400 */ +/*x13 */ 9, 11, 13, 13, 9, 10, 11, 12, 13, 0, 13, 14, 15, /* 2600 */ +/*x14 */ 9, 11, 13, 14, 9, 10, 11, 12, 13, 14, 0, 14, 15, /* 2800 */ +/*x15 */ 9, 11, 13, 15, 9, 10, 11, 12, 13, 14, 15, 0, 15, /* 3000 */ +/*x15 */ 9, 11, 13, 15, 9, 10, 11, 12, 13, 14, 15, 16, 0, /* 3200 */ }; msr_t msr; - uint32_t vid; - uint32_t fid; + uint32_t vid_new; + uint32_t fid_new; uint32_t vid_max; uint32_t fid_max; uint32_t vid_cur; uint32_t fid_cur; unsigned apicidx; - int steps; + int step_limit; int loop; apicidx = lapicid(); @@ -140,21 +147,22 @@ return fidvid; } - fid = (fidvid >> 8) & 0x3f; - vid = (fidvid >> 16) & 0x3f; + fid_new = (fidvid >> 8) & 0x3f; + vid_new = (fidvid >> 16) & 0x3f; msr = rdmsr(0xc0010042); vid_cur = msr.hi & 0x3f; fid_cur = msr.lo & 0x3f; - if ((vid_cur==vid) && (fid_cur==fid)) + if ((vid_cur == vid_new) && (fid_cur == fid_new)) return fidvid; - vid_max = (msr.hi>>(48-32)) & 0x3f; - fid_max = ((msr.lo>>16) & 0x3f); /* max fid */ + vid_max = (msr.hi >> (48-32)) & 0x3f; + fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */ + #if FX_SUPPORT - if (fid_max>=((25-4)*2)) { /* FX max fid is 5G */ + if (fid_max >= ((25 - 4) * 2)) { /* FX max fid is 5G */ fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2; /* max FID is min fid + 1G */ if (fid_max >= ((25-4) * 2)) { fid_max = (10-4) * 2; /* hard set to 2G */ @@ -163,10 +171,20 @@ #endif /* set vid to max */ + /* TODO - make this more correct. Not a big deal for setting max... + * BKDG figure 11 + * if TargetFID > InitialFID + * TargetVID = FinalVID - RVO + * else + * if CurrentVID > FinalVID + * TargetVID = FinalVID - RVO + * else + * TargetVID = CurrentVIDD - RVO + */ msr.hi = 1; msr.lo = (vid_max << 8) | (fid_cur); #if SB_VFSMAF == 1 - msr.lo |= (1<<16); /* init changes */ + msr.lo |= (1 << 16); /* init changes */ #endif wrmsr(0xc0010041, msr); #if SB_VFSMAF == 0 @@ -174,38 +192,92 @@ #endif - for (loop=0;loop<100000;loop++){ + for (loop=0; loop < 100000; loop++){ msr = rdmsr(0xc0010042); - if (!(msr.lo & (1<<31))) + if (!(msr.lo & (1 << 31))) break; } vid_cur = msr.hi & 0x3f; - steps = 8; //?? - while ((fid_cur != fid) && (steps-- > 0)) { - uint32_t fid_temp; - if ((fid_cur > (8-4)*2) && (fid> (8-4)*2)) { - if (fid_cur<fid) { + /* BKDG figure 12 and 13 + * if current fid is odd + * current fid -1 (next lower and even fid)(odd fid for rev G) + * if current fid in high-freq table + * while current fid < target fid + * transition to next higher fid in table + * else if target fid > VCO portal of current fid + * transition to highest portal fid in higher fid table + * while current fid < target fid + * transition to next higher fid in table + * else + * transition to target fid + */ + + printk_debug("Current fid_cur: 0x%x, fid_max: 0x%x\n", fid_cur, fid_max); + printk_debug("Requested fid_new: 0x%x\n", fid_new); + + step_limit = 8; /* max 8 steps just in case... */ + while ((fid_cur != fid_new) && (step_limit--)) { + u32 fid_temp; + int step; + + if (fid_cur < fid_new) + /* Force Fid steps even. step == 0 means 100MHz step */ + step = ((fid_new/2) - (fid_cur/2)) * 2; + else + step = ((fid_cur/2) - (fid_new/2)) * 2; + + /* If 200Mhz step OR past 3200 max table value */ + if ((step == 2) || (fid_new >= 0x18 || fid_cur >= 0x18)) { + + printk_debug("200MHZ step "); + + /* Step +/- 200MHz at a time */ + if (fid_cur < fid_new) fid_temp = fid_cur + 2; - } else { - fid_temp = fid_cur - 2; - } - } else { - /* there is one < 8, So we need to lookup the table to - * find the fid_cur */ + else + fid_temp = fid_cur - 2; + + + } else if ( step > 2) { /* If more than a 200Mhz step */ int temp; - temp = next_fid_a[(fid_cur/2)*12+(fid/2)]; - if (temp <= 0) break; - fid_temp = (temp-4) * 2; + + /* look it up in the table */ + printk_debug("FidVid table step "); + + temp = next_fid_200[((fid_new/2) * 13) + (fid_cur/2)]; + + if (temp > 0) + fid_temp = (temp-4) * 2; /* Table 108 */ + else if (temp == 0) + fid_temp = fid_new; + else + break; /* table error */ + + } else { /* step < 2 (100MHZ) */ + printk_debug("100MHZ step "); + + /* The table adjust in 200MHz increments. If requested, + * do the 100MHz increment if the CPU supports it.*/ + if (cpuid_edx(0x80000007) & (1 << 6)) { + fid_temp = fid_cur + 1; + } else { + /* 100 MHZ not supported. Get out of the loop */ + printk_debug("is not supported.\n"); + break; + } } - if (fid_temp > fid_max) + + if(fid_temp > fid_max) { + printk_debug("fid_temp 0x%x > fid_max 0x%x\n", fid_temp, fid_max); break; + } - fid_cur = fid_temp; + printk_debug("fidvid: 0x%x\n", fid_temp); /* set target fid */ - msr.hi = (100000/5); - msr.lo = (vid_cur << 8) | fid_cur; + msr.hi = 0x190; /* 2 us for AMD NPT Family 0Fh Processors */ + msr.lo = (vid_cur << 8) | fid_temp; #if SB_VFSMAF == 1 msr.lo |= (1 << 16); /* init changes */ #endif @@ -217,8 +289,8 @@ #if K8_SET_FIDVID_DEBUG == 1 if (showmessage) { - print_debug_fv_8("\tapicid in set_fidvid = ", apicid); - print_debug_fv_64("ctrl msr fid, vid ", msr.hi, msr.lo); + print_debug_fv_8("set_fidvid APICID = ", apicid); + print_debug_fv_64("fidvid ctrl msr ", msr.hi, msr.lo); } #endif @@ -231,14 +303,24 @@ #if K8_SET_FIDVID_DEBUG == 1 if (showmessage) { - print_debug_fv_64("status msr fid, vid ", msr.hi, msr.lo); + print_debug_fv_64("fidvid status msr ", msr.hi, msr.lo); } #endif } /* set vid to final */ + /* TODO - make this more correct. Not a big deal for setting max... + * BKDG figure 11 + * if TargetFID > InitialFID + * TargetVID = FinalVID - RVO + * else + * if CurrentVID > FinalVID + * TargetVID = FinalVID - RVO + * else + * TargetVID = CurrentVIDD - RVO + */ msr.hi = 1; - msr.lo = (vid << 8) | (fid_cur); + msr.lo = (vid_new << 8) | (fid_cur); #if SB_VFSMAF == 1 msr.lo |= (1 << 16); // init changes #endif @@ -257,10 +339,10 @@ fidvid = (vid_cur << 16) | (fid_cur << 8); if (showmessage) { - if (vid!=vid_cur) { + if (vid_new != vid_cur) { print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n"); } - if (fid!=fid_cur) { + if (fid_new != fid_cur) { print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n"); } }

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[PATCH]: buildrom - add MSI MS-7620 platform
by Jordan Crouse 03 Nov '08

03 Nov '08

By special request on IRC. Jordan -- Jordan Crouse Systems Software Development Engineer Advanced Micro Devices, Inc.

2 1

r3725 build service
by coreboot information 03 Nov '08

03 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "jcrouse" checked in revision 3725 to the coreboot source repository and caused the following changes: Change Log: Move the default payload to be more buildrom friendly. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Build Log: Compilation of via:epia-cn has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3725&device=epia-cn&vendor… If something broke during this checkin please be a pain in jcrouse's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3725 - trunk/coreboot-v2/targets/msi/ms7260
by svn＠coreboot.org 03 Nov '08

03 Nov '08

Author: jcrouse Date: 2008-11-03 17:55:22 +0100 (Mon, 03 Nov 2008) New Revision: 3725 Modified: trunk/coreboot-v2/targets/msi/ms7260/Config.lb Log: Move the default payload to be more buildrom friendly. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/coreboot-v2/targets/msi/ms7260/Config.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms7260/Config.lb 2008-11-03 04:08:35 UTC (rev 3724) +++ trunk/coreboot-v2/targets/msi/ms7260/Config.lb 2008-11-03 16:55:22 UTC (rev 3725) @@ -32,7 +32,8 @@ option ROM_IMAGE_SIZE = 128 * 1024 option XIP_ROM_SIZE = 256 * 1024 option COREBOOT_EXTRA_VERSION = ".0Normal" - payload /tmp/filo.elf +# payload /tmp/filo.elf + payload ../payload.elf end romimage "fallback" @@ -41,7 +42,8 @@ option ROM_IMAGE_SIZE = 128 * 1024 option XIP_ROM_SIZE = 256 * 1024 option COREBOOT_EXTRA_VERSION = ".0Fallback" - payload /tmp/filo.elf +# payload /tmp/filo.elf + payload ../payload.elf end romimage "failover"

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ASUS P5GD1 Data for COREBOOT
by Enrico Mangosio 03 Nov '08

03 Nov '08

Dear All, Thanks for your work. COREBOOT sounds amazing. Herewith you'll find some info about my MB, as you requested. MB: ASUS P5GD1 I could do the same with a laptop Thinkpad X61 If you need.. Regards, Enrico.

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Re: [coreboot] r3723 - trunk/util/flashrom
by Peter Stuge 03 Nov '08

03 Nov '08

svn(a)coreboot.org wrote: > +++ trunk/util/flashrom/chipset_enable.c 2008-11-03 00:20:22 UTC (rev 3723) .. > case BUS_TYPE_ICH9_SPI: > - /* TODO: Add dumping function for ICH8/ICH9, or drop the > - * whole SPIBAR dumping from chipset_enable.c - There's > - * inteltool for this task already. > - */ > + tmp2 = *(uint16_t *) (spibar + 0); > + printf_debug("0x00: 0x%04x (HSFS)\n", tmp2); > + printf_debug("FLOCKDN %i, ", (tmp >> 15 & 1)); > + printf_debug("FDV %i, ", (tmp >> 14) & 1); > + printf_debug("FDOPSS %i, ", (tmp >> 13) & 1); Would have been nice if this had gone into ichspi.c. //Peter

3 3

Supermicro PDSMI+ motherboard
by J 03 Nov '08

03 Nov '08

Hello, Coreboot, I have a cluster of servers which might benefit from corebios. However, it seems the motherboard hasn't been tried yet, and the only chip I found a reference to in the "supported" tables was the superI/O. Any chance the list trails the development and I'm lucky? Motherboard - Supermicro PDSMi+ CPU - Intel Xeon dual core Northbridge - Intel 3000 Southbridge - Intel ICH7R Super I/O Winbond 83627HG Adaptec HostRaid lspci output: /coreboot# cat lspciout 00:00.0 Host bridge: Intel Corporation E7230/3000/3010 Memory Controller Hub (rev c0) 00:01.0 PCI bridge: Intel Corporation E7230/3000/3010 PCI Express Root Port (rev c0) 00:1c.0 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 1 (rev 01) 00:1c.4 PCI bridge: Intel Corporation 82801GR/GH/GHM (ICH7 Family) PCI Express Port 5 (rev 01) 00:1c.5 PCI bridge: Intel Corporation 82801GR/GH/GHM (ICH7 Family) PCI Express Port 6 (rev 01) 00:1d.0 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #1 (rev 01) 00:1d.1 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #2 (rev 01) 00:1d.2 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #3 (rev 01) 00:1d.3 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #4 (rev 01) 00:1d.7 USB Controller: Intel Corporation 82801G (ICH7 Family) USB2 EHCI Controller (rev 01) 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev e1) 00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge (rev 01) 00:1f.1 IDE interface: Intel Corporation 82801G (ICH7 Family) IDE Controller (rev 01) 00:1f.3 SMBus: Intel Corporation 82801G (ICH7 Family) SMBus Controller (rev 01) 09:00.0 PCI bridge: Intel Corporation 6702PXH PCI Express-to-PCI Bridge A (rev 09) 09:00.1 PIC: Intel Corporation 6700/6702PXH I/OxAPIC Interrupt Controller A (rev 09) 0d:00.0 Ethernet controller: Intel Corporation 82573E Gigabit Ethernet Controller (Copper) (rev 03) 0e:00.0 Ethernet controller: Intel Corporation 82573L Gigabit Ethernet Controller 0f:00.0 VGA compatible controller: ATI Technologies Inc ES1000 (rev 02) jlm-bdt:/home BIOS Device - SST 49LF008A (32-pin PLCC) http://www.sst.com/products.xhtml/serial_flash/49/SST49LF008A Motherboard URL: http://www.supermicro.com/products/motherboard/Xeon3000/3000/PDSMi+.cfm Thanks in advance for your response. John

1 0

r3724 build service
by coreboot information 03 Nov '08

03 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "rminnich" checked in revision 3724 to the coreboot source repository and caused the following changes: Change Log: modify pirq tables for epia-cn. Not tested, builds, derived from getpir. Definitely better than what was there. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Bari Ari <bari(a)onelabs.com> Build Log: Compilation of bcom:winnetp680 has been fixed If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3724 - trunk/coreboot-v2/src/mainboard/via/epia-cn
by svn＠coreboot.org 03 Nov '08

03 Nov '08

Author: rminnich Date: 2008-11-03 05:08:35 +0100 (Mon, 03 Nov 2008) New Revision: 3724 Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c Log: modify pirq tables for epia-cn. Not tested, builds, derived from getpir. Definitely better than what was there. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Bari Ari <bari(a)onelabs.com> Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb 2008-11-03 00:20:22 UTC (rev 3723) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb 2008-11-03 04:08:35 UTC (rev 3724) @@ -81,7 +81,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default HAVE_HARD_RESET = 0 default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 10 +default IRQ_SLOT_COUNT = 9 default HAVE_ACPI_TABLES = 0 default HAVE_OPTION_TABLE = 1 default ROM_IMAGE_SIZE = 64 * 1024 Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c 2008-11-03 00:20:22 UTC (rev 3723) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/irq_tables.c 2008-11-03 04:08:35 UTC (rev 3724) @@ -27,24 +27,23 @@ 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x11 << 3) | 0x0, /* Interrupt router device */ - 0x828, /* IRQs devoted exclusively to PCI usage */ + 0xc20, /* IRQs devoted exclusively to PCI usage */ 0x1106, /* Vendor */ 0x596, /* Device */ 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x3e, /* Checksum */ + 0x66, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, - {0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, - {0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0}, - {0x00,(0x0c<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0}, - {0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x10<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x12<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0}, + {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x4, 0x0}, + {0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x0f<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x12<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, } };

1 0

patch: fix up epia-cn PIRQ
by ron minnich 03 Nov '08

03 Nov '08

attached.

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coreboot November 2008