coreboot November 2008

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[PCI Utilities PATCH] Decode HyperTransport 1.02 as 1.03
by Carl-Daniel Hailfinger 03 Nov '08

03 Nov '08

AMD K8 processors claim that they're using HyperTransport 1.02, but the publicly available documentation (specifically the BKDG) states that the HT version is 1.03 in reality. lspci will issue a warning "!!! Possibly incomplete decoding" and only decode some basic HT properties for HT versions before 1.03. Move that boundary down to HT version 1.02. Example output before the patch: 00:18.0 0600: 1022:1100 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Example output with the same processor after the patch: 00:18.0 0600: 1022:1100 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Revision ID: 1.02 Link Frequency: 1.0GHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> -- http://www.hailfinger.org/

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[PATCH] fix CONFIG_FS_PAYLOAD=1
by Jens Rottmann 03 Nov '08

03 Nov '08

Fix compile errors if CONFIG_FS_PAYLOAD=1: Compile error in filo.c if AUTOBOOT_DELAY=0. Replace #ifndef AUTOBOOT_DELAY with #if !AUTOBOOT_DELAY which should work for both the #undef and the =0 case. In ext2fs.c, fat.c #if ARCH == 'i386' results in a compile warning: "multi-character character constant" and the condition ARCH == 'i386' is mis-evaluated as FALSE, eventually choking the assembler on a PPC instruction. Change it to #ifdef __i386 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> --- Hi, yes, I already posted this last week, together with 1 other patch, but got no response. Now I'll try splitting it up to 2 seperate mails, hopefully that works better. Regards, Jens Rottmann Index: src/boot/filo.c =================================================================== --- src/boot/filo.c (revision 3724) +++ src/boot/filo.c (working copy) @@ -18,7 +18,7 @@ #define autoboot(mem) #endif -#ifndef AUTOBOOT_DELAY +#if !AUTOBOOT_DELAY #define autoboot_delay() 0 /* success */ #endif Index: src/stream/fs/ext2fs.c =================================================================== --- src/stream/fs/ext2fs.c (revision 3724) +++ src/stream/fs/ext2fs.c (working copy) @@ -239,7 +239,7 @@ * ffz = Find First Zero in word. Undefined if no zero exists, * so code should check against ~0UL first.. */ -#if ARCH == 'i386' +#ifdef __i386 static __inline__ unsigned long ffz (unsigned long word) { Index: src/stream/fs/fat.c =================================================================== --- src/stream/fs/fat.c (revision 3724) +++ src/stream/fs/fat.c (working copy) @@ -54,7 +54,7 @@ #define FAT_CACHE_SIZE 2048 -#if ARCH == 'i386' +#ifdef __i386 static __inline__ unsigned long log2 (unsigned long word) {

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r3729 - in trunk/coreboot-v2/src: boot stream/fs
by svn＠coreboot.org 03 Nov '08

03 Nov '08

Author: stepan Date: 2008-11-04 00:16:00 +0100 (Tue, 04 Nov 2008) New Revision: 3729 Modified: trunk/coreboot-v2/src/boot/filo.c trunk/coreboot-v2/src/stream/fs/ext2fs.c trunk/coreboot-v2/src/stream/fs/fat.c Log: Fix compile errors if CONFIG_FS_PAYLOAD=1: Compile error in filo.c if AUTOBOOT_DELAY=0. Replace #ifndef AUTOBOOT_DELAY with #if !AUTOBOOT_DELAY which should work for both the #undef and the =0 case. In ext2fs.c, fat.c #if ARCH == 'i386' results in a compile warning: "multi-character character constant" and the condition ARCH == 'i386' is mis-evaluated as FALSE, eventually choking the assembler on a PPC instruction. Change it to #ifdef __i386 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/boot/filo.c =================================================================== --- trunk/coreboot-v2/src/boot/filo.c 2008-11-03 22:58:56 UTC (rev 3728) +++ trunk/coreboot-v2/src/boot/filo.c 2008-11-03 23:16:00 UTC (rev 3729) @@ -18,7 +18,7 @@ #define autoboot(mem) #endif -#ifndef AUTOBOOT_DELAY +#if !AUTOBOOT_DELAY #define autoboot_delay() 0 /* success */ #endif Modified: trunk/coreboot-v2/src/stream/fs/ext2fs.c =================================================================== --- trunk/coreboot-v2/src/stream/fs/ext2fs.c 2008-11-03 22:58:56 UTC (rev 3728) +++ trunk/coreboot-v2/src/stream/fs/ext2fs.c 2008-11-03 23:16:00 UTC (rev 3729) @@ -239,7 +239,7 @@ * ffz = Find First Zero in word. Undefined if no zero exists, * so code should check against ~0UL first.. */ -#if ARCH == 'i386' +#ifdef __i386 static __inline__ unsigned long ffz (unsigned long word) { Modified: trunk/coreboot-v2/src/stream/fs/fat.c =================================================================== --- trunk/coreboot-v2/src/stream/fs/fat.c 2008-11-03 22:58:56 UTC (rev 3728) +++ trunk/coreboot-v2/src/stream/fs/fat.c 2008-11-03 23:16:00 UTC (rev 3729) @@ -54,7 +54,7 @@ #define FAT_CACHE_SIZE 2048 -#if ARCH == 'i386' +#ifdef __i386 static __inline__ unsigned long log2 (unsigned long word) {

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r3727 build service
by coreboot information 03 Nov '08

03 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "mjones" checked in revision 3727 to the coreboot source repository and caused the following changes: Change Log: Set asus/a8v-3_se to use printk in CAR. (trivial) Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Marc Jones <marc.jones(a)amd.com> Build Log: Compilation of asus:a8v-e_se has been fixed If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] IT8712F GPIO resources
by Jens Rottmann 03 Nov '08

03 Nov '08

Add the missing I/O resources for IT8712F GPIOs. (E.g. some LiPPERT boards need them to switch the com ports from RS232 to RS485.) The PnP resources should prevent other devices from being mapped at the same spot, even if no OS driver actively uses them. The IT8712F manual makes it look like PNP_IO1 had a size/granularity of 1 byte, but that must be a mistake. The Simple-I/O resource has a size of 5 bytes (1 for each GPIO set 1-5) and trying different addresses reveals a granularity of 8. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> --- Hi, yes, I already posted this patch last week, together with 2 others, but got no response. Now I'll try splitting it up to 2 seperate mails, hopefully that works better. Regards, Jens Rottmann Index: src/superio/ite/it8712f/superio.c =================================================================== --- src/superio/ite/it8712f/superio.c (revision 3724) +++ src/superio/ite/it8712f/superio.c (working copy) @@ -129,7 +129,7 @@ {&ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xff8, 0}, {0xff8, 4},}, {&ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfff, 0}, {0xfff, 4},}, {&ops, IT8712F_KBCM, PNP_IRQ0,}, - {&ops, IT8712F_GPIO,}, + {&ops, IT8712F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, {0xfff, 0}, {0xff8, 0}, {0xff8, 0},}, {&ops, IT8712F_MIDI, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, {&ops, IT8712F_GAME, PNP_IO0, {0xfff, 0},}, {&ops, IT8712F_IR, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},

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r3728 - trunk/coreboot-v2/src/superio/ite/it8712f
by svn＠coreboot.org 03 Nov '08

03 Nov '08

Author: mjones Date: 2008-11-03 23:58:56 +0100 (Mon, 03 Nov 2008) New Revision: 3728 Modified: trunk/coreboot-v2/src/superio/ite/it8712f/superio.c Log: Add the missing I/O resources for IT8712F GPIOs. (E.g. some LiPPERT boards need them to switch the com ports from RS232 to RS485.) The PnP resources should prevent other devices from being mapped at the same spot, even if no OS driver actively uses them. The IT8712F manual makes it look like PNP_IO1 had a size/granularity of 1 byte, but that must be a mistake. The Simple-I/O resource has a size of 5 bytes (1 for each GPIO set 1-5) and trying different addresses reveals a granularity of 8. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: trunk/coreboot-v2/src/superio/ite/it8712f/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8712f/superio.c 2008-11-03 22:46:27 UTC (rev 3727) +++ trunk/coreboot-v2/src/superio/ite/it8712f/superio.c 2008-11-03 22:58:56 UTC (rev 3728) @@ -129,7 +129,7 @@ {&ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xff8, 0}, {0xff8, 4},}, {&ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfff, 0}, {0xfff, 4},}, {&ops, IT8712F_KBCM, PNP_IRQ0,}, - {&ops, IT8712F_GPIO,}, + {&ops, IT8712F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, {0xfff, 0}, {0xff8, 0}, {0xff8, 0},}, {&ops, IT8712F_MIDI, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, {&ops, IT8712F_GAME, PNP_IO0, {0xfff, 0},}, {&ops, IT8712F_IR, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},

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r3727 - trunk/coreboot-v2/src/mainboard/asus/a8v-e_se
by svn＠coreboot.org 03 Nov '08

03 Nov '08

Author: mjones Date: 2008-11-03 23:46:27 +0100 (Mon, 03 Nov 2008) New Revision: 3727 Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb Log: Set asus/a8v-3_se to use printk in CAR. (trivial) Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb 2008-11-03 21:39:03 UTC (rev 3726) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb 2008-11-03 22:46:27 UTC (rev 3727) @@ -91,6 +91,7 @@ uses SB_HT_CHAIN_ON_BUS0 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_USE_PRINTK_IN_CAR default ROM_SIZE = 512 * 1024 default FALLBACK_SIZE = 256 * 1024 @@ -158,6 +159,7 @@ default CC = "$(CROSS_COMPILE)gcc -m32" default HOSTCC = "gcc" default CONFIG_GDB_STUB = 0 +default CONFIG_USE_PRINTK_IN_CAR = 1 default CONFIG_CONSOLE_SERIAL8250 = 1 default TTYS0_BAUD = 115200 default TTYS0_BASE = 0x3f8

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HT revision 1.02 in K8
by Carl-Daniel Hailfinger 03 Nov '08

03 Nov '08

Hi, I'm getting the following message from lspci on my K8 machine: 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding for revision 1.02 Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Kernel modules: ipmi_si 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 00 00 00 00 e4 00 00 00 0f cc 00 0f 0c 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 00 01 21 20 00 11 11 22 05 35 80 02 00 00 00 90: 69 01 61 01 00 00 ff 00 07 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Note the warning about "Possibly incomplete decoding" which stems from the fact that the processor mentions HT revision 1.02 which is the last non-public revision. Every revision from 1.03 and beyond seems to be publically available. Now the big question is: Can we decode HT 1.02 like HT 1.03 or have there been fundamental changes in between? I'd like to create a patch for PCIutils (lspci) so we can have full info without a warning message. Regards, Carl-Daniel -- http://www.hailfinger.org/

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r3726 build service
by coreboot information 03 Nov '08

03 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "mjones" checked in revision 3726 to the coreboot source repository and caused the following changes: Change Log: Update K8 FID/VID setup. Add support for 100MHz FIDs (revG). Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of asus:a8v-e_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3726&device=a8v-e_se&vendo… Compilation of via:epia-cn has been fixed If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2][patch] update k8 fid/vid setup
by Marc Jones 03 Nov '08

03 Nov '08

See attached patch. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Update K8 FID/VID setup. Add support for 100MHz FIDs (revG). Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: coreboot-v2/src/cpu/amd/model_fxx/fidvid.c =================================================================== --- coreboot-v2.orig/src/cpu/amd/model_fxx/fidvid.c 2008-08-22 07:38:01.000000000 -0600 +++ coreboot-v2/src/cpu/amd/model_fxx/fidvid.c 2008-08-22 13:08:15.000000000 -0600 @@ -99,27 +99,34 @@ static unsigned set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) { - /* for (cur, new) there is one <1600MHz x8 to find out next_fid */ - static const uint8_t next_fid_a[] = { - /* x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 */ -/* x4 */ 0, 9, 9, 8, 9, 9, 9, 9, 9, 9, 9, 9, -/* x5 */ 9, 0, 11, 11, 9, 9, 10, 11, 11, 11, 11, 11, -/* x6 */ 11, 11, 0, 13, 11, 11, 11, 11, 12, 13, 13, 13, -/* x7 */ 13, 13, 13, 0, 13, 13, 13, 13, 13, 13, 14, 15, -/* x8 */ 4, 9, 9, 9, 0, 9, 9, 9, 9, 9, 9, 9, -/* x9 */ 4, 5, 10, 10, 8, 0, 0, 0, 0, 0, 0, 0, -/*x10 */ 9, 5, 11, 11, 9, 0, 0, 0, 0, 0, 0, 0, -/*x11 */ 10, 5, 6, 12, 10, 0, 0, 0, 0, 0, 0, 0, -/*x12 */ 11, 11, 6, 13, 11, 0, 0, 0, 0, 0, 0, 0, -/*x13 */ 12, 12, 6, 7, 12, 0, 0, 0, 0, 0, 0, 0, -/*x14 */ 13, 13, 13, 7, 13, 0, 0, 0, 0, 0, 0, 0, -/*x15 */ 14, 14, 14, 7, 14, 0, 0, 0, 0, 0, 0, 0, -/* 0:x4, 2:x5....BASE=4, MIN=4, MAX=25, INC=2 result = (xX-BASE)*INC */ + +/* CurrentFID--> 4x(00h) 5x(02h) 6x(04h) 7x(06h) ... + * -------------------------------------- + * TargetFID | Next_FID, Next_FID, Next_FID, Next_FID ... + * | | Next_FID, Next_FID, Next_FID, Next_FID ... + * \|/ | Next_FID, Next_FID, Next_FID, Next_FID ... + */ + static const uint8_t next_fid_200[] = { +/* x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 */ +/* x4 */ 0, -1, -1, -1, 0, 0, 9, 10, 11, 12, 13, 14, 15, /* 800 */ +/* x5 */ -1, 0, -1, -1, -1, 5, 5, 5, 11, 12, 13, 14, 15, /* 1000 */ +/* x6 */ -1, -1, 0, -1, -1, -1, -1, 6, 6, 6, 13, 14, 15, /* 1200 */ +/* x7 */ -1, -1, -1, 0, -1, -1, -1, -1, -1, 7, 7, 7, 15, /* 1400 */ +/* lower table to upper table boarder (table 70 and 71 in BKDG) */ +/* x8 */ 8, -1, -1, -1, 0, 8, 9, 10, 11, 12, 13, 14, 15, /* 1600 */ +/* x9 */ 9, 9, -1, -1, 9, 0, 9, 10, 11, 12, 13, 14, 15, /* 1800 */ +/*x10 */ 9, 10, -1, -1, 9, 10, 0, 10, 11, 12, 13, 14, 15, /* 2000 */ +/*x11 */ 9, 11, 11, -1, 9, 10, 11, 0, 11, 12, 13, 14, 15, /* 2200 */ +/*x12 */ 9, 11, 12, -1, 9, 10, 11, 12, 0, 12, 13, 14, 15, /* 2400 */ +/*x13 */ 9, 11, 13, 13, 9, 10, 11, 12, 13, 0, 13, 14, 15, /* 2600 */ +/*x14 */ 9, 11, 13, 14, 9, 10, 11, 12, 13, 14, 0, 14, 15, /* 2800 */ +/*x15 */ 9, 11, 13, 15, 9, 10, 11, 12, 13, 14, 15, 0, 15, /* 3000 */ +/*x15 */ 9, 11, 13, 15, 9, 10, 11, 12, 13, 14, 15, 16, 0, /* 3200 */ }; msr_t msr; - uint32_t vid; - uint32_t fid; + uint32_t vid_new; + uint32_t fid_new; uint32_t vid_max; uint32_t fid_max; uint32_t vid_cur; @@ -140,19 +147,20 @@ return fidvid; } - fid = (fidvid >> 8) & 0x3f; - vid = (fidvid >> 16) & 0x3f; + fid_new = (fidvid >> 8) & 0x3f; + vid_new = (fidvid >> 16) & 0x3f; msr = rdmsr(0xc0010042); vid_cur = msr.hi & 0x3f; fid_cur = msr.lo & 0x3f; - if ((vid_cur==vid) && (fid_cur==fid)) + if ((vid_cur==vid_new) && (fid_cur==fid_new)) return fidvid; vid_max = (msr.hi>>(48-32)) & 0x3f; fid_max = ((msr.lo>>16) & 0x3f); /* max fid */ + #if FX_SUPPORT if (fid_max>=((25-4)*2)) { /* FX max fid is 5G */ fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2; /* max FID is min fid + 1G */ @@ -163,10 +171,20 @@ #endif /* set vid to max */ + /* TODO - make this more correct. Not a big deal for setting max... + * BKDG figure 11 + * if TargetFID > InitialFID + * TargetVID = FinalVID - RVO + * else + * if CurrentVID > FinalVID + * TargetVID = FinalVID - RVO + * else + * TargetVID = CurrentVIDD - RVO + */ msr.hi = 1; msr.lo = (vid_max << 8) | (fid_cur); #if SB_VFSMAF == 1 - msr.lo |= (1<<16); /* init changes */ + msr.lo |= (1 << 16); /* init changes */ #endif wrmsr(0xc0010041, msr); #if SB_VFSMAF == 0 @@ -181,31 +199,63 @@ } vid_cur = msr.hi & 0x3f; - steps = 8; //?? - while ((fid_cur != fid) && (steps-- > 0)) { + /* BKDG figure 12 and 13 + * if current fid is odd + * current fid -1 (next lower and even fid)(odd fid for rev G) + * if current fid in high-freq table + * while current fid < target fid + * transition to next higher fid in table + * else if target fid > VCO portal of current fid + * transition to highest portal fid in higher fid table + * while current fid < target fid + * transition to next higher fid in table + * else + * transition to target fid + */ + + steps = 8; /* max 8 steps just in case... */ + while ((fid_cur != fid_new) && (steps-- > 0)) { uint32_t fid_temp; - if ((fid_cur > (8-4)*2) && (fid> (8-4)*2)) { - if (fid_cur<fid) { - fid_temp = fid_cur + 2; - } else { + + /* If more than a 200Mhz step */ + if ((fid_cur - 2 != fid_new) && (fid_cur + 2 != fid_new)) { + /* Find the table value if it is in the table */ + if (fid_new <= 0x18) { /* 3200 max table value */ + int temp; + + temp = next_fid_200[((fid_cur/2) * 13) + (fid_new/2)]; + + if (temp > 0) + fid_temp = (temp-4) * 2; + else if (temp == 0) + fid_temp = fid_new; + else + break; /* table error */ + + } else { /* above table, step +/- 200MHz at a time */ + if (fid_cur < fid_new) + fid_temp = fid_cur + 2; + else fid_temp = fid_cur - 2; - } - } else { - /* there is one < 8, So we need to lookup the table to - * find the fid_cur */ - int temp; - temp = next_fid_a[(fid_cur/2)*12+(fid/2)]; - if (temp <= 0) break; - fid_temp = (temp-4) * 2; + } + } else { /* just do the 200Mhz step */ + fid_temp = fid_new; + } + + /* The table adjust in 200MHz increments. If the next table + * entry is higher than the requested fid we can do + * the 100MHz increment if the CPU supports it.*/ + if (cpuid_ecx(0x80000007) & (1 << 6)) { /* 100MHz? */ + if ((fid_temp > fid_new) && (fid_cur < fid_new)) + fid_temp = fid_new; } - if (fid_temp > fid_max) - break; - fid_cur = fid_temp; + if(fid_temp>fid_max) + break; /* set target fid */ - msr.hi = (100000/5); - msr.lo = (vid_cur << 8) | fid_cur; + msr.hi = 0x190; /* 2 us for AMD NPT Family 0Fh Processors */ + msr.lo = (vid_cur << 8) | fid_temp; #if SB_VFSMAF == 1 msr.lo |= (1 << 16); /* init changes */ #endif @@ -231,14 +281,24 @@ #if K8_SET_FIDVID_DEBUG == 1 if (showmessage) { - print_debug_fv_64("status msr fid, vid ", msr.hi, msr.lo); + print_debug_fv_64("status msr fid, vid ", msr.hi, msr.lo); } #endif } /* set vid to final */ + /* TODO - make this more correct. Not a big deal for setting max... + * BKDG figure 11 + * if TargetFID > InitialFID + * TargetVID = FinalVID - RVO + * else + * if CurrentVID > FinalVID + * TargetVID = FinalVID - RVO + * else + * TargetVID = CurrentVIDD - RVO + */ msr.hi = 1; - msr.lo = (vid << 8) | (fid_cur); + msr.lo = (vid_new << 8) | (fid_cur); #if SB_VFSMAF == 1 msr.lo |= (1 << 16); // init changes #endif @@ -257,10 +317,10 @@ fidvid = (vid_cur << 16) | (fid_cur << 8); if (showmessage) { - if (vid!=vid_cur) { + if (vid_new!=vid_cur) { print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n"); } - if (fid!=fid_cur) { + if (fid_new!=fid_cur) { print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n"); } }

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coreboot November 2008