Hi, I'm getting the following message from lspci on my K8 machine: 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding for revision 1.02 Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Kernel modules: ipmi_si 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 00 00 00 00 e4 00 00 00 0f cc 00 0f 0c 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 00 01 21 20 00 11 11 22 05 35 80 02 00 00 00 90: 69 01 61 01 00 00 ff 00 07 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Note the warning about "Possibly incomplete decoding" which stems from the fact that the processor mentions HT revision 1.02 which is the last non-public revision. Every revision from 1.03 and beyond seems to be publically available. Now the big question is: Can we decode HT 1.02 like HT 1.03 or have there been fundamental changes in between? I'd like to create a patch for PCIutils (lspci) so we can have full info without a warning message. Regards, Carl-Daniel -- http://www.hailfinger.org/
On 24.10.2008 17:13, Carl-Daniel Hailfinger wrote:
Hi,
I'm getting the following message from lspci on my K8 machine:
00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding for revision 1.02 Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Kernel modules: ipmi_si
Note the warning about "Possibly incomplete decoding" which stems from the fact that the processor mentions HT revision 1.02 which is the last non-public revision. Every revision from 1.03 and beyond seems to be publically available. Now the big question is: Can we decode HT 1.02 like HT 1.03 or have there been fundamental changes in between? I'd like to create a patch for PCIutils (lspci) so we can have full info without a warning message.
I forgot to specify the processor: /proc/cpuinfo processor : 0 vendor_id : AuthenticAMD cpu family : 15 model : 44 model name : AMD Sempron(tm) Processor 3000+ stepping : 2 cpu MHz : 1800.000 cache size : 128 KB fpu : yes fpu_exception : yes cpuid level : 1 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx mmxext fxsr_opt lm 3dnowext 3dnow up pni lahf_lm bogomips : 3620.86 TLB size : 1024 4K pages clflush size : 64 cache_alignment : 64 address sizes : 40 bits physical, 48 bits virtual power management: ts fid vid ttp tm stc Regards, Carl-Daniel -- http://www.hailfinger.org/
On Fri, Oct 24, 2008 at 9:21 AM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2006@gmx.net> wrote:
On 24.10.2008 17:13, Carl-Daniel Hailfinger wrote:
Hi,
I'm getting the following message from lspci on my K8 machine:
00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding for revision 1.02 Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Kernel modules: ipmi_si
Note the warning about "Possibly incomplete decoding" which stems from the fact that the processor mentions HT revision 1.02 which is the last non-public revision. Every revision from 1.03 and beyond seems to be publically available. Now the big question is: Can we decode HT 1.02 like HT 1.03 or have there been fundamental changes in between? I'd like to create a patch for PCIutils (lspci) so we can have full info without a warning message.
From the BKDG: 3.1 Configuration Space Accesses The AMD Athlon™ 64 and AMD Opteron™ Processors implement configuration space as defined in the PCI Local Bus Specification, Rev. 2.2, and the HyperTransport™ I/O Link Specification, Rev. 1.03.
I read that to mean that even though the processor reports Rev 1.02, it's 1.03. Thanks, Myles
Hi Marc, maybe you can shed some light on the problem below. Basically, the K8 reports in lspci that it supports HT 1.02, but the BKDG says it uses HT 1.03. And HT 1.03 is the first publicly available spec. On 03.11.2008 17:24, Myles Watson wrote:
On Fri, Oct 24, 2008 at 9:21 AM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2006@gmx.net> wrote:
On 24.10.2008 17:13, Carl-Daniel Hailfinger wrote:
Hi,
I'm getting the following message from lspci on my K8 machine:
00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding for revision 1.02 Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Kernel modules: ipmi_si
Note the warning about "Possibly incomplete decoding" which stems from the fact that the processor mentions HT revision 1.02 which is the last non-public revision. Every revision from 1.03 and beyond seems to be publically available. Now the big question is: Can we decode HT 1.02 like HT 1.03 or have there been fundamental changes in between? I'd like to create a patch for PCIutils (lspci) so we can have full info without a warning message.
From the BKDG: 3.1 Configuration Space Accesses The AMD Athlon™ 64 and AMD Opteron™ Processors implement configuration space as defined in the PCI Local Bus Specification, Rev. 2.2, and the HyperTransport™ I/O Link Specification, Rev. 1.03.
I read that to mean that even though the processor reports Rev 1.02, it's 1.03.
That certainly would make sense. Regards, Carl-Daniel -- http://www.hailfinger.org/
Carl-Daniel Hailfinger wrote:
Hi Marc,
maybe you can shed some light on the problem below.
Basically, the K8 reports in lspci that it supports HT 1.02, but the BKDG says it uses HT 1.03. And HT 1.03 is the first publicly available spec.
I am not sure why you are blowing this out of proportion. It is a warning. It isn't a problem. If you examine the freely available K8 BKDG, you will find that registers in the K8 match the 1.03 revision of the spec. Thus, the settings read by lspci are decoded correctly. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors
Hi Marc, On 03.11.2008 22:21, Marc Jones wrote:
Carl-Daniel Hailfinger wrote:
Hi Marc,
maybe you can shed some light on the problem below.
Basically, the K8 reports in lspci that it supports HT 1.02, but the BKDG says it uses HT 1.03. And HT 1.03 is the first publicly available spec.
I am not sure why you are blowing this out of proportion.
I'm very sorry if my questions gave that impression.
It is a warning. It isn't a problem. If you examine the freely available K8 BKDG, you will find that registers in the K8 match the 1.03 revision of the spec.
Thanks for confirming this.
Thus, the settings read by lspci are decoded correctly.
Actually, the settings decoded by lspci are incomplete because of the version mismatch. I'll send a patch to lspci maintainers with a workaround. Regards, Carl-Daniel -- http://www.hailfinger.org/
On Fri, Oct 24, 2008 at 11:13 AM, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> wrote:
Note the warning about "Possibly incomplete decoding" which stems from the fact that the processor mentions HT revision 1.02 which is the last non-public revision. Every revision from 1.03 and beyond seems to be publically available. Now the big question is: Can we decode HT 1.02 like HT 1.03 or have there been fundamental changes in between? I'd like to create a patch for PCIutils (lspci) so we can have full info without a warning message.
I think the only people who can really answer that are inside AMD. My company is NDAed with AMD, and also a HyperTransport Consortium member, but I have only ever seen the 1.03 spec and later. I also have not found a changelog from 1.02 to 1.03. Maybe Jordan and/or Marc might be able to help.
participants (4)
-
Carl-Daniel Hailfinger -
Marc Jones -
Myles Watson -
Tom Sylla