In northbridge/intel/i440bx/raminit.c:sdram_set_spd_registers all PAM registers are programmed for RAM R/W access (0x33). When SeaBIOS searches for option ROMs (including VGA ROM) it doesn't do anything about PAM, so it sees empty memory instead of the ROMs.
I am not sure what is the best solution here. It is debatable how coreboot should set PAM register, and it is not right to make SeaBIOS too hardware dependent.
Maybe coreboot could somehow export functions for setting access to option ROM space (aka legacy memory segments) and SeaBIOS could call them.
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Andriy Gapon Sent: Thursday, October 30, 2008 8:25 AM To: Coreboot Subject: [coreboot] coreboot.v2+seabios on 440bx: option roms not found
In northbridge/intel/i440bx/raminit.c:sdram_set_spd_registers all PAM registers are programmed for RAM R/W access (0x33). When SeaBIOS searches for option ROMs (including VGA ROM) it doesn't do anything about PAM, so it sees empty memory instead of the ROMs.
I am not sure what is the best solution here. It is debatable how coreboot should set PAM register, and it is not right to make SeaBIOS too hardware dependent.
Maybe coreboot could somehow export functions for setting access to option ROM space (aka legacy memory segments) and SeaBIOS could call them.
I think SeaBIOS expects Coreboot to copy the option ROM to 0xc0000 in RAM. That way SeaBIOS gets to stay hardware agnostic.
Myles
-- Andriy Gapon
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
on 30/10/2008 16:34 Myles Watson said the following:
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Andriy Gapon Sent: Thursday, October 30, 2008 8:25 AM To: Coreboot Subject: [coreboot] coreboot.v2+seabios on 440bx: option roms not found
In northbridge/intel/i440bx/raminit.c:sdram_set_spd_registers all PAM registers are programmed for RAM R/W access (0x33). When SeaBIOS searches for option ROMs (including VGA ROM) it doesn't do anything about PAM, so it sees empty memory instead of the ROMs.
I am not sure what is the best solution here. It is debatable how coreboot should set PAM register, and it is not right to make SeaBIOS too hardware dependent.
Maybe coreboot could somehow export functions for setting access to option ROM space (aka legacy memory segments) and SeaBIOS could call them.
I think SeaBIOS expects Coreboot to copy the option ROM to 0xc0000 in RAM. That way SeaBIOS gets to stay hardware agnostic.
Makes sense! But it doesn't look like this does actually happen (by default). I am playing with msi/ms6147 target (under heavily tweaked qemu).
-----Original Message----- From: Andriy Gapon [mailto:avg@icyb.net.ua] Sent: Thursday, October 30, 2008 8:43 AM To: Myles Watson Cc: 'Coreboot' Subject: Re: [coreboot] coreboot.v2+seabios on 440bx: option roms not found
on 30/10/2008 16:34 Myles Watson said the following:
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-
bounces@coreboot.org]
On Behalf Of Andriy Gapon Sent: Thursday, October 30, 2008 8:25 AM To: Coreboot Subject: [coreboot] coreboot.v2+seabios on 440bx: option roms not found
In northbridge/intel/i440bx/raminit.c:sdram_set_spd_registers all PAM registers are programmed for RAM R/W access (0x33). When SeaBIOS searches for option ROMs (including VGA ROM) it doesn't do anything about PAM, so it sees empty memory instead of the ROMs.
I am not sure what is the best solution here. It is debatable how coreboot should set PAM register, and it is not right to make SeaBIOS too hardware dependent.
Maybe coreboot could somehow export functions for setting access to option ROM space (aka legacy memory segments) and SeaBIOS could call
them.
I think SeaBIOS expects Coreboot to copy the option ROM to 0xc0000 in
RAM.
That way SeaBIOS gets to stay hardware agnostic.
Makes sense! But it doesn't look like this does actually happen (by default). I am playing with msi/ms6147 target (under heavily tweaked qemu).
You're right. It doesn't happen by default. Kevin sent a simple patch to the list, which I can't find right now :(
Basically you tell coreboot to run the ROM, but comment out the execution right after the copy. Let me know if you can't find it, and I'll try to help you dig.
Thanks, Myles
-- Andriy Gapon
on 30/10/2008 16:52 Myles Watson said the following:
-----Original Message----- From: Andriy Gapon [mailto:avg@icyb.net.ua] Sent: Thursday, October 30, 2008 8:43 AM To: Myles Watson Cc: 'Coreboot' Subject: Re: [coreboot] coreboot.v2+seabios on 440bx: option roms not found
on 30/10/2008 16:34 Myles Watson said the following:
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-
bounces@coreboot.org]
On Behalf Of Andriy Gapon Sent: Thursday, October 30, 2008 8:25 AM To: Coreboot Subject: [coreboot] coreboot.v2+seabios on 440bx: option roms not found
In northbridge/intel/i440bx/raminit.c:sdram_set_spd_registers all PAM registers are programmed for RAM R/W access (0x33). When SeaBIOS searches for option ROMs (including VGA ROM) it doesn't do anything about PAM, so it sees empty memory instead of the ROMs.
I am not sure what is the best solution here. It is debatable how coreboot should set PAM register, and it is not right to make SeaBIOS too hardware dependent.
Maybe coreboot could somehow export functions for setting access to option ROM space (aka legacy memory segments) and SeaBIOS could call
them.
I think SeaBIOS expects Coreboot to copy the option ROM to 0xc0000 in
RAM.
That way SeaBIOS gets to stay hardware agnostic.
Makes sense! But it doesn't look like this does actually happen (by default). I am playing with msi/ms6147 target (under heavily tweaked qemu).
You're right. It doesn't happen by default. Kevin sent a simple patch to the list, which I can't find right now :(
Basically you tell coreboot to run the ROM, but comment out the execution right after the copy. Let me know if you can't find it, and I'll try to help you dig.
I found a post where Kevin talks about this but no patch.
I am thinking about this approach for 440BX: set PAM registers to "read from ROM, write to RAM" mode, copy the whole range onto itself, set PAM register to R/W RAM mode. I am not sure if this better be done for all legacy segments (0xC0000 - 0xFFFFF range) or only for option ROM segments (0xC0000 - 0xDFFFF range) excluding BIOS Area and BIOS Extension segments.
P.S. This approach won't work in stock qemu because of incorrect implementation (absence, actually) of emulation of this "mixed" PAM mode.
Andriy Gapon wrote:
on 30/10/2008 16:52 Myles Watson said the following:
-----Original Message----- From: Andriy Gapon [mailto:avg@icyb.net.ua] Sent: Thursday, October 30, 2008 8:43 AM To: Myles Watson Cc: 'Coreboot' Subject: Re: [coreboot] coreboot.v2+seabios on 440bx: option roms not found
on 30/10/2008 16:34 Myles Watson said the following:
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-
bounces@coreboot.org]
On Behalf Of Andriy Gapon Sent: Thursday, October 30, 2008 8:25 AM To: Coreboot Subject: [coreboot] coreboot.v2+seabios on 440bx: option roms not found
In northbridge/intel/i440bx/raminit.c:sdram_set_spd_registers all PAM registers are programmed for RAM R/W access (0x33). When SeaBIOS searches for option ROMs (including VGA ROM) it doesn't do anything about PAM, so it sees empty memory instead of the ROMs.
I am not sure what is the best solution here. It is debatable how coreboot should set PAM register, and it is not right to make SeaBIOS too hardware dependent.
Maybe coreboot could somehow export functions for setting access to option ROM space (aka legacy memory segments) and SeaBIOS could call
them.
I think SeaBIOS expects Coreboot to copy the option ROM to 0xc0000 in
RAM.
That way SeaBIOS gets to stay hardware agnostic.
Makes sense! But it doesn't look like this does actually happen (by default). I am playing with msi/ms6147 target (under heavily tweaked qemu).
You're right. It doesn't happen by default. Kevin sent a simple patch to the list, which I can't find right now :(
Basically you tell coreboot to run the ROM, but comment out the execution right after the copy. Let me know if you can't find it, and I'll try to help you dig.
I found a post where Kevin talks about this but no patch.
I am thinking about this approach for 440BX: set PAM registers to "read from ROM, write to RAM" mode, copy the whole range onto itself, set PAM register to R/W RAM mode. I am not sure if this better be done for all legacy segments (0xC0000 - 0xFFFFF range) or only for option ROM segments (0xC0000 - 0xDFFFF range) excluding BIOS Area and BIOS Extension segments.
P.S. This approach won't work in stock qemu because of incorrect implementation (absence, actually) of emulation of this "mixed" PAM mode.
I think PAM should be set for the entire space. That would be consistent with K8 and Geode. We don't scan the legacy space for ISA ROMs (and if we did and they were there we should copy them to memory and set the space).
Marc
Hi,
On Thu, Oct 30, 2008 at 04:24:41PM +0200, Andriy Gapon wrote:
In northbridge/intel/i440bx/raminit.c:sdram_set_spd_registers all PAM registers are programmed for RAM R/W access (0x33). When SeaBIOS searches for option ROMs (including VGA ROM) it doesn't do anything about PAM, so it sees empty memory instead of the ROMs.
I am not sure what is the best solution here. It is debatable how coreboot should set PAM register, and it is not right to make SeaBIOS too hardware dependent.
Maybe coreboot could somehow export functions for setting access to option ROM space (aka legacy memory segments) and SeaBIOS could call them.
Currently, SeaBIOS needs coreboot to copy the option roms to memory in order for SeaBIOS to run them.
I modified my copy of coreboot-v2 to do this (at least for epia-m/cn). I posted this change (along with other stuff) at:
http://www.coreboot.org/pipermail/coreboot/2008-September/038551.html
I'm planning on enhancing SeaBIOS so that it can scan all the PCI devices and copy the option roms from the card to memory. For built-in vga devices on coreboot-v2, I'll add support for hardcoding the rom address for an option rom. Finally, I'd eventually like to add simple lar support so that SeaBIOS can pull option roms out of the lar on coreboot-v3.
PCI option rom copying looks to be straight forward and not too system specific. Unfortunately, I don't have any PCI devices with option roms handy, so I'll need some help to test it.
-Kevin
Kevin O'Connor wrote:
I'd eventually like to add simple lar support so that SeaBIOS can pull option roms out of the lar on coreboot-v3.
There's some lar code in libpayload that you could use for this.
//Peter
-
Andriy Gapon -
Kevin O'Connor -
Marc Jones -
Myles Watson -
Peter Stuge