coreboot November 2008

coreboot@coreboot.org

76 participants
490 discussions

Re: [coreboot] Coreboot on Tyan S2892
by Myles Watson 07 Nov '08

07 Nov '08

On Fri, Nov 7, 2008 at 12:17 PM, Anose, Bijoy K (N-Aerotek) < bijoy.k.anose(a)lmco.com> wrote: > Hello Myles, > > According to a mailing list post ( > http://article.gmane.org/gmane.linux.bios/18159/match=s2892) you were the > author of > the 2892 tutorial on the coreboot website. Sorry to bother you directly, > but you did say "feel free to ask for clarifications", > so I'm taking you at your word. :) > No problem. If you CC the list you could get a faster response sometimes, depending on the time of day, phases of the moon, etc. > I've been looking at the tutorial, and I'm a bit confused. It's probably > just my ignorance of how coreboot works, etc. > As I understand it, I should be able to replace the legacy bios on my > S2892-based system with a coreboot-generated > ROM image. I want to be able to boot from a SATA hard drive with an > existing Linux install. > > So far, I've taken the latest SVN snapshots of coreboot-v2, filo, and > buildrom. Hardware-wise, I have a contraption that > lets me hot swap the bios chip, and a couple of spare chips. I've already > successfully read an image file from the legacy > BIOS and written it back and verified it a few times. > > I'm pretty familiar with the Linux boot process, on top of a legacy BIOS > anyway. I created an isolinux-based system > that just worked out of the ramdisk and never mounted a hard disk. > > I believe the steps I want to follow are roughly the following: > * build a very minimal kernel that will end up in the ROM image > Buildrom does this. > * configure and build FILO (filo.elf will include the kernel image?) > Not needed. Filo doesn't have SATA drivers. That's why you need a kernel in the ROM. You will have to configure the shell and the boot scripts in buildrom/buildrom-devel/skeleton/ They select the defaults, mount the drives, etc. > * use buildrom to create the actual ROM image file (superset of filo.elf?) > Use buildrom, but the file only will have coreboot and the kernel with a minimal shell > * burn image to the chip using flashrom > Yes. > Is the documentation directory under coreboot-v2 the answer to all of my > questions, even though it seems to be intended > for an EPIA board? It seems to be the "general" part of the steps I would > need, with your S2892 tutorial just calling out > the additional/divergent steps specific to the S2892. > I think my tutorial was additional to another tutorial on the wiki, not the docs. The Tyan boards are very similar. Good luck. Myles

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Subtractive Resources
by Myles Watson 07 Nov '08

07 Nov '08

I'm running into a problem when resources are read. The amd8111 adds two subtractive resources on link 0. The problem is that it has no link 0. static void amd8111_lpc_read_resources(struct device * dev) { struct resource *res; printk(BIOS_DEBUG,"%s calls read_resources with %s bus %s \n", __func__, dev->dtsname, dev->bus? dev->bus->dev->dtsname: "NULL"); /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* Add an extra subtractive resource for both memory and I/O */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; printk(BIOS_DEBUG,"%s after read_resources\n", __func__); } Either of these changes fix it, but I'd like a little more understanding of why we're trying to do this. I like the first change better because it quits trying sooner. Index: device/device.c =================================================================== --- device/device.c (revision 984) +++ device/device.c (working copy) @@ -311,7 +311,7 @@ /* Read in subtractive resources behind the current device. */ links = 0; - for (i = 0; i < curdev->resources; i++) { + for (i = 0; i < curdev->resources && curdev->links>0; i++) { struct resource *resource; unsigned int link; resource = &curdev->resource[i]; @@ -326,7 +326,8 @@ } if (!(links & (1 << link))) { links |= (1 << link); - read_resources(&curdev->link[link]); + if (curdev->link[link].dev) + read_resources(&curdev->link[link]); } } } Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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[PATCH 0/6] Support for i945 + ICH7 + Kontron 986LCD-M
by Stefan Reinauer 07 Nov '08

07 Nov '08

Hi, I am glad to announce the release of the work we did in the last couple of months writing support for a somewhat modern Intel Desktop/Mobile chipset running with the Core Duo/Core 2 Duo: The i945 + ICH7. The support package has been split in 6 different smaller patches: 1_superio_winbond_w83627thg.diff: Implement support for the Winbond W83627THG. 2_southbridge_intel_i82801gx.diff: Support for the Intel ICH7 southbridge. 3_cpu_core_duo.diff: Support for Intel Core Duo and Core 2 Duo (tm) CPUs. 4_northbridge_intel_i945.diff: Support for the Intel 945 northbridge. 5_device_allocator.diff: Changes required to the device allocator 6_mainboard_kontron_986lcd_m.diff: Support for the Kontron 986LCD-M mainboard series. At this point I would like to say thank you to Intel Corporation for doing all they could to make this possible. I also want to cordially thank everyone else helping in the one way or the other to make this happen. Best regards, Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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r987 - coreboot-v3/mainboard/artecgroup/dbe61
by svn＠coreboot.org 07 Nov '08

07 Nov '08

Author: mraudsepp Date: 2008-11-07 17:33:57 +0100 (Fri, 07 Nov 2008) New Revision: 987 Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c Log: Working fake SPD for DBE61C Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-11-07 00:51:38 UTC (rev 986) +++ coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-11-07 16:33:57 UTC (rev 987) @@ -38,32 +38,40 @@ #define DIMM0 ((u8) 0xA0) #define DIMM1 ((u8) 0xA2) -/* The part is a Hynix hy5du121622ctp-d43. - * - * HY 5D U 12 16 2 2 C <blank> T <blank> P D43 - * Hynix - * DDR SDRAM (5D) - * VDD 2.5 VDDQ 2.5 (U) - * 512M 8K REFRESH (12) - * x16 (16) - * 4banks (2) - * SSTL_2 (2) - * 4th GEN die (C) - * Normal Power Consumption (<blank> ) - * TSOP (T) - * Single Die (<blank>) - * Lead Free (P) - * DDR400 3-3-3 (D43) - */ - struct spd_entry { u8 address; u8 data; }; /* Save space by using a short list of SPD values used by Geode LX Memory init */ +/* Fake SPD for DBE61C - 256MB. Same memory chip, and therefore same SPD entries, as for DBE62. */ +/* Micron MT46V32M16 */ static const struct spd_entry spd_table[] = { + {SPD_MEMORY_TYPE, 7}, + {SPD_NUM_ROWS, 13}, + {SPD_tRFC, 0x4b}, {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, + {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x40}, + {SPD_tRAS, 0x2d}, + {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x7}, /*0x <= 7},*/ + {SPD_MIN_RAS_TO_CAS_DELAY, 0x58}, + {SPD_tRRD, 0x3c}, + {SPD_tRP, 0x58}, + {SPD_PRIMARY_SDRAM_WIDTH, 8}, + {SPD_NUM_BANKS_PER_SDRAM, 0x4}, + {SPD_NUM_COLUMNS, 0xa}, /* 8kB */ + {SPD_NUM_DIMM_BANKS, 0x1}, + {SPD_REFRESH, 0x82}, + {SPD_SDRAM_CYCLE_TIME_2ND, 0x0}, + {SPD_SDRAM_CYCLE_TIME_3RD, 0x0}, + {SPD_tRCD, 15}, +}; + +#if 0 +/* Fake SPD for DBE61A - 128MB. Not working yet */ +/* Micron MT46V16M16 */ +static const struct spd_entry spd_table_dbe61a[] = { + {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, {SPD_BANK_DENSITY, 0x40}, {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, {SPD_MEMORY_TYPE, 7}, @@ -83,6 +91,7 @@ {SPD_tRP, 15}, {SPD_tRRD, 10}, }; +#endif /** * Given an SMBUS device, and an address in that device, return the value of SPD

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[RFC] Null pointer trap?
by Carl-Daniel Hailfinger 07 Nov '08

07 Nov '08

v3 does not have any mechanism to detect NULL pointers used by accident. I propose to fill the zero page (0x0-0xfff) with a special POISON_BYTE, maybe 0x6b. Furthermore, I'd like to make sure passing a NULL pointer (or something near it) to as a string to printk will be very visible in the logs. *(char *)0 = "ERROR NULL POINTER DEREFERENCE!\n"; The C statement above would cause a nice print everytime someone referenced the first 32 bytes in %s. Another way to do this is extending the non-NULL check in printk to cover the whole zero page. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH] Working fake SPD for DBE61C
by Mart Raudsepp 07 Nov '08

07 Nov '08

Working fake SPD for DBE61C Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- mainboard/artecgroup/dbe61/initram.c | 45 ++++++++++++++++++++------------- 1 files changed, 27 insertions(+), 18 deletions(-) diff --git a/mainboard/artecgroup/dbe61/initram.c b/mainboard/artecgroup/dbe61/initram.c index 393d575..8c84792 100644 --- a/mainboard/artecgroup/dbe61/initram.c +++ b/mainboard/artecgroup/dbe61/initram.c @@ -38,31 +38,39 @@ #define DIMM0 ((u8) 0xA0) #define DIMM1 ((u8) 0xA2) -/* The part is a Hynix hy5du121622ctp-d43. - * - * HY 5D U 12 16 2 2 C <blank> T <blank> P D43 - * Hynix - * DDR SDRAM (5D) - * VDD 2.5 VDDQ 2.5 (U) - * 512M 8K REFRESH (12) - * x16 (16) - * 4banks (2) - * SSTL_2 (2) - * 4th GEN die (C) - * Normal Power Consumption (<blank> ) - * TSOP (T) - * Single Die (<blank>) - * Lead Free (P) - * DDR400 3-3-3 (D43) - */ - struct spd_entry { u8 address; u8 data; }; /* Save space by using a short list of SPD values used by Geode LX Memory init */ +/* Fake SPD for DBE61C - 256MB. Same memory chip, and therefore same SPD entries, as for DBE62. */ +/* Micron MT46V32M16 */ static const struct spd_entry spd_table[] = { + {SPD_MEMORY_TYPE, 7}, + {SPD_NUM_ROWS, 13}, + {SPD_tRFC, 0x4b}, + {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, + {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x40}, + {SPD_tRAS, 0x2d}, + {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x7}, /*0x <= 7},*/ + {SPD_MIN_RAS_TO_CAS_DELAY, 0x58}, + {SPD_tRRD, 0x3c}, + {SPD_tRP, 0x58}, + {SPD_PRIMARY_SDRAM_WIDTH, 8}, + {SPD_NUM_BANKS_PER_SDRAM, 0x4}, + {SPD_NUM_COLUMNS, 0xa}, /* 8kB */ + {SPD_NUM_DIMM_BANKS, 0x1}, + {SPD_REFRESH, 0x82}, + {SPD_SDRAM_CYCLE_TIME_2ND, 0x0}, + {SPD_SDRAM_CYCLE_TIME_3RD, 0x0}, + {SPD_tRCD, 15}, +}; + +#if 0 +/* Fake SPD for DBE61A - 128MB. Not working yet */ +/* Micron MT46V16M16 */ +static const struct spd_entry spd_table_dbe61a[] = { {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, {SPD_BANK_DENSITY, 0x40}, {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, @@ -83,6 +91,7 @@ static const struct spd_entry spd_table[] = { {SPD_tRP, 15}, {SPD_tRRD, 10}, }; +#endif /** * Given an SMBUS device, and an address in that device, return the value of SPD -- 1.6.0.2

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Dell PE2850 with coreboot.
by Michal Widlok 07 Nov '08

07 Nov '08

Hello, I'm new to this lis and to coreboot, so please forgive me dumb questions for a while :-). I would like to learn some more about it and maybe install it on my Dell 2850. I've red then there is a WIP for coreboot on dell 1850 - this one is similar to mine. Where can I get some more information about this work? Is there any tutorial or other info that explains how to install coreboot on dells? Best Regards, Michael W.

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[patch] add required info to not-matched vendor/device id
by Elia Yehuda 07 Nov '08

07 Nov '08

Signed-off-by: Elia Yehuda <z4ziggy(a)gmail.com> Index: src/devices/pci_rom.c =================================================================== --- src/devices/pci_rom.c (revision 3698) +++ src/devices/pci_rom.c (working copy) @@ -67,8 +67,10 @@ printk_spew("PCI ROM Image, Vendor %04x, Device %04x,\n", rom_data->vendor, rom_data->device); if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) { - printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x\n", - rom_data->vendor, rom_data->device); + printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x " + "(Vendor %04x, Device %04x)\n", + rom_data->vendor, rom_data->device, + dev->vendor, dev->device); return NULL; }

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Fwd: fixing i810 onboard vga
by Elia Yehuda 07 Nov '08

07 Nov '08

---------- Forwarded message ---------- From: Elia Yehuda <z4ziggy(a)gmail.com> Date: Fri, Nov 7, 2008 at 3:19 AM Subject: Re: [coreboot] fixing i810 onboard vga To: Joseph Smith <joe(a)settoplinux.org> many thanks Joseph! you sure have found the problem in the code (without even looking... remarkable). i sure had the "CONFIG_VIDEO_MB=8" to my targets' Config.lb which was being ignored... so i've added the following (elementary) patch to coreboot-v2/src/northbridge/intel/i82810/northbridge.c : Index: northbridge.c =================================================================== --- northbridge.c (revision 3698) +++ northbridge.c (working copy) @@ -149,6 +149,16 @@ drp_value = drp_value >> 4; // >>= 4; //? mess with later tomk += (unsigned long)(translate_i82810_to_mb[drp_value]); +#ifdef CONFIG_VIDEO_MB + /* check for VGA reserved memory */ + if (CONFIG_VIDEO_MB == 512) { + /* FIXME: we round up the 1/2mb to 1 */ + tomk -= 1; + } else { + tomk -= CONFIG_VIDEO_MB; + } +#endif + printk_debug("Setting RAM size to %d MB\n", tomk); /* Convert tomk from MB to KB. */ the boot now works, but still no onboard-vga. ive noticed in pci_rom_probe() the dev->rom_address of the vga pci card is 0 (zero)! although i have the following in the mainboard/manu/type/Config.lb : ... device pci 1.0 on # Onboard video chip drivers/pci/onboard device pci 1.0 on end register "rom_address" = "0xfffc0000" end end ... this is according to the lspci output from the machine using the original bios : ... 00:01.0 VGA compatible controller: Intel Corporation 82810E DC-133 (CGC) Chipset Graphics Controller (rev 03) ... so im trying to find out why dev->rom_address is being set to 0. the fallback/static.c shows clearly that the rom address is being set in the proper device structure : ... struct drivers_pci_onboard_config drivers_pci_onboard_info_9 = { .rom_address = 0xfffc0000, }; ... so any clues on the matter will be appreciated. Regards, Elia Yehuda. On Fri, Nov 7, 2008 at 1:08 AM, Joseph Smith <joe(a)settoplinux.org> wrote: > > > > On Thu, 6 Nov 2008 20:38:31 +0200, "Elia Yehuda" <z4ziggy(a)gmail.com> > wrote: > > Hey all, > > > > im working at the on the i810, trying to fix the onboard-vga to work. > > > > removing the commented code of the vga-related stuff resulted with the > pci > > device to be displayed in the pci list on coreboot, but in a disabled > > state, > > and (as promised...) with the boot not executing the payload. complete > log > > can be shown here : http://pastebin.com/m20e821eb > > > > a few rough patches to my target and i82810/raminit.c and now the device > > is > > shown as enabled and i even get the information about the VGA allocating > > resources : > > > > Allocating VGA resource PCI: 00:01.0 > > Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 > > Setting PCI_BRIDGE_CTL_VGA for bridge Root Device > > > > but the payload still wont execute (it is seems to be loaded though) and > > ofcourse, no VGA output, only serial, with a dead boot hanging... > > complete log can be shown here : http://pastebin.com/m248a41ea > > > I had this problem on the i830. You need to allocate vga memory for the > onboard vga (northbridge.c if I remember correctly). The vga memory should > be allocated to the TOM. So your total system memory actually equals > phisical memory - vga memory. It should be close to the i830, take a look > at that and compare it to the i810 datasheet. Hope that helps. > > -- > Thanks, > Joseph Smith > Set-Top-Linux > www.settoplinux.org > >

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[PATCH] v3: s/BIOS_DEBUG/DEBUG/ etc. for printk()
by Uwe Hermann 07 Nov '08

07 Nov '08

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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coreboot November 2008