coreboot November 2008

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490 discussions

r3733 - trunk/coreboot-v2/src/southbridge/intel/i82801gx
by svn＠coreboot.org 06 Nov '08

06 Nov '08

Author: uwe Date: 2008-11-06 23:24:05 +0100 (Thu, 06 Nov 2008) New Revision: 3733 Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx.h Log: Drop #defines for registers that are not existant on the ICH7. Also, fix BIOS_CNTL, which is 0xdc on ICH7. Build-tested with kontron/986lcd-m. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx.h =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx.h 2008-11-06 22:23:05 UTC (rev 3732) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx.h 2008-11-06 22:24:05 UTC (rev 3733) @@ -24,18 +24,20 @@ #include "chip.h" extern void i82801gx_enable(device_t dev); -#define PCI_DMA_CFG 0x90 #define SERIRQ_CNTL 0x64 -#define GEN_CNTL 0xd0 -#define GEN_STS 0xd4 -#define RTC_CONF 0xd8 + #define GEN_PMCON_1 0xa0 #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 +/* GEN_PMCON_3 bits */ +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + #define PMBASE 0x40 #define ACPI_CNTL 0x44 -#define BIOS_CNTL 0x4E +#define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ @@ -48,28 +50,10 @@ #define PIRQG_ROUT 0x6A #define PIRQH_ROUT 0x6B -#define FUNC_DIS 0xF2 - #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ #define LPC_EN 0x82 /* LPC IF Enables Register */ -#define SBUS_NUM 0x19 -#define SUB_BUS_NUM 0x1A -#define SMLT 0x1B -#define IOBASE 0x1C -#define IOLIM 0x1D -#define MEMBASE 0x20 -#define MEMLIM 0x22 -#define CNF 0x50 -#define MTT 0x70 -#define PCI_MAST_STS 0x82 - -/* GEN_PMCON_3 bits */ -#define RTC_BATTERY_DEAD (1 << 2) -#define RTC_POWER_FAILED (1 << 1) -#define SLEEP_AFTER_POWER_FAIL (1 << 0) - -/* PCI Configuration Space (D31:F1) */ +/* PCI Configuration Space (D31:F1): IDE */ #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_DECODE_ENABLE (1 << 15) @@ -84,7 +68,7 @@ #define PCB1 (1 << 1) #define PCB0 (1 << 0) -/* PCI Configuration Space (D31:F3) */ +/* PCI Configuration Space (D31:F3): SMBus */ #define SMB_BASE 0x20 #define HOSTC 0x40

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[PATCH] v2: ICH7: Drop non-working enable_hpet() for now
by Uwe Hermann 06 Nov '08

06 Nov '08

Please correct me if I'm wrong (I don't have NDA'd Intel datasheets, I can only check the public ones), but I think the enable_hpet() in the ICH7 code will not work for ICH7. It should work for ICH4/ICH5 or so, but ICH7 requires a completely different init involving RCBA, offset 0x3404, it seems. Thus, drop the non-working code, add a TODO until somebody writes the proper code for ICH7. Maybe I'll do that if nobody beats me to it, but it may take a while. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

r3732 - trunk/coreboot-v2/src/southbridge/intel/i82801gx
by svn＠coreboot.org 06 Nov '08

06 Nov '08

Author: uwe Date: 2008-11-06 23:23:05 +0100 (Thu, 06 Nov 2008) New Revision: 3732 Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c Log: The enable_hpet() code in intel/i82801gx will not work with the ICH7 southbridge (but it might work with ICH4/ICH5 or so). The ICH7 needs a different init code. Drop the non-working code for now. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2008-11-05 22:54:36 UTC (rev 3731) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2008-11-06 22:23:05 UTC (rev 3732) @@ -194,22 +194,7 @@ static void enable_hpet(struct device *dev) { - u32 reg32; - u32 code = (0 & 0x3); - - reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (1 << 17); /* Enable HPET. */ - /* - * Bits [16:15] Memory Address Range - * 00 FED0_0000h - FED0_03FFh - * 01 FED0_1000h - FED0_13FFh - * 10 FED0_2000h - FED0_23FFh - * 11 FED0_3000h - FED0_33FFh - */ - reg32 &= ~(3 << 15); /* Clear it */ - reg32 |= (code << 15); - /* TODO: reg32 is never written to anywhere? */ - printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); + /* TODO */ } static void i82801gx_lock_smm(struct device *dev)

1 0

[PATCH] v3: Kill unnecessary rebuilds
by Carl-Daniel Hailfinger 06 Nov '08

06 Nov '08

Every time we run make in a v3 tree, lar, lzma, nrv2b and the option table get rebuilt unconditionally due to slightly incorrect dependencies. That's wasteful and may hide other dependency bugs. Fix the lar, lzma, nrv2b and option table dependencies. This trims down recompilation time a lot. The only remaining stuff being rebuilt is: ~/corebootv3-better_dependencies> make CP build/config.h GEN build/build.h LAR build/coreboot.rom PAYLOAD none (as specified by user) CP build/bios.bin DONE Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-better_dependencies/util/lzma/Makefile =================================================================== --- corebootv3-better_dependencies/util/lzma/Makefile (Revision 983) +++ corebootv3-better_dependencies/util/lzma/Makefile (Arbeitskopie) @@ -23,13 +23,13 @@ LZMA_OBJ += $(obj)/util/lzma/OutBuffer.o $(obj)/util/lzma/Alloc.o LZMA_OBJ += $(obj)/util/lzma/CRC.o -$(obj)/util/lzma/lzma: lzmadir $(LZMA_OBJ) $(obj)/util/lzma/minilzma.o +$(obj)/util/lzma/lzma: $(obj)/util/lzma/ $(LZMA_OBJ) $(obj)/util/lzma/minilzma.o $(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ $(LZMA_OBJ) $(obj)/util/lzma/minilzma.o $(obj)/util/lzma/lzma-compress.o: $(src)/util/lzma/minilzma.cc $(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c -DCOMPACT $< -lzmadir: +$(obj)/util/lzma/: $(Q)printf " BUILD LZMA\n" $(Q)mkdir -p $(obj)/util/lzma/ Index: corebootv3-better_dependencies/util/nrv2b/Makefile =================================================================== --- corebootv3-better_dependencies/util/nrv2b/Makefile (Revision 983) +++ corebootv3-better_dependencies/util/nrv2b/Makefile (Arbeitskopie) @@ -19,15 +19,15 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -$(obj)/util/nrv2b/nrv2b: nrv2bdir $(src)/util/nrv2b/nrv2b.c +$(obj)/util/nrv2b/nrv2b: $(obj)/util/nrv2b/ $(src)/util/nrv2b/nrv2b.c $(Q)printf " HOSTCC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(HOSTCC) $(HOSTCFLAGS) -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32 -DENDIAN=0 -o $@ $(src)/util/nrv2b/nrv2b.c -$(obj)/util/nrv2b/nrv2b-compress.o: nrv2bdir $(src)/util/nrv2b/nrv2b.c +$(obj)/util/nrv2b/nrv2b-compress.o: $(obj)/util/nrv2b/ $(src)/util/nrv2b/nrv2b.c $(Q)printf " HOSTCC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(HOSTCC) $(HOSTCFLAGS) -DENCODE -DDECODE -DVERBOSE -DCOMPACT -DNDEBUG -DBITSIZE=32 -DENDIAN=0 -c -o $@ $(src)/util/nrv2b/nrv2b.c -nrv2bdir: +$(obj)/util/nrv2b/: $(Q)printf " BUILD NRV2B\n" $(Q)mkdir -p $(obj)/util/nrv2b/ Index: corebootv3-better_dependencies/util/options/Makefile =================================================================== --- corebootv3-better_dependencies/util/options/Makefile (Revision 983) +++ corebootv3-better_dependencies/util/options/Makefile (Arbeitskopie) @@ -21,11 +21,11 @@ OPTIONS_OBJ := $(obj)/util/options/build_opt_tbl.o -$(obj)/util/options/build_opt_tbl: optionsdir $(OPTIONS_OBJ) +$(obj)/util/options/build_opt_tbl: $(obj)/util/options/ $(OPTIONS_OBJ) $(Q)printf " HOSTCC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(HOSTCC) $(HOSTCFLAGS) -o $@ $(OPTIONS_OBJ) -optionsdir: +$(obj)/util/options/: $(Q)mkdir -p $(obj)/util/options/ $(obj)/util/options/%.o: $(src)/util/options/%.c Index: corebootv3-better_dependencies/util/lar/Makefile =================================================================== --- corebootv3-better_dependencies/util/lar/Makefile (Revision 983) +++ corebootv3-better_dependencies/util/lar/Makefile (Arbeitskopie) @@ -19,16 +19,17 @@ ## LAROBJ := lar.o stream.o lib.o -LARDIR := lardir +LARDIR := $(obj)/util/lar COMPRESSOR := $(LZMA_OBJ) $(obj)/util/lzma/lzma-compress.o -LARDIR += lzmadir +LARDIR += $(obj)/util/lzma/ COMPRESSOR += $(obj)/util/nrv2b/nrv2b-compress.o -LARDIR += nrv2bdir +LARDIR += $(obj)/util/nrv2b/ LAROBJ_ABS := $(patsubst %,$(obj)/util/lar/%,$(LAROBJ)) -lardir: + +$(obj)/util/lar: $(Q)printf " BUILD LAR\n" $(Q)mkdir -p $(obj)/util/lar -- http://www.hailfinger.org/

4 7

Supporting boards with NAND flash on other chip selects than CS0
by Mart Raudsepp 06 Nov '08

06 Nov '08

Hello, Currently southbridge/amd/cs5536/cs5536.c:chipset_flash_setup() sets up NAND flash if enable_ide_nand_flash is set to "1" in the device tree based on a static const structure in the same file - FlashInitTable. The code itself supports having different NAND interfaces, specify extra NOR for the setup and so on, based on the struct values. However in practice this can't be used, because the struct is defined in the southbridge code, and can't be overriden by board specific dts files through any means - effectively telling things like "This board has NAND on CS1" is not possible. Due to that the ArtecGroup ThinCan DBE61 and DBE62 do not set up NAND flash properly in coreboot-v3. They could have (and DBE62 does) enable_ide_nand_flash enabled in dts, but that enables it on CS0, and not on CS1. I don't know how it's best to solve this. I think the most generic way would be to make the whole 4 member array struct definable or overridable in dts, but I don't think our dtc code supports anything like that - at best we could have a variable length array (cells) that is used for unwanted_vpci as well, telling that it has to come in three member chunks, where first tells the type, second the interface and third the (page size?) mask. But that is very suboptimal too - a zero would terminate the array immediately, the type is really an enum, not a 4 byte cell, etc. Another option is to just assume there is only one NAND to enable, and give the chip select location in dts - this doesn't regress what is in practice currently supported, while being the minimum necessary to setup up NAND for ThinCan boards properly. An initial patch for that is attached. Or maybe the call to chipset_flash_setup() should be pushed down to be the responsibility of board specific C code, so it could pass in its own FlashInitTable, after chipset_flash_setup is modified to take such a struct instead of using the file global const struct defined in the southbridge file? Thoughts? Mart Raudsepp Artec Design LLC

3 4

r985 - in coreboot-v3: mainboard/artecgroup/dbe62 southbridge/amd/cs5536
by svn＠coreboot.org 06 Nov '08

06 Nov '08

Author: mraudsepp Date: 2008-11-06 18:52:52 +0100 (Thu, 06 Nov 2008) New Revision: 985 Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts coreboot-v3/southbridge/amd/cs5536/cs5536.c coreboot-v3/southbridge/amd/cs5536/dts Log: cs5536: Support NAND flash on other locations than CS0 Modify chipset_flash_setup to support enabling NAND flash on other locations than CS0, by making enable_ide_nand_flash have a non-boolean meaning where zero means no NAND (IDE), and 1 through 4 gives the one-based chip select array location (so 1 means CS0, 2 means CS1, 3 means CS2 and 4 means CS3, as chip select notation is zero-based). This loses the code for supporting more than one NAND chip select or different ones than FLASH_MEM_4K, but these couldn't be supported before anyway, because that is board specific, but the supporting structure was a static const struct in generic southbridge specific code. This support should be instead implemented via the device tree dts files. Enables NAND on ArtecGroup DBE61 and DBE62 on CS1, as that's where it is. The end result is that these mainboards can now boot off of NAND with FILO without local modifications to the previously existing southbridge specific static const struct that had no chance of being upstreamed as it would break all other CS5536 NAND boards that have it on CS0. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-11-06 13:59:14 UTC (rev 984) +++ coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-11-06 17:52:52 UTC (rev 985) @@ -44,8 +44,8 @@ /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. * See virtual PIC spec. */ enable_gpio_int_route = "0x0D0C0700"; - /* 0:IDE 1:FLASH */ - enable_ide_nand_flash = "1"; + /* 0:IDE; 1:FLASH on CS0, 2:FLASH on CS1, 3:FLASH on CS2, 4:FLASH on CS3. */ + enable_ide_nand_flash = "2"; /* we use com2 since that is on the dongle */ com2_enable = "1"; /* Set com2 address to be COM1 */ Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-11-06 13:59:14 UTC (rev 984) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-11-06 17:52:52 UTC (rev 985) @@ -68,19 +68,6 @@ {0, 0} }; -struct FLASH_DEVICE { - unsigned char fType; /* Flash type: NOR or NAND */ - unsigned char fInterface; /* Flash interface: I/O or memory */ - unsigned long fMask; /* Flash size/mask */ -}; - -static const struct FLASH_DEVICE FlashInitTable[] = { - {FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K}, /* CS0, or Flash Device 0 */ - {FLASH_TYPE_NONE, 0, 0}, /* CS1, or Flash Device 1 */ - {FLASH_TYPE_NONE, 0, 0}, /* CS2, or Flash Device 2 */ - {FLASH_TYPE_NONE, 0, 0}, /* CS3, or Flash Device 3 */ -}; - static const u32 FlashPort[] = { MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, @@ -154,38 +141,31 @@ * correct size info. Call this routine only if flash needs to be * configured (don't call it if you want IDE). */ -static void chipset_flash_setup(void) +static void chipset_flash_setup(struct southbridge_amd_cs5536_dts_config *sb) { int i; struct msr msr; printk(BIOS_DEBUG, "chipset_flash_setup: Start\n"); - for (i = 0; i < ARRAY_SIZE(FlashInitTable); i++) { - if (FlashInitTable[i].fType != FLASH_TYPE_NONE) { - printk(BIOS_DEBUG, "Enable CS%d\n", i); - /* We need to configure the memory/IO mask. */ - msr = rdmsr(FlashPort[i]); - msr.hi = 0; /* Start with "enabled" bit clear. */ - if (FlashInitTable[i].fType == FLASH_TYPE_NAND) - msr.hi |= 0x00000002; - else - msr.hi &= ~0x00000002; - if (FlashInitTable[i].fInterface == FLASH_IF_MEM) - msr.hi |= 0x00000004; - else - msr.hi &= ~0x00000004; - msr.hi |= FlashInitTable[i].fMask; - printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", - FlashPort[i], msr.hi, msr.lo); - wrmsr(FlashPort[i], msr); + if (sb->enable_ide_nand_flash <= 4) { + i = sb->enable_ide_nand_flash - 1; + printk(BIOS_DEBUG, "Enable CS%d\n", i); + /* We need to configure the memory/IO mask. */ + msr = rdmsr(FlashPort[i]); + msr.hi = 0; /* Start with "enabled" bit clear. */ + msr.hi |= 0x00000002; /* For FLASH_TYPE_NAND */ + msr.hi |= 0x00000004; /* For FLASH_IF_MEM */ + msr.hi |= FLASH_MEM_4K; + printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", + FlashPort[i], msr.hi, msr.lo); + wrmsr(FlashPort[i], msr); - /* Now write-enable the device. */ - msr = rdmsr(MDD_NORF_CNTRL); - msr.lo |= (1 << i); - printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", - MDD_NORF_CNTRL, msr.hi, msr.lo); - wrmsr(MDD_NORF_CNTRL, msr); - } + /* Now write-enable the device. */ + msr = rdmsr(MDD_NORF_CNTRL); + msr.lo |= (1 << i); + printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", + MDD_NORF_CNTRL, msr.hi, msr.lo); + wrmsr(MDD_NORF_CNTRL, msr); } printk(BIOS_DEBUG, "chipset_flash_setup: Finish\n"); } @@ -596,9 +576,9 @@ /* Flash BAR size setup. */ printk(BIOS_ERR, "%sDoing chipset_flash_setup()\n", - sb->enable_ide_nand_flash == 1 ? "" : "Not "); - if (sb->enable_ide_nand_flash == 1) - chipset_flash_setup(); + sb->enable_ide_nand_flash != 0 ? "" : "Not "); + if (sb->enable_ide_nand_flash != 0) + chipset_flash_setup(sb); /* Set up hardware clock gating. */ /* TODO: Why the extra block here? Can it be removed? */ @@ -680,7 +660,7 @@ printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash); - if (sb->enable_ide_nand_flash == 1) + if (sb->enable_ide_nand_flash != 0) enable_ide_nand_flash_header(); enable_USB_port4(sb); Modified: coreboot-v3/southbridge/amd/cs5536/dts =================================================================== --- coreboot-v3/southbridge/amd/cs5536/dts 2008-11-06 13:59:14 UTC (rev 984) +++ coreboot-v3/southbridge/amd/cs5536/dts 2008-11-06 17:52:52 UTC (rev 985) @@ -33,7 +33,7 @@ /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual PIC spec. */ enable_gpio_int_route = "0"; - /* 0:IDE 1:FLASH, if you are using NAND flash instead of IDE drive. */ + /* 0:IDE; 1:FLASH on CS0, 2:FLASH on CS1, 3:FLASH on CS2, 4:FLASH on CS3. */ enable_ide_nand_flash = "0"; /* Enable USB Port 4 (0:host 1:device).

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HT Doc
by Myles Watson 06 Nov '08

06 Nov '08

Sorry it's rough. I'm really ready to clean up the #if statements in this code. This is for hypertransport.c, next is northbridge/amd/k8/*.c Thanks, Myles

2 2

Gigabyte GA-P965-S3 motherboard data and question.
by Sasha Medvedev 06 Nov '08

06 Nov '08

Hi, all. I found " You can help out Coreboot! " thread on ubuntu forums, in witch somebody "uid313" tell that the following info will be useful for you(in attachments): dmidecode.txt lspci-tvnn.txt irq_tables.c mptable.txt dmidecode-dump.txt lshw.txt superiotool-dV.txt. This is info of my GA-P965-S3 motherboard and system. I found, coreboot is a great project. So I'd like to investigate information in wiki and try to do something to bring coreboot on my system. I have a little skill in programming ( C/C++ and asm courses in the university). So I have some questions. 1)Is this hard to port code from i945 to i965P? Could we get support of i965P, for example, next year? I found in mail lists somebody try to work with i965PM chip-set. 2)Is there any method to boot bios image without flashing it to board? Or i need to bay another bios chip and experiment with it? I heard about lobos project, but can't found source code. 3)How can I help? I suppose I was useless as programmer, may be there is some howtos how to adopt existing part's code. Probably I can support developers with this motherboard, if it brings really result. Or it will be easier to change my platform(for example on amd)?

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r984 - in coreboot-v3/util: lar lzma nrv2b options
by svn＠coreboot.org 06 Nov '08

06 Nov '08

Author: hailfinger Date: 2008-11-06 14:59:14 +0100 (Thu, 06 Nov 2008) New Revision: 984 Modified: coreboot-v3/util/lar/Makefile coreboot-v3/util/lzma/Makefile coreboot-v3/util/nrv2b/Makefile coreboot-v3/util/options/Makefile Log: Every time we run make in a v3 tree, lar, lzma, nrv2b and the option table get rebuilt unconditionally due to slightly incorrect dependencies. That's wasteful and may hide other dependency bugs. Fix the lar, lzma, nrv2b and option table dependencies. This trims down recompilation time a lot. The only remaining stuff being rebuilt is: ~/corebootv3-better_dependencies> make CP build/config.h GEN build/build.h LAR build/coreboot.rom PAYLOAD none (as specified by user) CP build/bios.bin DONE Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/util/lar/Makefile =================================================================== --- coreboot-v3/util/lar/Makefile 2008-11-05 22:27:36 UTC (rev 983) +++ coreboot-v3/util/lar/Makefile 2008-11-06 13:59:14 UTC (rev 984) @@ -19,16 +19,17 @@ ## LAROBJ := lar.o stream.o lib.o -LARDIR := lardir +LARDIR := $(obj)/util/lar/ COMPRESSOR := $(LZMA_OBJ) $(obj)/util/lzma/lzma-compress.o -LARDIR += lzmadir +LARDIR += $(obj)/util/lzma/ COMPRESSOR += $(obj)/util/nrv2b/nrv2b-compress.o -LARDIR += nrv2bdir +LARDIR += $(obj)/util/nrv2b/ LAROBJ_ABS := $(patsubst %,$(obj)/util/lar/%,$(LAROBJ)) -lardir: + +$(obj)/util/lar/: $(Q)printf " BUILD LAR\n" $(Q)mkdir -p $(obj)/util/lar Modified: coreboot-v3/util/lzma/Makefile =================================================================== --- coreboot-v3/util/lzma/Makefile 2008-11-05 22:27:36 UTC (rev 983) +++ coreboot-v3/util/lzma/Makefile 2008-11-06 13:59:14 UTC (rev 984) @@ -23,13 +23,13 @@ LZMA_OBJ += $(obj)/util/lzma/OutBuffer.o $(obj)/util/lzma/Alloc.o LZMA_OBJ += $(obj)/util/lzma/CRC.o -$(obj)/util/lzma/lzma: lzmadir $(LZMA_OBJ) $(obj)/util/lzma/minilzma.o +$(obj)/util/lzma/lzma: $(obj)/util/lzma/ $(LZMA_OBJ) $(obj)/util/lzma/minilzma.o $(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ $(LZMA_OBJ) $(obj)/util/lzma/minilzma.o $(obj)/util/lzma/lzma-compress.o: $(src)/util/lzma/minilzma.cc $(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c -DCOMPACT $< -lzmadir: +$(obj)/util/lzma/: $(Q)printf " BUILD LZMA\n" $(Q)mkdir -p $(obj)/util/lzma/ Modified: coreboot-v3/util/nrv2b/Makefile =================================================================== --- coreboot-v3/util/nrv2b/Makefile 2008-11-05 22:27:36 UTC (rev 983) +++ coreboot-v3/util/nrv2b/Makefile 2008-11-06 13:59:14 UTC (rev 984) @@ -19,15 +19,15 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -$(obj)/util/nrv2b/nrv2b: nrv2bdir $(src)/util/nrv2b/nrv2b.c +$(obj)/util/nrv2b/nrv2b: $(obj)/util/nrv2b/ $(src)/util/nrv2b/nrv2b.c $(Q)printf " HOSTCC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(HOSTCC) $(HOSTCFLAGS) -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32 -DENDIAN=0 -o $@ $(src)/util/nrv2b/nrv2b.c -$(obj)/util/nrv2b/nrv2b-compress.o: nrv2bdir $(src)/util/nrv2b/nrv2b.c +$(obj)/util/nrv2b/nrv2b-compress.o: $(obj)/util/nrv2b/ $(src)/util/nrv2b/nrv2b.c $(Q)printf " HOSTCC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(HOSTCC) $(HOSTCFLAGS) -DENCODE -DDECODE -DVERBOSE -DCOMPACT -DNDEBUG -DBITSIZE=32 -DENDIAN=0 -c -o $@ $(src)/util/nrv2b/nrv2b.c -nrv2bdir: +$(obj)/util/nrv2b/: $(Q)printf " BUILD NRV2B\n" $(Q)mkdir -p $(obj)/util/nrv2b/ Modified: coreboot-v3/util/options/Makefile =================================================================== --- coreboot-v3/util/options/Makefile 2008-11-05 22:27:36 UTC (rev 983) +++ coreboot-v3/util/options/Makefile 2008-11-06 13:59:14 UTC (rev 984) @@ -21,11 +21,11 @@ OPTIONS_OBJ := $(obj)/util/options/build_opt_tbl.o -$(obj)/util/options/build_opt_tbl: optionsdir $(OPTIONS_OBJ) +$(obj)/util/options/build_opt_tbl: $(obj)/util/options/ $(OPTIONS_OBJ) $(Q)printf " HOSTCC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(HOSTCC) $(HOSTCFLAGS) -o $@ $(OPTIONS_OBJ) -optionsdir: +$(obj)/util/options/: $(Q)mkdir -p $(obj)/util/options/ $(obj)/util/options/%.o: $(src)/util/options/%.c

1 0

My spec from Ubuntu (dmi etc.)
by Anton Eklund 06 Nov '08

06 Nov '08

Here I send my spec from dmidecode and such others. Best Regards///Anton

1 0

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coreboot November 2008