coreboot November 2008

coreboot@coreboot.org

76 participants
490 discussions

Flashrom - verified mainboards
by Rogen, Mario 08 Nov '08

08 Nov '08

Hi... I just tested flashrom on a bunch of mainboards: SST49LF008A congatec conga-x852 SBC (http://www.congatec.com/single_news+M5e8f9751886.html). Read, write and erase works out of the box. I also verified with the original congatec tool. It reports success! SST49LF008A IEI PICOe-9452 (http://www.iei.com.tw/en/product_IPC.asp?model=PICOe-9452) Everything ok... SST39SF040 LEX Systems CV700A (http://www.lex.com.tw/product/CV700A_s.htm) Everything works fine... SST49LF004A/B Portwell PEB-4700VLA (http://www.portwell.com/products/detail.asp?CUSTCHAR1=PEB-4700VLA) Everything works fine.. Best regards Mario Rogen

3 3

r3736 - trunk/util/flashrom
by svn＠coreboot.org 08 Nov '08

08 Nov '08

Author: stuge Date: 2008-11-08 02:39:12 +0100 (Sat, 08 Nov 2008) New Revision: 3736 Modified: trunk/util/flashrom/flashchips.c Log: flashrom: SST39SF040 TEST_OK_ PROBE READ ERASE WRITE Per report from Mario Rogen. Thanks! Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-11-08 00:58:16 UTC (rev 3735) +++ trunk/util/flashrom/flashchips.c 2008-11-08 01:39:12 UTC (rev 3736) @@ -91,7 +91,7 @@ {"SST", "SST29LE020", SST_ID, SST_29LE020, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"SST", "SST39SF010A", SST_ID, SST_39SF010, 128, 4096, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39SF020A", SST_ID, SST_39SF020, 256, 4096, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_39sf020}, - {"SST", "SST39SF040", SST_ID, SST_39SF040, 512, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, + {"SST", "SST39SF040", SST_ID, SST_39SF040, 512, 4096, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39VF512", SST_ID, SST_39VF512, 64, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39VF010", SST_ID, SST_39VF010, 128, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39VF020", SST_ID, SST_39VF020, 256, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020},

1 0

Re: [coreboot] fixing i810 onboard vga
by Elia Yehuda 08 Nov '08

08 Nov '08

tnx Joseph, i've fixed the following (to match my 256kb bios) : device pci_domain 0 on device pci 0.0 on end # Host bridge chip drivers/pci/onboard device pci 1.0 on end # Onboard video register "rom_address" = "0xfffc0000" end ... end and now the rom_address is set AND i see the device in lspci : lspci: 00:01.0 VGA compatible controller: Intel Corporation 82810E DC-133 (CGC) Chipset Graphics Controller (rev 03) lspci -n: 00:01.0 0300: 8086:7125 (rev 03) but still no vga-output! i found the following to might suggest another problem : PCI Expansion ROM, signature 0xaa55, INIT size 0xa000, data ptr 0x0110 PCI ROM Image, Vendor 8086, Device 0000, Device or Vendor ID mismatch Vendor 8086, Device 0000 and no "copying VGA ROM Image"... any idea where the device_id needs to be set? (the weird thing is that the device_id is shown fine on lspci -n output) i'm attaching the complete boot log at the end of the message. Regards, Elia Yehuda. On Fri, Nov 7, 2008 at 3:35 AM, Joseph Smith <joe(a)settoplinux.org> wrote: > > > > On Fri, 7 Nov 2008 03:19:35 +0200, "Elia Yehuda" <z4ziggy(a)gmail.com> > wrote: > > many thanks Joseph! > > > > you sure have found the problem in the code (without even looking... > > remarkable). > > > > i sure had the "CONFIG_VIDEO_MB=8" to my targets' Config.lb which was > > being > > ignored... > > so i've added the following (elementary) patch to > > coreboot-v2/src/northbridge/intel/i82810/northbridge.c : > > > > Index: northbridge.c > > =================================================================== > > --- northbridge.c (revision 3698) > > +++ northbridge.c (working copy) > > @@ -149,6 +149,16 @@ > > drp_value = drp_value >> 4; // >>= 4; //? mess with later > > tomk += (unsigned long)(translate_i82810_to_mb[drp_value]); > > > > +#ifdef CONFIG_VIDEO_MB > > + /* check for VGA reserved memory */ > > + if (CONFIG_VIDEO_MB == 512) { > > + /* FIXME: we round up the 1/2mb to 1 */ > > + tomk -= 1; > > + } else { > > + tomk -= CONFIG_VIDEO_MB; > > + } > > +#endif > > + > > printk_debug("Setting RAM size to %d MB\n", tomk); > > > > /* Convert tomk from MB to KB. */ > > > > > > > > the boot now works, > > Great, that is a start :-) > > > but still no onboard-vga. ive noticed in > > pci_rom_probe() > > the dev->rom_address of the vga pci card is 0 (zero)! although i have the > > following in the mainboard/manu/type/Config.lb : > > ... > > device pci 1.0 on # Onboard video > > chip drivers/pci/onboard > > device pci 1.0 on end > > register "rom_address" = "0xfffc0000" > > end > > end > > ... > > > This should be: > > device pci_domain 0 on > device pci 0.0 on end # Host bridge > chip drivers/pci/onboard > device pci 1.0 on end # Onboard video > register "rom_address" = "0xfff80000" > end > end > > Hope that helps. > > -- > Thanks, > Joseph Smith > Set-Top-Linux > www.settoplinux.org > > complete boot log : coreboot-2.0.0.0Fallback Fri Nov 7 04:00:16 IST 2008 starting... Ram1.00 i810 Initial registers have been set. Ram2.00 Ram3 Found DIMM in slot 00 DIMM is 0x80MB After translation, dimm_size is 0x0d No DIMM found in slot 01 DRP calculated to 0x0d RAM Enable 1: Apply NOP Sending RAM command 0x88 to 0x00000000 RAM Enable 2: Precharge all Sending RAM command 0xa8 to 0x00000000 RAM Enable 3: CBR Sending RAM command 0xe8 to 0x00000000 RAM Enable 4: Mode register set Sending RAM command 0xc8 to 0x000001d0 RAM Enable 5: Normal operation Sending RAM command 0x28 to 0x00000000 RAM Enable 6: Enable Refresh Northbridge following SDRAM init: Ram4 coreboot-2.0.0.0Fallback Fri Nov 7 04:00:16 IST 2008 booting... end c9788c81, start 12 32-bit delta 1543 calibrate_tsc 32-bit result is 1543 clocks_per_usec: 1543 Enumerating buses... scan_static_bus for Root Device APIC_CLUSTER: 0 enabled Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/7124] enabled PCI: 00:01.0 [8086/7125] enabled PCI: 00:02.0, bad id 0xffffffff PCI: 00:03.0, bad id 0xffffffff PCI: 00:04.0, bad id 0xffffffff PCI: 00:05.0, bad id 0xffffffff PCI: 00:06.0, bad id 0xffffffff PCI: 00:07.0, bad id 0xffffffff PCI: 00:08.0, bad id 0xffffffff PCI: 00:09.0, bad id 0xffffffff PCI: 00:0a.0, bad id 0xffffffff PCI: 00:0b.0, bad id 0xffffffff PCI: 00:0c.0, bad id 0xffffffff PCI: 00:0d.0, bad id 0xffffffff PCI: 00:0e.0, bad id 0xffffffff PCI: 00:0f.0, bad id 0xffffffff PCI: 00:10.0, bad id 0xffffffff PCI: 00:11.0, bad id 0xffffffff PCI: 00:12.0, bad id 0xffffffff PCI: 00:13.0, bad id 0xffffffff PCI: 00:14.0, bad id 0xffffffff PCI: 00:15.0, bad id 0xffffffff PCI: 00:16.0, bad id 0xffffffff PCI: 00:17.0, bad id 0xffffffff PCI: 00:18.0, bad id 0xffffffff PCI: 00:19.0, bad id 0xffffffff PCI: 00:1a.0, bad id 0xffffffff PCI: 00:1b.0, bad id 0xffffffff PCI: 00:1c.0, bad id 0xffffffff PCI: 00:1d.0, bad id 0xffffffff PCI: 00:1e.0 [8086/2418] bus ops PCI: 00:1e.0 [8086/2418] enabled PCI: 00:1f.0 [8086/2410] bus ops PCI: 00:1f.0 [8086/2410] enabled PCI: 00:1f.1 [8086/2411] ops PCI: 00:1f.1 [8086/2411] enabled PCI: 00:1f.2 [8086/2412] ops PCI: 00:1f.2 [8086/2412] enabled PCI: 00:1f.3 [8086/2413] enabled PCI: 00:1f.4, bad id 0xffffffff PCI: 00:1f.5 [8086/2415] ops PCI: 00:1f.5 [8086/2415] enabled malloc Enter, size 1100, free_mem_ptr 00026000 malloc 0x00026000 PCI: 00:1f.6 [8086/2416] ops PCI: 00:1f.6 [8086/2416] enabled PCI: 00:1f.7, bad id 0xffffffff do_pci_scan_bridge for PCI: 00:1e.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0, bad id 0xffffffff PCI: 01:01.0, bad id 0xffffffff PCI: 01:02.0, bad id 0xffffffff PCI: 01:03.0, bad id 0xffffffff PCI: 01:04.0, bad id 0xffffffff malloc Enter, size 1100, free_mem_ptr 0002644c malloc 0x0002644c PCI: 01:05.0 [10ec/8139] enabled PCI: 01:06.0, bad id 0xffffffff PCI: 01:07.0, bad id 0xffffffff PCI: 01:08.0, bad id 0xffffffff PCI: 01:09.0, bad id 0xffffffff PCI: 01:0a.0, bad id 0xffffffff PCI: 01:0b.0, bad id 0xffffffff PCI: 01:0c.0, bad id 0xffffffff PCI: 01:0d.0, bad id 0xffffffff PCI: 01:0e.0, bad id 0xffffffff PCI: 01:0f.0, bad id 0xffffffff PCI: 01:10.0, bad id 0xffffffff PCI: 01:11.0, bad id 0xffffffff PCI: 01:12.0, bad id 0xffffffff PCI: 01:13.0, bad id 0xffffffff PCI: 01:14.0, bad id 0xffffffff PCI: 01:15.0, bad id 0xffffffff PCI: 01:16.0, bad id 0xffffffff PCI: 01:17.0, bad id 0xffffffff PCI: 01:18.0, bad id 0xffffffff PCI: 01:19.0, bad id 0xffffffff PCI: 01:1a.0, bad id 0xffffffff PCI: 01:1b.0, bad id 0xffffffff PCI: 01:1c.0, bad id 0xffffffff PCI: 01:1d.0, bad id 0xffffffff PCI: 01:1e.0, bad id 0xffffffff PCI: 01:1f.0, bad id 0xffffffff PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:1f.0 malloc Enter, size 1100, free_mem_ptr 00026898 malloc 0x00026898 malloc Enter, size 1100, free_mem_ptr 00026ce4 malloc 0x00026ce4 malloc Enter, size 1100, free_mem_ptr 00027130 malloc 0x00027130 malloc Enter, size 1100, free_mem_ptr 0002757c malloc 0x0002757c malloc Enter, size 1100, free_mem_ptr 000279c8 malloc 0x000279c8 PNP: 002e.1 enabled PNP: 002e.2 enabled PNP: 002e.5 enabled PNP: 002e.8 enabled PNP: 002e.9 enabled PNP: 002e.a enabled PNP: 002e.0 enabled PNP: 002e.3 enabled PNP: 002e.6 enabled PNP: 002e.7 enabled PNP: 002e.b enabled scan_static_bus for PCI: 00:1f.0 done PCI: pci_scan_bus returning with max=001 scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device compute_allocate_resource io: base: 00000400 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:1e.0 compute_allocate_resource io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 00:1e.0 read_resources bus 1 link: 0 PCI: 00:1e.0 read_resources bus 1 link: 0 done PCI: 01:05.0 10 * [0x00000000 - 0x000000ff] io PCI: 00:1e.0 compute_allocate_resource io: base: 00000100 size: 00001000 align: 12 gran: 12 done PCI: 00:1e.0 compute_allocate_resource prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:1e.0 read_resources bus 1 link: 0 PCI: 00:1e.0 read_resources bus 1 link: 0 done PCI: 00:1e.0 compute_allocate_resource prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:1e.0 compute_allocate_resource prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:1e.0 read_resources bus 1 link: 0 PCI: 00:1e.0 read_resources bus 1 link: 0 done PCI: 00:1e.0 compute_allocate_resource prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:1e.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:1e.0 compute_allocate_resource mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:1e.0 read_resources bus 1 link: 0 PCI: 00:1e.0 read_resources bus 1 link: 0 done PCI: 01:05.0 14 * [0x00000000 - 0x000000ff] mem PCI: 00:1e.0 compute_allocate_resource mem: base: 00000100 size: 00100000 align: 20 gran: 20 done PCI: 00:1f.0 read_resources bus 0 link: 0 PCI: 00:1f.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done PCI: 00:1e.0 1c * [0x00001000 - 0x00001fff] io PCI: 00:1f.5 10 * [0x00002000 - 0x000020ff] io PCI: 00:1f.6 10 * [0x00002400 - 0x000024ff] io PCI: 00:1f.6 14 * [0x00002800 - 0x0000287f] io PCI: 00:1f.5 14 * [0x00002880 - 0x000028bf] io PCI: 00:1f.2 20 * [0x000028c0 - 0x000028df] io PCI: 00:1f.1 20 * [0x000028e0 - 0x000028ef] io PCI: 00:1f.3 20 * [0x000028f0 - 0x000028ff] io PNP: 002e.7 60 * [0x00002c00 - 0x00002c00] io Root Device compute_allocate_resource io: base: 00002c01 size: 00002801 align: 12 gran: 0 done Root Device compute_allocate_resource mem: base: 00000000 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:01.0 10 * [0x00000000 - 0x01ffffff] prefmem PCI: 00:1e.0 20 * [0x02000000 - 0x020fffff] mem PCI: 00:01.0 14 * [0x02100000 - 0x0217ffff] mem Root Device compute_allocate_resource mem: base: 02180000 size: 02180000 align: 25 gran: 0 done Done reading resources. Allocating VGA resource PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... Root Device compute_allocate_resource io: base: 00001000 size: 00002801 align: 12 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:1e.0 1c * [0x00001000 - 0x00001fff] io PCI: 00:1f.5 10 * [0x00002000 - 0x000020ff] io PCI: 00:1f.6 10 * [0x00002400 - 0x000024ff] io PCI: 00:1f.6 14 * [0x00002800 - 0x0000287f] io PCI: 00:1f.5 14 * [0x00002880 - 0x000028bf] io PCI: 00:1f.2 20 * [0x000028c0 - 0x000028df] io PCI: 00:1f.1 20 * [0x000028e0 - 0x000028ef] io PCI: 00:1f.3 20 * [0x000028f0 - 0x000028ff] io PNP: 002e.7 60 * [0x00002c00 - 0x00002c00] io Root Device compute_allocate_resource io: base: 00002c01 size: 00001c01 align: 12 gran: 0 done Root Device compute_allocate_resource mem: base: fc000000 size: 02180000 align: 25 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:01.0 10 * [0xfc000000 - 0xfdffffff] prefmem PCI: 00:1e.0 20 * [0xfe000000 - 0xfe0fffff] mem PCI: 00:01.0 14 * [0xfe100000 - 0xfe17ffff] mem Root Device compute_allocate_resource mem: base: fe180000 size: 02180000 align: 25 gran: 0 done Root Device assign_resources, bus 0 link: 0 Setting RAM size to 120 MB PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 prefmem PCI: 00:01.0 14 <- [0x00fe100000 - 0x00fe17ffff] size 0x00080000 gran 0x13 mem PCI: 00:01.0 30 <- [0x00fffc0000 - 0x00fffbffff] size 0x00000000 gran 0x00 romem PCI: 00:1e.0 compute_allocate_resource io: base: 00001000 size: 00001000 align: 12 gran: 12 PCI: 00:1e.0 read_resources bus 1 link: 0 PCI: 00:1e.0 read_resources bus 1 link: 0 done PCI: 01:05.0 10 * [0x00001000 - 0x000010ff] io PCI: 00:1e.0 compute_allocate_resource io: base: 00001100 size: 00001000 align: 12 gran: 12 done PCI: 00:1e.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:1e.0 compute_allocate_resource mem: base: fe000000 size: 00100000 align: 20 gran: 20 PCI: 00:1e.0 read_resources bus 1 link: 0 PCI: 00:1e.0 read_resources bus 1 link: 0 done PCI: 01:05.0 14 * [0xfe000000 - 0xfe0000ff] mem PCI: 00:1e.0 compute_allocate_resource mem: base: fe000100 size: 00100000 align: 20 gran: 20 done PCI: 00:1e.0 20 <- [0x00fe000000 - 0x00fe0fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 00:1e.0 assign_resources, bus 1 link: 0 PCI: 01:05.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 01:05.0 14 <- [0x00fe000000 - 0x00fe0000ff] size 0x00000100 gran 0x08 mem PCI: 00:1e.0 assign_resources, bus 1 link: 0 PCI: 00:1f.0 assign_resources, bus 0 link: 0 PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq PNP: 002e.1 74 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq ERROR: PNP: 002e.0 60 io size: 0x0000000008 not assigned ERROR: PNP: 002e.0 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.0 74 drq size: 0x0000000001 not assigned ERROR: PNP: 002e.3 60 io size: 0x0000000008 not assigned ERROR: PNP: 002e.3 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.6 60 io size: 0x0000000008 not assigned ERROR: PNP: 002e.6 70 irq size: 0x0000000001 not assigned PNP: 002e.7 60 <- [0x0000002c00 - 0x0000002c00] size 0x00000001 gran 0x00 io ERROR: PNP: 002e.7 62 io size: 0x0000000002 not assigned ERROR: PNP: 002e.7 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.b 60 io size: 0x0000000008 not assigned ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned PCI: 00:1f.0 assign_resources, bus 0 link: 0 PCI: 00:1f.1 20 <- [0x00000028e0 - 0x00000028ef] size 0x00000010 gran 0x04 io PCI: 00:1f.2 20 <- [0x00000028c0 - 0x00000028df] size 0x00000020 gran 0x05 io PCI: 00:1f.3 20 <- [0x00000028f0 - 0x00000028ff] size 0x00000010 gran 0x04 io PCI: 00:1f.5 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:1f.5 14 <- [0x0000002880 - 0x00000028bf] size 0x00000040 gran 0x06 io PCI: 00:1f.6 10 <- [0x0000002400 - 0x00000024ff] size 0x00000100 gran 0x08 io PCI: 00:1f.6 14 <- [0x0000002800 - 0x000000287f] size 0x00000080 gran 0x07 io PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Done allocating resources. Enabling resources... PCI: 00:00.0 subsystem <- 00/00 PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 subsystem <- 00/00 PCI: 00:01.0 cmd <- 07 PCI: 00:1e.0 bridge ctrl <- 0003 PCI: 00:1e.0 cmd <- 07 PCI: 01:05.0 cmd <- 03 PCI: 00:1f.0 cmd <- 0f w83627hf hwm smbus enabled PCI: 00:1f.1 cmd <- 01 PCI: 00:1f.2 cmd <- 01 PCI: 00:1f.3 subsystem <- 00/00 PCI: 00:1f.3 cmd <- 01 PCI: 00:1f.5 cmd <- 01 PCI: 00:1f.6 cmd <- 01 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init malloc Enter, size 1100, free_mem_ptr 00027e14 malloc 0x00027e14 Initializing CPU #0 CPU: vendor Intel device 683 CPU: family 06, model 08, stepping 03 Enabling cache Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 64MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 1, base: 64MB, range: 32MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 2, base: 96MB, range: 16MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 3, base: 112MB, range: 8MB, type WB ADDRESS_MASK_HIGH=0xf DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled microcode_info: sig = 0x00000683 pf=0x00000010 rev = 0x00000000 Disabling local apic...done. CPU #0 Initialized PCI: 00:00.0 init pci_rom_probe() : dev->on_mainboard pci_rom_probe(): skipping for PCI: 00:00.0 = 0 PCI: 00:01.0 init pci_rom_probe() : dev->on_mainboard rom address for PCI: 00:01.0 = fffc0000 PCI Expansion ROM, signature 0xaa55, INIT size 0xa000, data ptr 0x0110 PCI ROM Image, Vendor 8086, Device 0000, Device or Vendor ID mismatch Vendor 8086, Device 0000 PCI: 00:1e.0 init PCI: 00:1f.0 init IOAPIC Southbridge enabled 2186 Southbridge APIC ID = 2000000 Set power on if power fails RTC Init PNP: 002e.1 init PNP: 002e.2 init PNP: 002e.5 init Keyboard init... PNP: 002e.8 init PNP: 002e.9 init PNP: 002e.a init PCI: 00:1f.1 init IDE0 IDE1 PCI: 00:1f.2 init PCI: 00:1f.3 init pci_rom_probe() : dev->on_mainboard pci_rom_probe(): skipping for PCI: 00:1f.3 = 0 PCI: 01:05.0 init pci_rom_probe() : !dev->on_mainboard (0/0) pci_rom_probe(): skipping for PCI: 01:05.0 = 0 PNP: 002e.0 init PNP: 002e.3 init PNP: 002e.6 init PNP: 002e.7 init PNP: 002e.b init Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. Moving GDT to 0x500...ok Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f0400 to 0x00100000 Booting 'hda1:/boot/vmlinuz-2.6.27-7-server root=/dev/sda1 ro console=ttyS0,115 200n8 console=tty0 initrd=hda1:/boot/initrd.img-2.6.27-7-server' Found Linux version 2.6.27-7-server (buildd@rothera) #1 SMP Fri Oct 24 07:37:55 UTC 2008 bzImage. Loading kernel... ok Loading initrd... ok Jumping to entry point...

7 23

[PATCH 1/2] bayou: use ACS for line drawing
by Ulf Jordan 08 Nov '08

08 Nov '08

Hello! Attached is a patch to update Bayou v0.3 to use ACS_ macros for the line drawing characters in the menu window border. Build and run tested under QEMU with bayou-0.3+coreboot-v3. /ulf

2 2

r3735 - trunk/payloads/bayou
by svn＠coreboot.org 08 Nov '08

08 Nov '08

Author: stuge Date: 2008-11-08 01:58:16 +0100 (Sat, 08 Nov 2008) New Revision: 3735 Modified: trunk/payloads/bayou/menu.c Log: Update bayou to use ACS_ macros for line drawing characters. Signed-off-by: Ulf Jordan <jordan(a)chalmers.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/payloads/bayou/menu.c =================================================================== --- trunk/payloads/bayou/menu.c 2008-11-06 22:38:31 UTC (rev 3734) +++ trunk/payloads/bayou/menu.c 2008-11-08 00:58:16 UTC (rev 3735) @@ -67,8 +67,8 @@ wattrset(menuwin, COLOR_PAIR(3)); wclear(menuwin); - wborder(menuwin, '\263', '\263', '\304', '\304', '\332', - '\277', '\300', '\331'); + wborder(menuwin, ACS_VLINE, ACS_VLINE, ACS_HLINE, ACS_HLINE, + ACS_ULCORNER, ACS_URCORNER, ACS_LLCORNER, ACS_LRCORNER); wattrset(menuwin, COLOR_PAIR(4) | A_BOLD); mvwprintw(menuwin, 0, (menu_width - 17) / 2, " Payload Chooser ");

1 0

FW: Source code download difficulties
by Ken.Fuchs＠bench.com 08 Nov '08

08 Nov '08

Ken Fuchs wrote: > $ svn co https://coreboot.org/svn/trunk/coreboot-v2 Sorry, the above command should have been quoted as: svn co https://coreboot.org/svn/trunk/filo > svn: PROPFIND request failed on '/svn/trunk/filo' > svn: PROPFIND of '/svn/trunk/filo': 405 Method Not Allowed > (https://coreboot.org) Sincerely, Ken Fuchs

2 2

Homemaid LPC flasher
by Joseph Smith 07 Nov '08

07 Nov '08

Hello everyone. Sorry for the quietness lately, I have been out straight at work implimenting a new tape library project (BRMS for those of you that know AS400's). Kind of cool working with LTO4's (1 1/2 terabites) and a tape library that can hold 110 LTO4's (IBM TS3310). Anyways, I am going to start a project based on a very simple and CHEAP LPC flasher originally designed for the xbox. http://rex.xbox-scene.com/LPC2/LPC2.html I have a friend that has already tested this on fwh hubs (SST49LF008A to be exact) and it worked great. I have placed an order so the parts should be arriving soon. The downside is the software is only for dos/win, but the software source code is also available on the site. I think it would be pretty easy to convert it to Linux. I am trying to get a hold of the original author for permission to release it under a GPL. My question to the coreboot community is….. I have no problem hosting this project on my site, but would everyone like me to incorporate this project into coreboot? If so is anyone interested in helping? By the way Stefan great work on the i945!! Those Intel doors are starting to slowly creep open... -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

5 10

Re: [coreboot] Flash Rom Live CD
by bari 07 Nov '08

07 Nov '08

Marco Schmidt wrote: > Dear Bari, > when will the first version of the CD be ready? > > Cheers, > Marco > __________________________________________________ > Dr.-Ing. Marco Schmidt > Software Development Engineer > Core Real-Time Implementation, Real-Time Processor Core > Werk 5, EG., Raum 6008 > dSPACE GmbH Tel.: +49 5251 1638 1829 > Technologiepark 25 > 33100 Paderborn _<__http://www.dspace.com__>_ > Germany _<__mailto:mschmidt@dspace.de__>_ > > __________________________________________________ > > We've been pretty busy and there hasn't been a real big demand. It would be nice though. Maybe near the end of the year. It will be up on the coreboot site when it's ready. http://www.coreboot.org/Flashrom_Live_CD -Bari

1 0

Fw: Coreboot on Tyan S2892
by Marc Jones 07 Nov '08

07 Nov '08

Meant to send this to the list. ----- Forwarded Message ---- > From: Marc Jones <marcj303(a)yahoo.com> > To: Myles Watson <mylesgw(a)gmail.com> > Sent: Friday, November 7, 2008 2:53:06 PM > Subject: Re: [coreboot] Coreboot on Tyan S2892 > > > > >> configure and build FILO (filo.elf will include the kernel image?) > > > Not needed. Filo doesn't have SATA drivers. That's why you need a kernel in > the ROM. > > > > You will have to configure the shell and the boot scripts in > buildrom/buildrom-devel/skeleton/ > > They select the defaults, mount the drives, etc. > > SATA devices should be in legacy mode and filo should be able to load your > kernel. The only challenge is getting the drive numbering lined up. > in buildrom do a make filo-config. You also need a grub like menu.lst on the > drive. > > > >> use buildrom to create the actual ROM image file (superset of filo.elf?) > > Use buildrom, but the file only will have coreboot and the kernel with a > minimal shell > > Use buildrom. If the platform isn't in the makeconfig, it is easy to add. > > > Marc

1 0

alix2c3 LEDs and mode switch
by Roman Yeryomin 07 Nov '08

07 Nov '08

Is there any chance to get LEDs working on alix boards? I suppose only GPIO lines/ports should be enabled in coreboot an everything else is done in software. Here is what documentation says about them: Status LEDs are all turned on by the BIOS on power up. The BIOS will turn off LEDs 2 and 3 before booting the operating system. Location GPIO read port write port LED1 (left) G6 port 06100h bit 6 port 06100h bit 6 / 22 LED2 (middle) G25 port 06180h bit 9 port 06180h bit 9 / 25 LED3 (right) G27 port 06180h bit 11 port 06180h bit 11 / 27 The CS5536 GPIO ports are programmed by 32 bit atomic writes. This avoids the need for read / modify / write operations and the locking issues they entail. For example, to turn off LED1 (high), write 0000'0040h to port 06100h. To turn on LED1 (low), write 0040'0000h. Multiple port bits can be changed at the same time. Maybe mode switch could also be useful: The mode switch can be accessed by software as follows: Location GPIO read port MODESW# G24 port 061b0h bit 8 (active low, 0 = switch pressed) Roman

2 3

← Newer
1
...
35
36
37
38
39
40
41
...
49
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot November 2008