coreboot November 2008

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490 discussions

r989 - coreboot-v3/util/x86emu
by svn＠coreboot.org 09 Nov '08

09 Nov '08

Author: hailfinger Date: 2008-11-09 02:03:57 +0100 (Sun, 09 Nov 2008) New Revision: 989 Modified: coreboot-v3/util/x86emu/Makefile Log: r965 broke x86emu compilation on all v3 targets. Fix the issue. OBJ->SRC conversions are a bit tricky to get right. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/util/x86emu/Makefile =================================================================== --- coreboot-v3/util/x86emu/Makefile 2008-11-08 22:39:35 UTC (rev 988) +++ coreboot-v3/util/x86emu/Makefile 2008-11-09 01:03:57 UTC (rev 989) @@ -23,7 +23,7 @@ VM86_SRC = vm86.c vm86_gdt.c ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y) -LIBX86EMU_SRC=$(X86EMU_SRC) $(BIOSEMU_SRC) +LIBX86EMU_SRC=$(patsubst %,x86emu/%,$(X86EMU_SRC)) $(BIOSEMU_SRC) endif ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_VM86),y)

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[PATCH] v3: Explain the ld options for initram
by Carl-Daniel Hailfinger 08 Nov '08

08 Nov '08

initram is linked with very special options to ld. It is not immediately obvious that they are needed, so a comment to that effect will hopefully prevent accidental "cleanups" in the future when nobody remembers the history of that makefile rule anymore. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-makefile_ld_xip_comments/arch/x86/Makefile =================================================================== --- corebootv3-makefile_ld_xip_comments/arch/x86/Makefile (Revision 986) +++ corebootv3-makefile_ld_xip_comments/arch/x86/Makefile (Arbeitskopie) @@ -274,6 +274,8 @@ $(Q)$(AS) $(obj)/initram_picwrapper.s -o $(obj)/initram_picwrapper.o $(Q)# initram links against stage0 $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" + $(Q)# WARNING: Using -N (and not -n or others) for ld is essential to + $(Q)# get all important stuff into one segment! $(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \ $(obj)/coreboot.initram_partiallylinked.o \ $(obj)/initram_picwrapper.o -o $(obj)/coreboot.initram -- http://www.hailfinger.org/

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r988 - coreboot-v3/arch/x86
by svn＠coreboot.org 08 Nov '08

08 Nov '08

Author: hailfinger Date: 2008-11-08 23:39:35 +0100 (Sat, 08 Nov 2008) New Revision: 988 Modified: coreboot-v3/arch/x86/Makefile Log: initram is linked with very special options to ld. It is not immediately obvious that they are needed, so a comment to that effect will hopefully prevent accidental "cleanups" in the future when nobody remembers the history of that makefile rule anymore. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/arch/x86/Makefile =================================================================== --- coreboot-v3/arch/x86/Makefile 2008-11-07 16:33:57 UTC (rev 987) +++ coreboot-v3/arch/x86/Makefile 2008-11-08 22:39:35 UTC (rev 988) @@ -274,6 +274,8 @@ $(Q)$(AS) $(obj)/initram_picwrapper.s -o $(obj)/initram_picwrapper.o $(Q)# initram links against stage0 $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" + $(Q)# WARNING: Using -N (and not -n or others) for ld is essential to + $(Q)# get all important stuff into one segment! $(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \ $(obj)/coreboot.initram_partiallylinked.o \ $(obj)/initram_picwrapper.o -o $(obj)/coreboot.initram

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Source code download difficulties
by Ken.Fuchs＠bench.com 08 Nov '08

08 Nov '08

I'm able to easily download the coreboot kernel from qa.coreboot.org, but all ancillary source code like FILO and libpayload are not easy to download. I'm behind firewall/proxy that allows only http and maybe https (with _valid_ certificates). In addition, the coreboot.org SSL certificate doesn't seem to be validated by a recognized certificate authority. $ svn co https://coreboot.org/svn/trunk/coreboot-v2 svn: PROPFIND request failed on '/svn/trunk/filo' svn: PROPFIND of '/svn/trunk/filo': 405 Method Not Allowed (https://coreboot.org) There seems to be a way to use tracker to get zip files of source code, but it doesn't seem to be available for all coreboot projects. What is the recommended way to get coreboot ancillary project source code like FILO and libpayload when svn and https/WebDAV protocols are not available or don't work? All coreboot source code should be available via one or more tarballs (like the coreboot kernel itself). Sincerely, Ken Fuchs

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FW: Source code download difficulties
by Ken.Fuchs＠bench.com 08 Nov '08

08 Nov '08

Ken Fuchs wrote: >> $ svn co https://coreboot.org/svn/trunk/coreboot-v2 > $ svn co https://coreboot.org/svn/trunk/filo OK, it appears that I still got the wrong URI for filo. Here's the correct one: $ svn co https://coreboot.org/filo/ <It does download the main filo files OK and then ...> Fetching external item into 'filo/trunk/filo/libpayload' svn: Can't connect to host 'coreboot.org': Connection refused $ How do I download the libpayload source code? Sincerely, Ken Fuchs

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Re: [coreboot] alix2c3 LEDs and mode switch
by Roman Yeryomin 08 Nov '08

08 Nov '08

On Fri, Nov 7, 2008 at 8:47 PM, Marc Jones <marcj303(a)yahoo.com> wrote: > I think I came into this discussion late with getting my email switched over. > What are you trying to accomplish and where/what do you want to control the LED from? There is fully functional linux kernel driver (see attachment) which works flawlessly with tinybios (alix factory bios). I want to indicate software status events (for example network is up or down) using custom scripts and driver I've mentioned. Roman

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and/or busybox issue with alix2c3 serial console
by Roman Yeryomin 08 Nov '08

08 Nov '08

I'm experimenting with coreboot (v3) on alix2c3 and still can't get serial console working. :( It stops right after kernel is done booting (I can see coreboot, filo and kernel messages just fine). I use openWRT but tried also another busybox based distribution (imedialinux) -- same problem. With original tinybios no problem. At the same time I tried voyage linux (without busybox) with corebooted alix and it has no such problem. It's obvious that this problem cannot be identified as 100% busybox's (why then it works on tinybios?). While digging coreboot sources I've noticed that uart initialization is done twice for this board -- once in /southbridge/amd/cs5536/cs5536.c (based on dts config) and second time in /mainboard/pcengines/alix2c3/stage1.c. I tried playing with these (and /southbridge/amd/cs5536/stage1.c), disabling one code or another, but no luck. Tried to set MOD bits: msr.lo = (1 << 4) | (1 << 5) | (1 << 6); msr.hi = 0; wrmsr(MDD_UART1_MOD, msr); Also no luck. Not enabling upper banks, however, makes uart appear in kernel as regular 16550A (and not as NS16550): /* Bit 1 = DEVEN (device enable) * Bit 4 = EN_BANKS (allow access to the upper banks) */ //msr.lo = (1 << 4) | (1 << 1); msr.lo = 1 << 1; msr.hi = 0; So... where should I go now? I'm really stuck. Begging for help... Regards, Roman

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[PATCH 2/2] bayou: adjust color pairs
by Ulf Jordan 08 Nov '08

08 Nov '08

Hello! Atttached is a patch that will restore blue background and bright yellow menu title in Bayou v0.3, after (if) the tinycurses VGA color correction patch is applied (see an earlier thread started today). Build and run tested under QEMU with bayou-0.3+coreboot-v3. /ulf

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r3737 build service
by coreboot information 08 Nov '08

08 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "hailfinger" checked in revision 3737 to the coreboot source repository and caused the following changes: Change Log: The POST_CODE macro had the outb() argument order backwards. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of sunw:ultra40 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3737&device=ultra40&vendor… Compilation of supermicro:x6dai_g has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3737&device=x6dai_g&vendor… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3737 - trunk/coreboot-v2/src/northbridge/amd/gx2
by svn＠coreboot.org 08 Nov '08

08 Nov '08

Author: hailfinger Date: 2008-11-08 02:51:32 +0100 (Sat, 08 Nov 2008) New Revision: 3737 Modified: trunk/coreboot-v2/src/northbridge/amd/gx2/pll_reset.c Log: The POST_CODE macro had the outb() argument order backwards. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/northbridge/amd/gx2/pll_reset.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx2/pll_reset.c 2008-11-08 01:39:12 UTC (rev 3736) +++ trunk/coreboot-v2/src/northbridge/amd/gx2/pll_reset.c 2008-11-08 01:51:32 UTC (rev 3737) @@ -115,7 +115,7 @@ #if USE_GOODRICH_VERSION /////////////////////////////////////////////////////////////////////////////// // Goodrich Version of pll_reset -#define POST_CODE(x) outb(0x80, x) +#define POST_CODE(x) outb(x, 0x80) // PLLCHECK_COMPLETED is the "we've already done this" flag #define PLLCHECK_COMPLETED (1 << RSTPLL_LOWER_SWFLAGS_SHIFT)

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coreboot November 2008