coreboot November 2008

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490 discussions

r3740 - trunk/util/getpir
by svn＠coreboot.org 10 Nov '08

10 Nov '08

Author: stepan Date: 2008-11-10 14:52:14 +0100 (Mon, 10 Nov 2008) New Revision: 3740 Modified: trunk/util/getpir/code_gen.c Log: cosmetic update for getpir. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/getpir/code_gen.c =================================================================== --- trunk/util/getpir/code_gen.c 2008-11-10 13:03:56 UTC (rev 3739) +++ trunk/util/getpir/code_gen.c 2008-11-10 13:52:14 UTC (rev 3740) @@ -46,7 +46,7 @@ rt->exclusive_irqs); fprintf(fpir, "\t%#x, /* Vendor */\n", rt->rtr_vendor); fprintf(fpir, "\t%#x, /* Device */\n", rt->rtr_device); - fprintf(fpir, "\t%#x, /* Crap (miniport) */\n", + fprintf(fpir, "\t%#x, /* Miniport */\n", rt->miniport_data); fprintf(fpir, "\t{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */\n"); fprintf(fpir, "\t%#x, /* u8 checksum. This has to be set to some\n value that would give 0 after the sum of all\n bytes for this structure (including checksum) */\n", @@ -54,7 +54,7 @@ fprintf(fpir, "\t{\n"); fprintf(fpir, "\t\t/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */\n"); for (i = 0; i < ts; i++) { - fprintf(fpir, "\t\t{0x%02x,(0x%02x<<3)|0x%01x, {{0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x0%04x}}, 0x%x, 0x%x},\n", + fprintf(fpir, "\t\t{0x%02x,(0x%02x<<3)|0x%01x, {{0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}}, 0x%x, 0x%x},\n", (se_arr+i)->bus, (se_arr+i)->devfn >> 3, (se_arr+i)->devfn & 7, (se_arr+i)->irq[0].link, (se_arr+i)->irq[0].bitmap, (se_arr+i)->irq[1].link,

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r3739 build service
by coreboot information 10 Nov '08

10 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3739 to the coreboot source repository and caused the following changes: Change Log: add inteltool to v2/util (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of digitallogic:adl855pc has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3739 - trunk/coreboot-v2/util
by svn＠coreboot.org 10 Nov '08

10 Nov '08

Author: stepan Date: 2008-11-10 14:03:56 +0100 (Mon, 10 Nov 2008) New Revision: 3739 Modified: trunk/coreboot-v2/util/ Log: add inteltool to v2/util (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Property changes on: trunk/coreboot-v2/util ___________________________________________________________________ Modified: svn:externals - flashrom svn://coreboot.org/repos/trunk/util/flashrom nvramtool svn://coreboot.org/repos/trunk/util/nvramtool superiotool svn://coreboot.org/repos/trunk/util/superiotool getpir svn://coreboot.org/repos/trunk/util/getpir mptable svn://coreboot.org/repos/trunk/util/mptable + flashrom svn://coreboot.org/repos/trunk/util/flashrom nvramtool svn://coreboot.org/repos/trunk/util/nvramtool superiotool svn://coreboot.org/repos/trunk/util/superiotool getpir svn://coreboot.org/repos/trunk/util/getpir mptable svn://coreboot.org/repos/trunk/util/mptable inteltool svn://coreboot.org/repos/trunk/util/inteltool

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How coreboot cooperate with other "bioses"
by Michal Widlok 10 Nov '08

10 Nov '08

Hello, I am thinking about trying coreboot on a server (dell 2850) and after reading of some manuals I fall into doubts. My question is how coreboot work with other bioses / firmwares that are usually presented on a server boards? For example on my PE2850 I can see messages (during boot-up) from: 1) Original Bios, 2) RAID controller, 3) BMC controller, 4) Backplane 1, 5) Backplane 2, 6) IPMI. Some of them (BMC, Raid, Backplane) can be even upgraded from OS or boot disk. Also some of them have a setup screen similar to original Bios, that can be accessed by special key press. How coreboot will handle them? Next problem is that I am not sure how to find Bios flash memory on mainboard. The are about 3 candidates (flash chips with stickers), however they are all very similar - how to pick the right one? I never though about coreboot before, however some time ago I have seen a Work In Progress for dell 1850 (very similar to mine) and decide learn something about it. Was coreboot really installed on this dell? If yes then how physically it was done? Best Regards, Michael W.

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SeaBIOS question and cross compilation fix.
by Stefan Reinauer 10 Nov '08

10 Nov '08

Hi, Kevin, I am experimenting with v3 and better integration of SeaBIOS and coreboot. For that, I am copying a SeaBIOS image to the FSEG during coreboot's VGA init code. In addition I added another 32bit entry point to SeaBIOS at 0xffc0 (Thus, living at 0xfffc0) int copy_systembios(void) { struct mem_file archive, result; int ret; init_archive(&archive); ret = find_file(&archive, "bios.bin", &result); if (ret) { printk(BIOS_WARNING, "No legacy bios found.\n"); return -1; } process_file(&result, (void *)0xf0000); return 0; } void run_bios(struct device *dev, unsigned long addr) { int i; void (*init_systembios)(void) = (void *)0xfffc0; copy_systembios(); init_systembios(); real_mode_switch_call_vga((dev->bus->secondary << 8) | dev->path.pci.devfn); } Now, the entry point looks like this: diff -ur -x .git seabios2/src/romlayout.S seabios/src/romlayout.S --- seabios2/src/romlayout.S 2008-11-06 15:46:44.000000000 +0100 +++ seabios/src/romlayout.S 2008-11-01 11:38:06.000000000 +0100 @@ -544,6 +544,18 @@ ORG 0xff54 IRQ_ENTRY_ARG 05 +.code32 + ORG 0xffc0 // coreboot Entry Point + mov $0x3f8, %dx + mov $0x44, %al + outb %al, %dx // print + call _code32__init + mov $0x3f8, %dx + mov $0x45, %al + outb %al, %dx + ret +.code16gcc + ORG 0xfff0 // Power-up Entry Point ljmpw $SEG_BIOS, $post16 And _init looks like this (simplified): void VISIBLE32 _init() { outb('@', 0x3f8); } Unfortunately, this does not seem to work. The machine jumps somewhere else and will triple fault eventually. The outb to serial console in the assembler entry point work fine. If I comment out the call to _code32__init, the function also returns nicely. (printing "DE" on the way. But as soon as I leave the call in, seabios crashes after printing "D" It does not even print the @. Any hints? Also, find attached a patch to allow cross compilation of SeaBIOS and make it work with systems where /bin/echo does not know the option -e Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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Max pci bus number?
by Kevin O'Connor 09 Nov '08

09 Nov '08

How can I find the maximum PCI bus number of the system? The PCI bios calls need to be able to return this information. It also helps when scanning for pci devices, because then we don't have to check for all 256 possible buses. Right now, SeaBIOS has a compile time definition for the max, but that is awkward and it can lead to hard to debug failures. Ideas? -Kevin

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r3738 build service
by coreboot information 09 Nov '08

09 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3738 to the coreboot source repository and caused the following changes: Change Log: i945.h: Add some more comments, align data for better readability (trivial). Also, add missing C1DRA2 #define (as per public datasheet). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of digitallogic:adl855pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3738&device=adl855pc&vendo… Compilation of sunw:ultra40 has been fixed Compilation of supermicro:x6dai_g has been fixed If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3738 - trunk/coreboot-v2/src/northbridge/intel/i945
by svn＠coreboot.org 09 Nov '08

09 Nov '08

Author: uwe Date: 2008-11-09 11:57:26 +0100 (Sun, 09 Nov 2008) New Revision: 3738 Modified: trunk/coreboot-v2/src/northbridge/intel/i945/i945.h Log: i945.h: Add some more comments, align data for better readability (trivial). Also, add missing C1DRA2 #define (as per public datasheet). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/northbridge/intel/i945/i945.h =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/i945.h 2008-11-08 01:51:32 UTC (rev 3737) +++ trunk/coreboot-v2/src/northbridge/intel/i945/i945.h 2008-11-09 10:57:26 UTC (rev 3738) @@ -31,15 +31,15 @@ #define X60BAR 0x60 /* Northbridge BARs */ -#define DEFAULT_PCIEXBAR 0xf0000000 +#define DEFAULT_PCIEXBAR 0xf0000000 /* 4 KB per PCIe device */ #define DEFAULT_X60BAR 0xfed13000 -#define DEFAULT_MCHBAR 0xfed14000 -#define DEFAULT_DMIBAR 0xfed18000 -#define DEFAULT_EPBAR 0xfed19000 +#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ -#define GGC 0x52 +#define GGC 0x52 /* GMCH Graphics Control */ -#define DEVEN 0x54 +#define DEVEN 0x54 /* Device Enable */ #define DEVEN_D0F0 (1 << 0) #define DEVEN_D1F0 (1 << 1) #define DEVEN_D2F0 (1 << 3) @@ -48,22 +48,22 @@ #define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 ) #endif -#define PAM0 0x90 -#define PAM1 0x91 -#define PAM2 0x92 -#define PAM3 0x93 -#define PAM4 0x94 -#define PAM5 0x95 -#define PAM6 0x96 +#define PAM0 0x90 +#define PAM1 0x91 +#define PAM2 0x92 +#define PAM3 0x93 +#define PAM4 0x94 +#define PAM5 0x95 +#define PAM6 0x96 -#define LAC 0x97 /* Legacy Access Control */ -#define TOLUD 0x9c /* Top of Low Used Memory */ -#define SMRAM 0x9d -#define ESMRAM 0x9e +#define LAC 0x97 /* Legacy Access Control */ +#define TOLUD 0x9c /* Top of Low Used Memory */ +#define SMRAM 0x9d /* System Management RAM Control */ +#define ESMRAM 0x9e /* Extended System Management RAM Control */ -#define TOM 0xa0 +#define TOM 0xa0 -#define SKPAD 0xdc /* Scratchpad */ +#define SKPAD 0xdc /* Scratchpad Data */ /* Device 0:1.0 PCI configuration space (PCI Express) */ @@ -72,7 +72,7 @@ /* Device 0:2.0 PCI configuration space (Graphics Device) */ -#define GCFC 0xf0 /* Graphics Clock Frequency and Gating Control */ +#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */ /* @@ -119,6 +119,7 @@ #define C1DRB2 0x182 /* 8bit */ #define C1DRB3 0x183 /* 8bit */ #define C1DRA0 0x188 /* 8bit */ +#define C1DRA2 0x189 /* 8bit */ #define C1DCLKDIS 0x18c /* 8bit */ #define C1BNKARC 0x18e /* 16bit */ #define C1DRT0 0x190 /* 32bit */ @@ -152,7 +153,7 @@ #define DQSMT 0x2f4 /* 16bit */ #define RCVENMT 0x2f8 /* 32bit */ -#define C0R0B00DQST 0x300 /* 64bit */ +#define C0R0B00DQST 0x300 /* 64bit */ #define C0WL0REOST 0x340 /* 8bit */ #define C0WL1REOST 0x341 /* 8bit */ @@ -162,7 +163,7 @@ #define C0WDLLCMC 0x36c /* 32bit */ #define C0HCTC 0x37c /* 8bit */ -#define C1R0B00DQST 0x380 /* 64bit */ +#define C1R0B00DQST 0x380 /* 64bit */ #define C1WL0REOST 0x3c0 /* 8bit */ #define C1WL1REOST 0x3c1 /* 8bit */

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Help test SeaBIOS option roms
by Kevin O'Connor 09 Nov '08

09 Nov '08

Hi, I just finished adding initial support for option rom deployment in SeaBIOS. The idea is to allow SeaBIOS to be able to scan and run option roms without assistance from coreboot. Unfortunately, I don't have any PCI cards with option roms on them. It would help if others could test this and report how it works. The latest code is in git. To pull it, run: git clone git://git.linuxtogo.org/home/kevin/seabios.git I've also placed a pre-compiled payload at: http://linuxtogo.org/~kevin/SeaBIOS/bios.bin.elf-20081108 If you have an on-board VGA at BDF 0x0100 and build the vga rom at 0xfffc0000 (as is common on coreboot-v2 with via motherboards), then you can also use: http://linuxtogo.org/~kevin/SeaBIOS/bios.bin.elf-20081108-viavga The option rom deployment code is at: http://git.linuxtogo.org/?p=kevin/seabios.git;a=blob;f=src/optionroms.c;h=a… I'm a little concerned on how to ensure that the option rom is mapped to an area not cached and not in conflict with something else. So, I ended up mapping it to just above memory. (I only map it long enough to copy it.) Hopefully this will work out okay. In order to support on-board option roms, I've added an ability to allow devices (with a specified Bus/Dev/Fn) to have option roms pulled from flash instead of PCI space. This is in keeping with how coreboot-v2 handles built-in option roms. (For coreboot-v3, I'd like to add in LAR parsing.) Finally, if you want to try building from source, please be sure to update config.h and set CONFIG_COREBOOT and CONFIG_DEBUG_SERIAL, and clear CONFIG_OPTIONROMS_DEPLOYED. Thoughts? -Kevin

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[PATCH] v3: Unbreak x86emu
by Carl-Daniel Hailfinger 09 Nov '08

09 Nov '08

Hi, the following change broke x86emu compilation on all v3 targets. > r965 | rminnich > [...] > Also make the vm86 stuff use the SRC instead of OBJ names so we can > see it in ks > cope. > > Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> > Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Fix the issue.OBJ->SRC conversions are a bit tricky to get right. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Attached for gmail users. Index: corebootv3-x86emu_makefile/util/x86emu/Makefile =================================================================== --- corebootv3-x86emu_makefile/util/x86emu/Makefile (Revision 988) +++ corebootv3-x86emu_makefile/util/x86emu/Makefile (Arbeitskopie) @@ -23,7 +23,7 @@ VM86_SRC = vm86.c vm86_gdt.c ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y) -LIBX86EMU_SRC=$(X86EMU_SRC) $(BIOSEMU_SRC) +LIBX86EMU_SRC=$(patsubst %,x86emu/%,$(X86EMU_SRC)) $(BIOSEMU_SRC) endif ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_VM86),y) -- http://www.hailfinger.org/

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coreboot November 2008