Re: [coreboot] alix2c3 LEDs and mode switch

[Roman Yeryomin]

On Fri, Nov 7, 2008 at 8:47 PM, Marc Jones  wrote:
> I think I came into this discussion late with getting my email switched over.
> What are you trying to accomplish and where/what do you want to control the LED from?

There is fully functional linux kernel driver (see attachment) which
works flawlessly with tinybios (alix factory bios).
I want to indicate software status events (for example network is up
or down) using custom scripts and driver I've mentioned.

Roman

alix2c3 LEDs and mode switch

[ron minnich]

I don't have one of these boards, I may order one this weekend.

Can you tell me a bit more about these LEDs, how connected, which
GPIOs, and so forth?

ron

alix2c3 LEDs and mode switch

[Roman Yeryomin]

On Fri, Nov 7, 2008 at 11:07 PM, ron minnich  wrote:
> I don't have one of these boards, I may order one this weekend.
>
> Can you tell me a bit more about these LEDs, how connected, which
> GPIOs, and so forth?

Not sure about their connection but there is some information about it
in schematics document on page 6 (attached alix2c.pdf).
GPIOs are 6,25,27 (see my first post and/or attached alix2.pdf page 18).

Roman

alix2c3 LEDs and mode switch

[Marc Jones]

----- Original Message ----
> From: Roman Yeryomin 
> To: Marc Jones ; [e-mail]
> Sent: Friday, November 7, 2008 12:56:26 PM
> Subject: Re: [coreboot] alix2c3 LEDs and mode switch
>
> On Fri, Nov 7, 2008 at 8:47 PM, Marc Jones wrote:
> > I think I came into this discussion late with getting my email switched over.
> > What are you trying to accomplish and where/what do you want to control the
>
> LED from?
>
> There is fully functional linux kernel driver (see attachment) which
> works flawlessly with tinybios (alix factory bios).
> I want to indicate software status events (for example network is up
> or down) using custom scripts and driver I've mentioned.
> #define ALIX_LED1_PORT        (0x6100)

The scripts and driver should get the GPIO IO address from the 5536 PCI cfg header instead of hard coding the address.
coreboot can allocate the GPIO space to any address. A quick try could be made by checking lspci.

GPIO is BAR1 (offset 0x14) in the 5536.

You can find some example GPIO setup in coreboot at src/southbridge/amd/cs5536/cs5536.c. It uses GPIOs for UARTs.

Marc

alix2c3 LEDs and mode switch

[Roman Yeryomin]

On Fri, Nov 7, 2008 at 11:47 PM, Marc Jones  wrote:
> > On Fri, Nov 7, 2008 at 8:47 PM, Marc Jones wrote:
> > > I think I came into this discussion late with getting my email switched over.
> > > What are you trying to accomplish and where/what do you want to control the
> >
> > LED from?
> >
> > There is fully functional linux kernel driver (see attachment) which
> > works flawlessly with tinybios (alix factory bios).
> > I want to indicate software status events (for example network is up
> > or down) using custom scripts and driver I've mentioned.
> > #define ALIX_LED1_PORT        (0x6100)
>
> The scripts and driver should get the GPIO IO address from the 5536 PCI cfg header instead of hard coding the address.
> coreboot can allocate the GPIO space to any address. A quick try could be made by checking lspci.
> GPIO is BAR1 (offset 0x14) in the 5536.

hmm.. I din't think the address could change. So is it this? wrong
address? Here is my lspci

00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode
companion] Host Bridge (rev 33)
        Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode
companion] Host Bridge
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx-
        Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium
> TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

Latency: 64
        Region 0: I/O ports at ac1c [size=4]

00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD]
Geode LX AES Security Block
        Subsystem: Advanced Micro Devices [AMD] Geode LX AES Security Block
        Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx-
        Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium
> TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

Interrupt: pin A routed to IRQ 9
        Region 0: Memory at febf0000 (32-bit, non-prefetchable) [size=16K]

00:09.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
        Subsystem: VIA Technologies, Inc. Device 0106
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr+ Stepping+ SERR+ FastB2B- DisINTx-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium
> TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

Latency: 64 (750ns min, 2000ns max), Cache Line Size: 64 bytes
        Interrupt: pin A routed to IRQ 10
        Region 0: I/O ports at 1000 [size=256]
        Region 1: Memory at febfa000 (32-bit, non-prefetchable) [size=256]
        Capabilities: [40] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0+,D1+,D2+,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
        Kernel driver in use: via-rhine

00:0a.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
        Subsystem: VIA Technologies, Inc. Device 0106
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr+ Stepping+ SERR+ FastB2B- DisINTx-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium
> TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

Latency: 64 (750ns min, 2000ns max), Cache Line Size: 64 bytes
        Interrupt: pin A routed to IRQ 11
        Region 0: I/O ports at 1400 [size=256]
        Region 1: Memory at febfb000 (32-bit, non-prefetchable) [size=256]
        Capabilities: [40] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0+,D1+,D2+,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
        Kernel driver in use: via-rhine

00:0b.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
        Subsystem: VIA Technologies, Inc. Device 0106
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr+ Stepping+ SERR+ FastB2B- DisINTx-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium
> TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

Latency: 64 (750ns min, 2000ns max), Cache Line Size: 64 bytes
        Interrupt: pin A routed to IRQ 11
        Region 0: I/O ports at 1800 [size=256]
        Region 1: Memory at febfc000 (32-bit, non-prefetchable) [size=256]
        Capabilities: [40] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0+,D1+,D2+,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
        Kernel driver in use: via-rhine

00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode
companion] ISA (rev 03)
        Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA
        Control: I/O+ Mem- BusMaster- SpecCycle+ MemWINV- VGASnoop-
ParErr+ Stepping- SERR- FastB2B- DisINTx-
        Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium
> TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

Region 0: I/O ports at 24b0 [size=8]
        Region 1: I/O ports at 1c00 [size=256]
        Region 2: I/O ports at 2400 [size=64]
        Region 3: I/O ports at 2480 [size=32]
        Region 4: I/O ports at 2000 [size=128]
        Region 5: I/O ports at 2440 [size=64]

00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode
companion] IDE (rev 01) (prog-if 80 [Master])
        Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE
        Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop-
ParErr+ Stepping- SERR- FastB2B- DisINTx-
        Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium
> TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

Region 0: [virtual] Memory at 000001f0 (32-bit,
non-prefetchable) [disabled] [size=8]
        Region 1: [virtual] Memory at 000003f0 (type 3,
non-prefetchable) [disabled] [size=1]
        Region 2: [virtual] Memory at 00000170 (32-bit,
non-prefetchable) [disabled] [size=8]
        Region 3: [virtual] Memory at 00000370 (type 3,
non-prefetchable) [disabled] [size=1]
        Region 4: I/O ports at 24a0 [size=16]

00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD]
CS5536 [Geode companion] Audio (rev 01)
        Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio
        Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop-
ParErr+ Stepping- SERR- FastB2B- DisINTx-
        Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium
> TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

Interrupt: pin B routed to IRQ 10
        Region 0: I/O ports at 2080 [size=128]

00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode
companion] OHC (rev 02) (prog-if 10 [OHCI])
        Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC
        Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx-
        Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium
> TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

Interrupt: pin D routed to IRQ 11
        Region 0: Memory at febf7000 (32-bit, non-prefetchable) [size=4K]
        Capabilities: [40] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0+,D1-,D2-,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode
companion] EHC (rev 02) (prog-if 20 [EHCI])
        Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC
        Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx-
        Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium
> TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

Interrupt: pin D routed to IRQ 11
        Region 0: Memory at febf8000 (32-bit, non-prefetchable) [size=4K]
        Capabilities: [40] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0+,D1-,D2-,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> You can find some example GPIO setup in coreboot at src/southbridge/amd/cs5536/cs5536.c. It uses GPIOs for UARTs.

Yes, this is where I looked when trying this (this is for LED1):

outl(GPIOL_6_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
   outl(GPIOL_6_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
   outl(GPIOL_6_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
   outl(GPIOL_6_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);

Roman

alix2c3 LEDs and mode switch

[Marc Jones]

----- Original Message ----
> From: Roman Yeryomin 
> To: Marc Jones 
> Cc: [e-mail]
> Sent: Saturday, November 8, 2008 9:25:54 AM
> Subject: Re: [coreboot] alix2c3 LEDs and mode switch
>
> On Fri, Nov 7, 2008 at 11:47 PM, Marc Jones wrote:
> > > On Fri, Nov 7, 2008 at 8:47 PM, Marc Jones wrote:
> > > > I think I came into this discussion late with getting my email switched
>
> over.
> > > > What are you trying to accomplish and where/what do you want to control the
> > >
> > > LED from?
> > >
> > > There is fully functional linux kernel driver (see attachment) which
> > > works flawlessly with tinybios (alix factory bios).
> > > I want to indicate software status events (for example network is up
> > > or down) using custom scripts and driver I've mentioned.
> > > #define ALIX_LED1_PORT        (0x6100)
> >
> > The scripts and driver should get the GPIO IO address from the 5536 PCI cfg
>
> header instead of hard coding the address.
> > coreboot can allocate the GPIO space to any address. A quick try could be made
>
> by checking lspci.
> > GPIO is BAR1 (offset 0x14) in the 5536.
>
> hmm.. I din't think the address could change. So is it this? wrong
> address? Here is my lspci
> 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode
> companion] ISA (rev 03)
>         Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA
>         Control: I/O+ Mem- BusMaster- SpecCycle+ MemWINV- VGASnoop-
> ParErr+ Stepping- SERR- FastB2B- DisINTx-
>         Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium
> > TAbort- SERR-
>     Region 0: I/O ports at 24b0 [size=8]
>     Region 1: I/O ports at 1c00 [size=256]
>     Region 2: I/O ports at 2400 [size=64]
>     Region 3: I/O ports at 2480 [size=32]
>     Region 4: I/O ports at 2000 [size=128]
>     Region 5: I/O ports at 2440 [size=64]

Region 1: 1C00 is what you want to use. The driver should check that BAR and use that address.

Marc

alix2c3 LEDs and mode switch

[Roman Yeryomin]

On Sat, Nov 8, 2008 at 6:40 PM, Marc Jones  wrote:
> > On Fri, Nov 7, 2008 at 11:47 PM, Marc Jones wrote:
> > > GPIO is BAR1 (offset 0x14) in the 5536.
> >
> > 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode
> > companion] ISA (rev 03)
> >         Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA
> >         Control: I/O+ Mem- BusMaster- SpecCycle+ MemWINV- VGASnoop-
> > ParErr+ Stepping- SERR- FastB2B- DisINTx-
> >         Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium
> > > TAbort- SERR-
> >     Region 0: I/O ports at 24b0 [size=8]
> >     Region 1: I/O ports at 1c00 [size=256]
> >     Region 2: I/O ports at 2400 [size=64]
> >     Region 3: I/O ports at 2480 [size=32]
> >     Region 4: I/O ports at 2000 [size=128]
> >     Region 5: I/O ports at 2440 [size=64]
>
> Region 1: 1C00 is what you want to use. The driver should check that BAR and use that address.

ok, I will try it
but this is only one led, what about others? their ports will change
respectively? 6100->1c00, 6180->1c80 ?
and what about this? is it needed?
outl(GPIOL_6_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
outl(GPIOL_6_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
outl(GPIOL_6_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
outl(GPIOL_6_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);

Roman

alix2c3 LEDs and mode switch

[Peter Stuge]

Roman Yeryomin wrote:
> > Region 1: 1C00 is what you want to use. The driver should check
> > that BAR and use that address.
>
> ok, I will try it
> but this is only one led, what about others? their ports will change
> respectively? 6100->1c00, 6180->1c80 ?

The 5536 doesn't have a single port per GPIO. Please have a look at
the 5536 GPIO documentation to learn how they work. I think it is
explained well:

http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33238G_cs5536_...

See 6.16 GPIO Device Register Descriptions

The GPIO I/O Offset should be added to what is read from the ISA
bridge BAR1, 0x1c00 in this case.
> and what about this? is it needed?
> outl(GPIOL_6_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
> outl(GPIOL_6_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
> outl(GPIOL_6_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
> outl(GPIOL_6_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);

Yes. The PDF explains how these registers work.

//Peter