coreboot November 2008

coreboot@coreboot.org

76 participants
490 discussions

[PATCH 2/5] artecgroup/dbe61: Use dbe61c specific variables and macros instead of generic ones
by Mart Raudsepp 13 Nov '08

13 Nov '08

artecgroup/dbe61: Use dbe61c specific variables and macros instead of generic ones This is in preparation of dbe61a handling addition. Uses DIMM_DBE61C and DIMM_EMPTY instead of generic DIMM0/DIMM1, and spd_table_dbe61c instead of spd_table. Also removes a completely unused smb_devices structure definition. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- mainboard/artecgroup/dbe61/initram.c | 27 ++++++++++++--------------- 1 files changed, 12 insertions(+), 15 deletions(-) diff --git a/mainboard/artecgroup/dbe61/initram.c b/mainboard/artecgroup/dbe61/initram.c index 8c84792..4a89247 100644 --- a/mainboard/artecgroup/dbe61/initram.c +++ b/mainboard/artecgroup/dbe61/initram.c @@ -35,8 +35,8 @@ #define MANUALCONF 0 /* Do automatic strapped PLL config */ #define PLLMSRHI 0x00001490 /* manual settings for the PLL */ #define PLLMSRLO 0x02000030 -#define DIMM0 ((u8) 0xA0) -#define DIMM1 ((u8) 0xA2) +#define DIMM_DBE61C ((u8) 0xA0) +#define DIMM_EMPTY ((u8) 0xA2) struct spd_entry { u8 address; @@ -46,7 +46,7 @@ struct spd_entry { /* Save space by using a short list of SPD values used by Geode LX Memory init */ /* Fake SPD for DBE61C - 256MB. Same memory chip, and therefore same SPD entries, as for DBE62. */ /* Micron MT46V32M16 */ -static const struct spd_entry spd_table[] = { +static const struct spd_entry spd_table_dbe61c[] = { {SPD_MEMORY_TYPE, 7}, {SPD_NUM_ROWS, 13}, {SPD_tRFC, 0x4b}, @@ -95,7 +95,7 @@ static const struct spd_entry spd_table_dbe61a[] = { /** * Given an SMBUS device, and an address in that device, return the value of SPD - * for that device. In this mainboard, the only one that can return is DIMM0. + * for that device. In this mainboard, the only one that can return is DIMM_DBE61C. * @param device The device number * @param address The address in SPD rom to return the value of * @returns The value @@ -107,15 +107,15 @@ u8 spd_read_byte(u16 device, u8 address) u8 ret = 0xff; printk(BIOS_DEBUG, "spd_read_byte dev %04x", device); - if (device == DIMM0) { - for (i = 0; i < ARRAY_SIZE(spd_table); i++) { - if (spd_table[i].address == address) { - ret = spd_table[i].data; + if (device == DIMM_DBE61C) { + for (i = 0; i < ARRAY_SIZE(spd_table_dbe61c); i++) { + if (spd_table_dbe61c[i].address == address) { + ret = spd_table_dbe61c[i].data; break; } } - if (i == ARRAY_SIZE(spd_table)) + if (i == ARRAY_SIZE(spd_table_dbe61c)) printk(BIOS_DEBUG, " addr %02x does not exist in SPD table", address); } @@ -143,9 +143,6 @@ static void mb_gpio_init(void) */ int main(void) { - u8 smb_devices[] = { - DIMM0, DIMM1 - }; printk(BIOS_DEBUG, "Hi there from stage1\n"); post_code(POST_START_OF_MAIN); @@ -158,16 +155,16 @@ int main(void) pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO); printk(BIOS_DEBUG, "done pll reset\n"); - cpu_reg_init(0, DIMM0, DIMM1, DRAM_UNTERMINATED); + cpu_reg_init(0, DIMM_DBE61C, DIMM_EMPTY, DRAM_UNTERMINATED); printk(BIOS_DEBUG, "done cpu reg init\n"); sdram_set_registers(); printk(BIOS_DEBUG, "done sdram set registers\n"); - sdram_set_spd_registers(DIMM0, DIMM1); + sdram_set_spd_registers(DIMM_DBE61C, DIMM_EMPTY); printk(BIOS_DEBUG, "done sdram set spd registers\n"); - sdram_enable(DIMM0, DIMM1); + sdram_enable(DIMM_DBE61C, DIMM_EMPTY); printk(BIOS_DEBUG, "done sdram enable\n"); /* Check low memory */ -- 1.6.0.2

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Re: [coreboot] r1009 - in coreboot-v3: mainboard/kontron/986lcd-m northbridge/intel/i945 southbridge/intel/i82801gx
by Peter Stuge 13 Nov '08

13 Nov '08

svn(a)coreboot.org wrote: > +++ coreboot-v3/mainboard/kontron/986lcd-m/Makefile 2008-11-12 23:09:42 UTC (rev 1009) > @@ -28,6 +28,18 @@ > INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ > $(src)/northbridge/intel/i945/raminit.c \ > > +STAGE2_CHIPSET_SRC=\ > + $(src)/southbridge/intel/i82801gx/ac97.c \ > + $(src)/southbridge/intel/i82801gx/lpc.c \ > + $(src)/southbridge/intel/i82801gx/nic.c \ > + $(src)/southbridge/intel/i82801gx/pci.c \ > + $(src)/southbridge/intel/i82801gx/pcie.c \ > + $(src)/southbridge/intel/i82801gx/sata.c \ > + $(src)/southbridge/intel/i82801gx/smbus.c \ > + $(src)/southbridge/intel/i82801gx/usb_ehci.c \ > + $(src)/southbridge/intel/i82801gx/usb.c \ > + $(src)/southbridge/intel/i82801gx/watchdog.c > +# $(src)/southbridge/intel/i82801gx/libsmbus.c \ We must fix this design. This list of files has to go in southbridge/intel/i82801gx/ somewhere and mainboard/ Makefiles should just reference the right south Makefile per Kconfig settings, preferably using one common rule. Did we consider using the scheme that Linux uses to pick which objects to build? STAGE2_CHIPSET_SRC-$(CONFIG_INTEL_I82801GX) += srcfiles in south/ and always include every Makefile in every build. (Maybe that's done anyway?) > +++ coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-11-12 23:09:42 UTC (rev 1009) > @@ -181,6 +181,13 @@ > pci@1f,0{/* which ich? */ > /config/("southbridge/intel/i82801gx/ich7m_dh_lpc.dts"); > }; > + pci@1f,2{ > + /config/("southbridge/intel/i82801gx/sata.dts"); > + }; > + pci@1f,3{ > + /config/("southbridge/intel/i82801gx/smbus.dts"); > + }; I'd like the same principle for dts. More reuse and one single include line pulling in whatever is needed for one complex device. > -static void pci_domain_set_resources(struct device * dev) > +static void I945_pci_domain_set_resources(struct device * dev) This is just one example, there are many cases of copypaste like this. Is it really neccessary? I think the design has failed if we can't reuse this kind of code. > /* Report the memory regions */ > - ram_resource(dev, 3, 0, 640); > - ram_resource(dev, 4, 768, (tolmk - 768)); > + i945_ram_resource(dev, 3, 0, 640); > + i945_ram_resource(dev, 4, 768, (tolmk - 768)); > if (tomk > 4 * 1024 * 1024) { > - ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024); > + i945_ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024); So what's the difference? I just cut the i945_ram_resource() changes out, but.. > Modified: coreboot-v3/southbridge/intel/i82801gx/Makefile > =================================================================== > --- coreboot-v3/southbridge/intel/i82801gx/Makefile 2008-11-12 22:43:50 UTC (rev 1008) > +++ coreboot-v3/southbridge/intel/i82801gx/Makefile 2008-11-12 23:09:42 UTC (rev 1009) > @@ -24,18 +24,6 @@ > STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82801gx/i82801gx.c > > STAGE2_CHIPSET_SRC += \ > - $(src)/southbridge/intel/i82801gx/ac97.c \ > - $(src)/southbridge/intel/i82801gx/ide.c \ > - $(src)/southbridge/intel/i82801gx/lpc.c \ > - $(src)/southbridge/intel/i82801gx/nic.c \ > - $(src)/southbridge/intel/i82801gx/pci.c \ > - $(src)/southbridge/intel/i82801gx/pcie.c \ > - $(src)/southbridge/intel/i82801gx/sata.c \ > - $(src)/southbridge/intel/i82801gx/smbus.c \ > - $(src)/southbridge/intel/i82801gx/usb_ehci.c \ > - $(src)/southbridge/intel/i82801gx/usb.c \ > - $(src)/southbridge/intel/i82801gx/watchdog.c > -# $(src)/southbridge/intel/i82801gx/libsmbus.c \ This has to change back. Any solution that does not keep this list of files in southbridge/ is plain wrong. Sorry. > +++ coreboot-v3/southbridge/intel/i82801gx/ac97.c 2008-11-12 23:09:42 UTC (rev 1009) > +void i82801gx_enable(struct device * dev); What? This function has to get a better name. > +void i82801gx_enable(struct device * dev); Here it is again. It appears a few more times. //Peter

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Re: [coreboot] r1009 - in coreboot-v3: mainboard/kontron/986lcd-m northbridge/intel/i945 southbridge/intel/i82801gx
by Stefan Reinauer 13 Nov '08

13 Nov '08

svn(a)coreboot.org wrote: > Fewer errors. The weird part: I had to move all the i82801gx south files to be compiled to the mainboard. > > Why? Because the board doesn't use ide support. So you can't compile that in, it's not in the dts. > Oh, the dts is not capable of marking a device unused? This looks like a major shortcoming. I thought we had a discussion about a disabled flag in the past that would allow disabling a device. But: The board uses IDE support. Only a quick glance at the DTS stuff, but it's confusing me: > Modified: coreboot-v3/mainboard/kontron/986lcd-m/dts > =================================================================== > --- coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-11-12 22:43:50 UTC (rev 1008) > +++ coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-11-12 23:09:42 UTC (rev 1009) > @@ -181,6 +181,13 @@ > pci@1f,0{/* which ich? */ > /config/("southbridge/intel/i82801gx/ich7m_dh_lpc.dts"); > }; > + pci@1f,2{ > + /config/("southbridge/intel/i82801gx/sata.dts"); > + }; > + pci@1f,3{ > + /config/("southbridge/intel/i82801gx/smbus.dts"); > + }; > + > }; > ioport@2e { > /config/("superio/winbond/w83627thg/dts"); > > So, the generic ICH7 device structure is described in the mainboard dts? We need to mention in the mainboard dts that there's 1f,0 and 1f,2 and which config it uses? That's a rather generic device description > Modified: coreboot-v3/southbridge/intel/i82801gx/sata.dts > =================================================================== > --- coreboot-v3/southbridge/intel/i82801gx/sata.dts 2008-11-12 22:43:50 UTC (rev 1008) > +++ coreboot-v3/southbridge/intel/i82801gx/sata.dts 2008-11-12 23:09:42 UTC (rev 1009) > @@ -20,4 +20,9 @@ > > { > device_operations = "i82801gx_sata_normal_driver"; > + ide_legacy_combined = "0"; > + ide_enable_primary = "0"; > + ide_enable_secondary = "0"; > + sata_ahci = "0"; > }; > + > --- and --- the mainboard specific variables are in the generic code? Now, this is definitely very unexpected. Is this a shortcoming in our DTS/DTC concept? Something's really fishy here. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

4 3

r1013 - coreboot-v3/arch/x86/intel/core2
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: hailfinger Date: 2008-11-13 02:53:55 +0100 (Thu, 13 Nov 2008) New Revision: 1013 Modified: coreboot-v3/arch/x86/intel/core2/stage0.S Log: Kill v2 leftovers. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/arch/x86/intel/core2/stage0.S =================================================================== --- coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-13 01:28:32 UTC (rev 1012) +++ coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-13 01:53:55 UTC (rev 1013) @@ -64,7 +64,6 @@ movw %ax, %gs cache_as_ram: -#if USE_FALLBACK_IMAGE == 1 port80_post(0x20) @@ -129,7 +128,6 @@ //movl $0x23322332, %eax xorl %eax, %eax rep stosl -#endif /* Enable Cache As RAM mode by disabling cache */ movl %cr0, %eax

1 0

Re: [coreboot] Help test SeaBIOS option roms
by Jeka 12 Nov '08

12 Nov '08

Hello, Kevin! I've tested both new SeaBioses(yours precompiled and compiled by me) on Asus A8N-E with PCI Video Card. It doesn't work to me... Video card initialization works fine I can see first hello string (SeaBios...), but there is no boot devices choice and so on... Keyboard doesn't work too. Old SeaBios copied VGA rom from memory and worked fine. I've installed XP without ACPI. Main problem was that there wasn't any pci-devices(network, audio...) in XP, but Fedora could see it. Another problem was with PCI-Express video cards (8600GT, 2600XT). Does PCi-E support in SeaBios

2 1

[PATCH] v3: add a stack checker
by Carl-Daniel Hailfinger 12 Nov '08

12 Nov '08

We are woefully unaware about how much stack v3 really uses. This is a complete rewrite of my earlier stack checker. It works for CAR and RAM, has better abstraction and actually gives us nice results. The stack checker is default off due to its rather measurable impact on boot speed. Diagnostic messages are printed on first initialization, directly after RAM init and directly before passing control to the payload. Sample qemu log is attached. Extract from that log follows: coreboot-3.0.986 Fri Nov 7 04:04:37 CET 2008 starting... (console_loglevel=8) Initial lowest stack is 0x0008fe98 Choosing fallback boot. [...] Done RAM init code After RAM init, lowest stack is 0x0008fe30 Done printk() buffer move [...] LAR: load_file_segments: Failed for normal/payload Before handoff to payload, lowest stack is 0x0008bf50 FATAL: No usable payload found. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Patch attached as well for gmail users. Index: corebootv3-stackcheck/include/globalvars.h =================================================================== --- corebootv3-stackcheck/include/globalvars.h (Revision 986) +++ corebootv3-stackcheck/include/globalvars.h (Arbeitskopie) @@ -59,6 +59,10 @@ struct sys_info sys_info; /* has the spd hardware been set up? */ int spd_inited; + int ram_available; +#ifdef CONFIG_CHECK_STACK_USAGE + void *loweststack; +#endif }; #endif /* GLOBALVARS_H */ Index: corebootv3-stackcheck/include/arch/x86/cpu.h =================================================================== --- corebootv3-stackcheck/include/arch/x86/cpu.h (Revision 986) +++ corebootv3-stackcheck/include/arch/x86/cpu.h (Arbeitskopie) @@ -265,6 +265,7 @@ EXPORT_SYMBOL(bottom_of_stack); struct global_vars * global_vars(void); EXPORT_SYMBOL(global_vars); +void check_stack(void); #define CAR_STACK_BASE (CONFIG_CARBASE + CONFIG_CARSIZE - 4) #define RAM_STACK_BASE 0x88ffc @@ -278,6 +279,8 @@ #else #define CAR_STACK_SIZE (CONFIG_CARSIZE - 4) #endif +/* To be honest, this limit is arbitrary and only used for stack checking. */ +#define RAM_STACK_SIZE (65536 - 4) /* resource maps. These started out as special for the K8 but now have more general usage */ /* it's not totally clear that the type and union are a great idea, but see the v2 code: Index: corebootv3-stackcheck/lib/console.c =================================================================== --- corebootv3-stackcheck/lib/console.c (Revision 986) +++ corebootv3-stackcheck/lib/console.c (Arbeitskopie) @@ -150,6 +150,9 @@ i += vtxprintf(console_tx_byte, (void *)0, fmt, args); va_end(args); +#ifdef CONFIG_CHECK_STACK_USAGE + check_stack(); +#endif return i; } Index: corebootv3-stackcheck/arch/x86/Kconfig =================================================================== --- corebootv3-stackcheck/arch/x86/Kconfig (Revision 986) +++ corebootv3-stackcheck/arch/x86/Kconfig (Arbeitskopie) @@ -227,4 +227,13 @@ help Test the CAR area after it has been set up. +config CHECK_STACK_USAGE + bool "Check stack usage" + default n + help + Continuously monitor stack usage and keep statistics. + The monitoring code is invoked from printk because printk is + a leaf function and consumes quite a bit of stack for itself. + This slows down booting a LOT. + endmenu Index: corebootv3-stackcheck/arch/x86/stage1.c =================================================================== --- corebootv3-stackcheck/arch/x86/stage1.c (Revision 986) +++ corebootv3-stackcheck/arch/x86/stage1.c (Arbeitskopie) @@ -105,6 +105,28 @@ } +#ifdef CONFIG_CHECK_STACK_USAGE +/* STACKFILL_BYTE could be a special value like 0x6b. Just make sure the stage0 + * code fills the complete CAR area with it. And the stack switching needs to + * overwrite the unused parts of the stack with STACKFILL_BYTE as well. + */ +#define STACKFILL_BYTE 0x0 +void check_stack() +{ + unsigned long stacksize, i; + char *lowestaddr; + if (global_vars()->ram_available) + stacksize = RAM_STACK_SIZE; + else + stacksize = CAR_STACK_SIZE; + lowestaddr = bottom_of_stack() - stacksize; + for (i = 0; i < stacksize; i++) + if (lowestaddr[i] != STACKFILL_BYTE) + break; + global_vars()->loweststack = lowestaddr + i; +} +#endif + void dump_mem_range(int msg_level, unsigned char *buf, int size) { int i; @@ -194,6 +216,10 @@ */ console_init(); +#ifdef CONFIG_CHECK_STACK_USAGE + printk(BIOS_DEBUG, "Initial lowest stack is %p\n", + global_vars()->loweststack); +#endif if (bist!=0) { printk(BIOS_INFO, "BIST FAILED: %08x", bist); die(""); @@ -227,6 +253,10 @@ die("Failed RAM init code\n"); printk(BIOS_DEBUG, "Done RAM init code\n"); +#ifdef CONFIG_CHECK_STACK_USAGE + printk(BIOS_DEBUG, "After RAM init, lowest stack is %p\n", + global_vars()->loweststack); +#endif /* Switch the stack location from CAR to RAM, rebuild the stack, * disable CAR and continue at stage1_phase3(). This is all wrapped in @@ -299,6 +329,9 @@ mem->map[0].type = LB_MEM_RAM; #endif /* CONFIG_PAYLOAD_ELF_LOADER */ + /* Provide an easy way to check whether RAM is available. */ + global_vars()->ram_available = 1; + // location and size of image. init_archive(&archive); @@ -318,6 +351,10 @@ #endif /* CONFIG_PAYLOAD_ELF_LOADER */ entry = load_file_segments(&archive, "normal/payload"); +#ifdef CONFIG_CHECK_STACK_USAGE + printk(BIOS_DEBUG, "Before handoff to payload, lowest stack is %p\n", + global_vars()->loweststack); +#endif if (entry != (void*)-1) { /* Final coreboot call before handing off to the payload. */ mainboard_pre_payload(); -- http://www.hailfinger.org/ coreboot-3.0.986 Fri Nov 7 04:04:37 CET 2008 starting... (console_loglevel=8) Initial lowest stack is 0x0008fe98 Choosing fallback boot. LAR: Attempting to open 'fallback/initram/segment0'. LAR: Start 0xfffc0000 len 0x40000 LAR: seen member normal/option_table@0xfffc0000, size 932 LAR: seen member normal/initram/segment0@0xfffc0400, size 420 LAR: seen member normal/stage2/segment0@0xfffc0600, size 1 LAR: seen member normal/stage2/segment1@0xfffc0660, size 16161 LAR: seen member normal/stage2/segment2@0xfffc45e0, size 311 LAR: seen member bootblock@0xffffafc0, size 20480 LAR: File not found! LAR: Run file fallback/initram/segment0 failed: No such file. Fallback failed. Try normal boot LAR: Attempting to open 'normal/initram/segment0'. LAR: Start 0xfffc0000 len 0x40000 LAR: seen member normal/option_table@0xfffc0000, size 932 LAR: seen member normal/initram/segment0@0xfffc0400, size 420 LAR: CHECK normal/initram/segment0 @ 0xfffc0400 start 0xfffc0450 len 420 reallen 420 compression 0 entry 0x00000040 loadaddress 0x00000000 Entry point is 0xfffc0490 RAM init code started. Nothing to do. printktest1: If the immediately preceding line does not say "Nothing to do.", then execution did not start at main() Trying absolute call from non-_MAINOBJECT XIP code. Absolute call successful. Done. run_file returns with 0 Done RAM init code After RAM init, lowest stack is 0x0008fe30 Done printk() buffer move LAR: Attempting to open 'normal/stage2/segment0'. LAR: Start 0xfffc0000 len 0x40000 LAR: seen member normal/option_table@0xfffc0000, size 932 LAR: seen member normal/initram/segment0@0xfffc0400, size 420 LAR: seen member normal/stage2/segment0@0xfffc0600, size 1 LAR: CHECK normal/stage2/segment0 @ 0xfffc0600 start 0xfffc0650 len 1 reallen 194788 compression 3 entry 0x00002000 loadaddress 0x0000c44c LAR: Compression algorithm #3 (zeroes) used LAR: Attempting to open 'normal/stage2/segment1'. LAR: Start 0xfffc0000 len 0x40000 LAR: seen member normal/option_table@0xfffc0000, size 932 LAR: seen member normal/initram/segment0@0xfffc0400, size 420 LAR: seen member normal/stage2/segment0@0xfffc0600, size 1 LAR: seen member normal/stage2/segment1@0xfffc0660, size 16161 LAR: CHECK normal/stage2/segment1 @ 0xfffc0660 start 0xfffc06b0 len 16161 reallen 30272 compression 1 entry 0x00002000 loadaddress 0x00002000 LAR: Compression algorithm #1 (lzma) used LAR: Attempting to open 'normal/stage2/segment2'. LAR: Start 0xfffc0000 len 0x40000 LAR: seen member normal/option_table@0xfffc0000, size 932 LAR: seen member normal/initram/segment0@0xfffc0400, size 420 LAR: seen member normal/stage2/segment0@0xfffc0600, size 1 LAR: seen member normal/stage2/segment1@0xfffc0660, size 16161 LAR: seen member normal/stage2/segment2@0xfffc45e0, size 311 LAR: CHECK normal/stage2/segment2 @ 0xfffc45e0 start 0xfffc4630 len 311 reallen 5208 compression 1 entry 0x00002000 loadaddress 0x0000aff4 LAR: Compression algorithm #1 (lzma) used LAR: Attempting to open 'normal/stage2/segment3'. LAR: Start 0xfffc0000 len 0x40000 LAR: seen member normal/option_table@0xfffc0000, size 932 LAR: seen member normal/initram/segment0@0xfffc0400, size 420 LAR: seen member normal/stage2/segment0@0xfffc0600, size 1 LAR: seen member normal/stage2/segment1@0xfffc0660, size 16161 LAR: seen member normal/stage2/segment2@0xfffc45e0, size 311 LAR: seen member bootblock@0xffffafc0, size 20480 LAR: File not found! LAR: load_file: No such file 'normal/stage2/segment3' LAR: load_file_segments: All loaded, entry 0x00002000 Phase 1: Very early setup... Phase 1: done Show all devs... root(Root Device): enabled 1 have_resources 0 cpus(CPU: 00): enabled 1 have_resources 0 domain_0_bus_0_pci_0_0(PCI: 00:00.0): enabled 1 have_resources 0 domain_0_bus_0_pci_1_1(PCI: 00:01.1): enabled 1 have_resources 0 domain_0_bus_0(PCI_BUS: 0000): enabled 1 have_resources 0 domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 Phase 2: Early setup... dev_phase2: dev root: ops 0x0000aff8 ops->phase2_fixup 0x00000000 dev_phase2: dev cpus: ops 0x00000000 ops->phase2_fixup 0x00000000 dev_phase2: dev domain_0_bus_0_pci_0_0: ops 0x00000000 ops->phase2_fixup 0x00000000 dev_phase2: dev domain_0_bus_0_pci_1_1: ops 0x0000b1b4 ops->phase2_fixup 0x00000000 dev_phase2: dev domain_0_bus_0: ops 0x00000000 ops->phase2_fixup 0x00000000 dev_phase2: dev domain_0: ops 0x0000b104 ops->phase2_fixup 0x00000000 Phase 2: Done. Show all devs... root(Root Device): enabled 1 have_resources 0 cpus(CPU: 00): enabled 1 have_resources 0 domain_0_bus_0_pci_0_0(PCI: 00:00.0): enabled 1 have_resources 0 domain_0_bus_0_pci_1_1(PCI: 00:01.1): enabled 1 have_resources 0 domain_0_bus_0(PCI_BUS: 0000): enabled 1 have_resources 0 domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 Phase 3: Enumerating buses... dev_phase3_scan: scanning root(Root Device) scan_static_bus for root (Root Device) cpus(CPU: 00) enabled domain_0(PCI_DOMAIN: 0000) enabled domain_0(PCI_DOMAIN: 0000) scanning... dev_phase3_scan: scanning domain_0(PCI_DOMAIN: 0000) pci_domain_scan_bus: calling pci_scan_bus pci_scan_bus start bus->dev domain_0 bus 0 ERROR: pci_scan_bus called with incorrect bus->dev->path.type, path is PCI_DOMAIN: 0000 PCI: pci_scan_bus for bus 00 pci_scan_bus: old_devices domain_0_bus_0, dev for this bus domain_0 PCI: scan devfn 0x0 to 0xff PCI: devfn 0x0 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) new_device: devcnt 1 find_device_operations: check all_device_operations[i] 0x0000b0ac find_device_operations: cons 0x0000b0ac, cons id PCI: 1013:00b8 find_device_operations: check all_device_operations[i] 0x0000b104 find_device_operations: cons 0x0000b104, cons id PCI_DOMAIN: 8086:7190 find_device_operations: check all_device_operations[i] 0x0000b1b4 find_device_operations: cons 0x0000b1b4, cons id PCI: 8086:7010 constructor: constructor is 0x00000000 No ops found and no constructor called for PCI: 8086:1237. find_device_operations: check all_device_operations[i] 0x0000b0ac find_device_operations: cons 0x0000b0ac, cons id PCI: 1013:00b8 find_device_operations: check all_device_operations[i] 0x0000b104 find_device_operations: cons 0x0000b104, cons id PCI_DOMAIN: 8086:7190 find_device_operations: check all_device_operations[i] 0x0000b1b4 find_device_operations: cons 0x0000b1b4, cons id PCI: 8086:7010 set_pci_ops: dev dynamic PCI: 00:00.0 set ops to type 0 PCI: 00:00.0 [PCI: 8086:1237] enabled PCI: pci_scan_bus pci_probe_dev returns dev dynamic PCI: 00:00.0 Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x8 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) new_device: devcnt 2 find_device_operations: check all_device_operations[i] 0x0000b0ac find_device_operations: cons 0x0000b0ac, cons id PCI: 1013:00b8 find_device_operations: check all_device_operations[i] 0x0000b104 find_device_operations: cons 0x0000b104, cons id PCI_DOMAIN: 8086:7190 find_device_operations: check all_device_operations[i] 0x0000b1b4 find_device_operations: cons 0x0000b1b4, cons id PCI: 8086:7010 constructor: constructor is 0x00000000 No ops found and no constructor called for PCI: 8086:7000. find_device_operations: check all_device_operations[i] 0x0000b0ac find_device_operations: cons 0x0000b0ac, cons id PCI: 1013:00b8 find_device_operations: check all_device_operations[i] 0x0000b104 find_device_operations: cons 0x0000b104, cons id PCI_DOMAIN: 8086:7190 find_device_operations: check all_device_operations[i] 0x0000b1b4 find_device_operations: cons 0x0000b1b4, cons id PCI: 8086:7010 set_pci_ops: dev dynamic PCI: 00:01.0 set ops to type 0 PCI: 00:01.0 [PCI: 8086:7000] enabled PCI: pci_scan_bus pci_probe_dev returns dev dynamic PCI: 00:01.0 PCI: devfn 0x9 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) new_device: devcnt 3 find_device_operations: check all_device_operations[i] 0x0000b0ac find_device_operations: cons 0x0000b0ac, cons id PCI: 1013:00b8 find_device_operations: check all_device_operations[i] 0x0000b104 find_device_operations: cons 0x0000b104, cons id PCI_DOMAIN: 8086:7190 find_device_operations: check all_device_operations[i] 0x0000b1b4 find_device_operations: cons 0x0000b1b4, cons id PCI: 8086:7010 find_device_operations: match constructor: constructor is 0x0000b1b4 default device constructor called set_pci_ops: dev dynamic PCI: 00:01.1 already has ops of type 20504349 PCI: 00:01.1 [PCI: 8086:7010] enabled PCI: pci_scan_bus pci_probe_dev returns dev dynamic PCI: 00:01.1 PCI: devfn 0xa pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xa, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) PCI: devfn 0xb pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) new_device: devcnt 4 find_device_operations: check all_device_operations[i] 0x0000b0ac find_device_operations: cons 0x0000b0ac, cons id PCI: 1013:00b8 find_device_operations: check all_device_operations[i] 0x0000b104 find_device_operations: cons 0x0000b104, cons id PCI_DOMAIN: 8086:7190 find_device_operations: check all_device_operations[i] 0x0000b1b4 find_device_operations: cons 0x0000b1b4, cons id PCI: 8086:7010 constructor: constructor is 0x00000000 No ops found and no constructor called for PCI: 8086:7113. find_device_operations: check all_device_operations[i] 0x0000b0ac find_device_operations: cons 0x0000b0ac, cons id PCI: 1013:00b8 find_device_operations: check all_device_operations[i] 0x0000b104 find_device_operations: cons 0x0000b104, cons id PCI_DOMAIN: 8086:7190 find_device_operations: check all_device_operations[i] 0x0000b1b4 find_device_operations: cons 0x0000b1b4, cons id PCI: 8086:7010 set_pci_ops: dev dynamic PCI: 00:01.3 set ops to type 0 PCI: 00:01.3 [PCI: 8086:7113] enabled PCI: pci_scan_bus pci_probe_dev returns dev dynamic PCI: 00:01.3 PCI: devfn 0xc pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xc, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) PCI: devfn 0xd pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xd, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) PCI: devfn 0xe pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xe, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) PCI: devfn 0xf pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xf, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) PCI: devfn 0x10 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) new_device: devcnt 5 find_device_operations: check all_device_operations[i] 0x0000b0ac find_device_operations: cons 0x0000b0ac, cons id PCI: 1013:00b8 find_device_operations: match constructor: constructor is 0x0000b0ac default device constructor called set_pci_ops: dev dynamic PCI: 00:02.0 already has ops of type 20504349 PCI: 00:02.0 [PCI: 1013:00b8] enabled PCI: pci_scan_bus pci_probe_dev returns dev dynamic PCI: 00:02.0 Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x18 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) new_device: devcnt 6 find_device_operations: check all_device_operations[i] 0x0000b0ac find_device_operations: cons 0x0000b0ac, cons id PCI: 1013:00b8 find_device_operations: check all_device_operations[i] 0x0000b104 find_device_operations: cons 0x0000b104, cons id PCI_DOMAIN: 8086:7190 find_device_operations: check all_device_operations[i] 0x0000b1b4 find_device_operations: cons 0x0000b1b4, cons id PCI: 8086:7010 constructor: constructor is 0x00000000 No ops found and no constructor called for PCI: 10ec:8029. find_device_operations: check all_device_operations[i] 0x0000b0ac find_device_operations: cons 0x0000b0ac, cons id PCI: 1013:00b8 find_device_operations: check all_device_operations[i] 0x0000b104 find_device_operations: cons 0x0000b104, cons id PCI_DOMAIN: 8086:7190 find_device_operations: check all_device_operations[i] 0x0000b1b4 find_device_operations: cons 0x0000b1b4, cons id PCI: 8086:7010 set_pci_ops: dev dynamic PCI: 00:03.0 set ops to type 0 PCI: 00:03.0 [PCI: 10ec:8029] enabled PCI: pci_scan_bus pci_probe_dev returns dev dynamic PCI: 00:03.0 Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x20 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x20, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x28 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x28, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x30 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x30, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x38 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x38, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x40 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x40, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x48 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x48, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x50 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x50, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x58 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x58, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x60 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x60, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x68 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x68, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x70 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x70, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x78 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x78, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x80 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x80, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x88 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x88, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x90 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x90, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x98 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x98, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xa0 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xa0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xa8 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xa8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xb0 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xb0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xb8 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xb8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xc0 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xc0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xc8 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xc8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xd0 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xd0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xd8 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xd8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xe0 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xe0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xe8 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xe8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xf0 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xf0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xf8 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_bus_0 pci_get_dev: child domain_0_bus_0(PCI_BUS: 0000) not a pci device: it's type 3 PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: Done for loop PCI: Left over static devices: domain_0_bus_0 PCI: End of leftover list. dev_phase3_scan: dynamic PCI: 00:00.0: busdevice 0x0000c778 enabled 1 ops 0x00008f6c dev_phase3_scan: can not scan from here, returning 0 dev_phase3_scan: dynamic PCI: 00:01.0: busdevice 0x0000ca70 enabled 1 ops 0x00008f6c dev_phase3_scan: can not scan from here, returning 0 dev_phase3_scan: dynamic PCI: 00:01.1: busdevice 0x0000cd68 enabled 1 ops 0x0000b1b4 dev_phase3_scan: can not scan from here, returning 0 dev_phase3_scan: dynamic PCI: 00:01.3: busdevice 0x0000d060 enabled 1 ops 0x00008f6c dev_phase3_scan: can not scan from here, returning 0 dev_phase3_scan: dynamic PCI: 00:02.0: busdevice 0x0000d358 enabled 1 ops 0x0000b0ac dev_phase3_scan: can not scan from here, returning 0 dev_phase3_scan: dynamic PCI: 00:03.0: busdevice 0x0000d650 enabled 1 ops 0x00008f6c dev_phase3_scan: can not scan from here, returning 0 PCI: pci_scan_bus returning with curr_bus=000 dev_phase3_scan: returning 0 scan_static_bus for root(Root Device) done dev_phase3_scan: returning 0 Phase 3: Done. Show all devs... root(Root Device): enabled 1 have_resources 0 cpus(CPU: 00): enabled 1 have_resources 0 domain_0_bus_0_pci_0_0(PCI: 00:00.0): enabled 1 have_resources 0 domain_0_bus_0_pci_1_1(PCI: 00:01.1): enabled 1 have_resources 0 domain_0_bus_0(PCI_BUS: 0000): enabled 1 have_resources 0 domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 dynamic PCI: 00:00.0(PCI: 00:00.0): enabled 1 have_resources 0 dynamic PCI: 00:01.0(PCI: 00:01.0): enabled 1 have_resources 0 dynamic PCI: 00:01.1(PCI: 00:01.1): enabled 1 have_resources 0 dynamic PCI: 00:01.3(PCI: 00:01.3): enabled 1 have_resources 0 dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1 have_resources 0 dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1 have_resources 0 Phase 4: Allocating resources... Phase 4: Reading resources... read_resources: root(Root Device) read_resources bus 0 link: 0 read_resources: root(Root Device) dtsname cpus have_resources 0 enabled 1 read_resources: cpus(CPU: 00) missing phase4_read_resources read_resources: root(Root Device) dtsname domain_0 have_resources 0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) read_resources bus 0 link: 0 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname dynamic PCI: 00:00.0 have_resources 0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname dynamic PCI: 00:01.0 have_resources 0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname dynamic PCI: 00:01.1 have_resources 0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname dynamic PCI: 00:01.3 have_resources 0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname dynamic PCI: 00:02.0 have_resources 0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname dynamic PCI: 00:03.0 have_resources 0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) read_resources bus 0 link: 0 done read_resources: root(Root Device) read_resources bus 0 link: 0 done root_dev_read_resources: Done allocating Show all devs... root(Root Device): enabled 1 have_resources 0 cpus(CPU: 00): enabled 1 have_resources 0 domain_0_bus_0_pci_0_0(PCI: 00:00.0): enabled 1 have_resources 0 domain_0_bus_0_pci_1_1(PCI: 00:01.1): enabled 1 have_resources 0 domain_0_bus_0(PCI_BUS: 0000): enabled 1 have_resources 0 domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 1 PCI_DOMAIN: 0000 10000000 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 io PCI_DOMAIN: 0000 10000100 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 mem dynamic PCI: 00:00.0(PCI: 00:00.0): enabled 1 have_resources 1 dynamic PCI: 00:01.0(PCI: 00:01.0): enabled 1 have_resources 1 dynamic PCI: 00:01.1(PCI: 00:01.1): enabled 1 have_resources 1 PCI: 00:01.1 20 <- [0x0000000000 - 0x000000000f] size 0x00000010 gran 0x04 io dynamic PCI: 00:01.3(PCI: 00:01.3): enabled 1 have_resources 1 dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1 have_resources 1 PCI: 00:02.0 10 <- [0x0000000000 - 0x0001ffffff] size 0x02000000 gran 0x19 prefmem PCI: 00:02.0 14 <- [0x0000000000 - 0x0000000fff] size 0x00001000 gran 0x0c mem dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1 have_resources 1 PCI: 00:03.0 10 <- [0x0000000000 - 0x00000000ff] size 0x00000100 gran 0x08 io Phase 4: Done reading resources. Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0 read_resources: root(Root Device) read_resources bus 0 link: 0 read_resources: root(Root Device) dtsname cpus have_resources 0 enabled 1 read_resources: cpus(CPU: 00) missing phase4_read_resources read_resources: root(Root Device) dtsname domain_0 have_resources 1 enabled 1 read_resources: root(Root Device) read_resources bus 0 link: 0 done PCI: 00:03.0 10 * [0x00000400 - 0x000004ff] io PCI: 00:01.1 20 * [0x00000800 - 0x0000080f] io Root Device compute_allocate_io: base: 00000810 size: 00000410 align: 8 gran: 0 done Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: 0 read_resources: root(Root Device) read_resources bus 0 link: 0 read_resources: root(Root Device) dtsname cpus have_resources 0 enabled 1 read_resources: cpus(CPU: 00) missing phase4_read_resources read_resources: root(Root Device) dtsname domain_0 have_resources 1 enabled 1 read_resources: root(Root Device) read_resources bus 0 link: 0 done PCI: 00:02.0 10 * [0x00000000 - 0x01ffffff] prefmem PCI: 00:02.0 14 * [0x02000000 - 0x02000fff] mem Root Device compute_allocate_mem: base: 02001000 size: 02001000 align: 25 gran: 0 done Allocating VGA resource PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Root Device compute_allocate_io: base: 00001000 size: 00000410 align: 8 gran: 0 read_resources: root(Root Device) read_resources bus 0 link: 0 read_resources: root(Root Device) dtsname cpus have_resources 0 enabled 1 read_resources: cpus(CPU: 00) missing phase4_read_resources read_resources: root(Root Device) dtsname domain_0 have_resources 1 enabled 1 read_resources: root(Root Device) read_resources bus 0 link: 0 done PCI: 00:03.0 10 * [0x00001000 - 0x000010ff] io PCI: 00:01.1 20 * [0x00001400 - 0x0000140f] io Root Device compute_allocate_io: base: 00001410 size: 00000410 align: 8 gran: 0 done Root Device compute_allocate_mem: base: fc000000 size: 02001000 align: 25 gran: 0 read_resources: root(Root Device) read_resources bus 0 link: 0 read_resources: root(Root Device) dtsname cpus have_resources 0 enabled 1 read_resources: cpus(CPU: 00) missing phase4_read_resources read_resources: root(Root Device) dtsname domain_0 have_resources 1 enabled 1 read_resources: root(Root Device) read_resources bus 0 link: 0 done PCI: 00:02.0 10 * [0xfc000000 - 0xfdffffff] prefmem PCI: 00:02.0 14 * [0xfe000000 - 0xfe000fff] mem Root Device compute_allocate_mem: base: fe001000 size: 02001000 align: 25 gran: 0 done Phase 4: Setting resources... root(Root Device) assign_resources, bus 0 link: 0 Ignoring chipset specified RAM size. Using dts settings of 114688 kB instead. Adding RAM resource (655360 bytes) Adding RAM resource (116654080 bytes) domain_0(PCI_DOMAIN: 0000) assign_resources, bus 0 link: 0 PCI: 00:01.1 20 <- [0x0000001400 - 0x000000140f] size 0x00000010 gran 0x04 io PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 prefmem PCI: 00:02.0 14 <- [0x00fe000000 - 0x00fe000fff] size 0x00001000 gran 0x0c mem PCI: 00:03.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io domain_0(PCI_DOMAIN: 0000) assign_resources done, bus 0 link: 0 root(Root Device) assign_resources done, bus 0 link: 0 Phase 4: Done setting resources. Phase 4: Done allocating resources. Show all devs... root(Root Device): enabled 1 have_resources 0 cpus(CPU: 00): enabled 1 have_resources 0 domain_0_bus_0_pci_0_0(PCI: 00:00.0): enabled 1 have_resources 0 domain_0_bus_0_pci_1_1(PCI: 00:01.1): enabled 1 have_resources 0 domain_0_bus_0(PCI_BUS: 0000): enabled 1 have_resources 0 domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 1 dynamic PCI: 00:00.0(PCI: 00:00.0): enabled 1 have_resources 1 dynamic PCI: 00:01.0(PCI: 00:01.0): enabled 1 have_resources 1 dynamic PCI: 00:01.1(PCI: 00:01.1): enabled 1 have_resources 1 dynamic PCI: 00:01.3(PCI: 00:01.3): enabled 1 have_resources 1 dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1 have_resources 1 dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1 have_resources 1 Phase 5: Enabling resources... dev_phase5: cpus(CPU: 00) missing ops PCI: 00:00.0: Device not on_mainboard PCI: 00:00.0: Not setting subsystem VID/DID pci_dev_enable_resources: dynamic PCI: 00:00.0 (PCI: 00:00.0) cmd <- 140 PCI: 00:01.0: Device not on_mainboard PCI: 00:01.0: Not setting subsystem VID/DID pci_dev_enable_resources: dynamic PCI: 00:01.0 (PCI: 00:01.0) cmd <- 147 PCI: 00:01.1: Device not on_mainboard PCI: 00:01.1: Not setting subsystem VID/DID pci_dev_enable_resources: dynamic PCI: 00:01.1 (PCI: 00:01.1) cmd <- 141 PCI: 00:01.3: Device not on_mainboard PCI: 00:01.3: Not setting subsystem VID/DID pci_dev_enable_resources: dynamic PCI: 00:01.3 (PCI: 00:01.3) cmd <- 140 PCI: 00:02.0: Device not on_mainboard PCI: 00:02.0: Not setting subsystem VID/DID pci_dev_enable_resources: dynamic PCI: 00:02.0 (PCI: 00:02.0) cmd <- 143 PCI: 00:03.0: Device not on_mainboard PCI: 00:03.0: Not setting subsystem VID/DID pci_dev_enable_resources: dynamic PCI: 00:03.0 (PCI: 00:03.0) cmd <- 141 Phase 5: Done. Show all devs... root(Root Device): enabled 1 have_resources 0 cpus(CPU: 00): enabled 1 have_resources 0 domain_0_bus_0_pci_0_0(PCI: 00:00.0): enabled 1 have_resources 0 domain_0_bus_0_pci_1_1(PCI: 00:01.1): enabled 1 have_resources 0 domain_0_bus_0(PCI_BUS: 0000): enabled 1 have_resources 0 domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 1 dynamic PCI: 00:00.0(PCI: 00:00.0): enabled 1 have_resources 1 dynamic PCI: 00:01.0(PCI: 00:01.0): enabled 1 have_resources 1 dynamic PCI: 00:01.1(PCI: 00:01.1): enabled 1 have_resources 1 dynamic PCI: 00:01.3(PCI: 00:01.3): enabled 1 have_resources 1 dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1 have_resources 1 dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1 have_resources 1 Phase 6: Initializing devices... Phase 6: Root Device init. Phase 6: PCI: 00:01.1 init. Enabling IDE channel 1 Enabling IDE channel 2 Enabling Legacy IDE Phase 6: PCI: 00:00.0 init. PCI: pci_dev_init dynamic PCI: 00:00.0 Probing for option ROM Phase 6: PCI: 00:01.0 init. PCI: pci_dev_init dynamic PCI: 00:01.0 Probing for option ROM Phase 6: PCI: 00:01.1 init. Enabling IDE channel 1 Enabling IDE channel 2 Enabling Legacy IDE Phase 6: PCI: 00:01.3 init. PCI: pci_dev_init dynamic PCI: 00:01.3 Probing for option ROM Phase 6: PCI: 00:02.0 init. Init VGA device PCI: pci_dev_init dynamic PCI: 00:02.0 Probing for option ROM ROM address for PCI: 00:02.0 = c0000 PCI Expansion ROM, signature 0xaa55, INIT size 0x8a00, data ptr 0x736f PCI ROM Image, @0x000c7373, Vendor 0846, Device ec89, Device or Vendor ID mismatch Vendor 0846, Device ec89 Phase 6: PCI: 00:03.0 init. PCI: pci_dev_init dynamic PCI: 00:03.0 Probing for option ROM Phase 6: Devices initialized. Show all devs... root(Root Device): enabled 1 have_resources 0 cpus(CPU: 00): enabled 1 have_resources 0 domain_0_bus_0_pci_0_0(PCI: 00:00.0): enabled 1 have_resources 0 domain_0_bus_0_pci_1_1(PCI: 00:01.1): enabled 1 have_resources 0 domain_0_bus_0(PCI_BUS: 0000): enabled 1 have_resources 0 domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 1 dynamic PCI: 00:00.0(PCI: 00:00.0): enabled 1 have_resources 1 dynamic PCI: 00:01.0(PCI: 00:01.0): enabled 1 have_resources 1 dynamic PCI: 00:01.1(PCI: 00:01.1): enabled 1 have_resources 1 dynamic PCI: 00:01.3(PCI: 00:01.3): enabled 1 have_resources 1 dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1 have_resources 1 dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1 have_resources 1 search_global_resources: mask 4200 type 4200 search_global_resources: dev root, have_resources 0 #resources 2 search_global_resources: dev cpus, have_resources 0 #resources 0 search_global_resources: dev domain_0_bus_0_pci_0_0, have_resources 0 #resources 0 search_global_resources: dev domain_0_bus_0_pci_1_1, have_resources 0 #resources 0 search_global_resources: dev domain_0_bus_0, have_resources 0 #resources 0 search_global_resources: dev domain_0, have_resources 1 #resources 4 search_global_resources: dev domain_0, resource 0, flags 40040100 base 0x0 size 0x0 search_global_resources: dev domain_0, resource 1, flags 40040200 base 0x0 size 0x0 search_global_resources: dev domain_0, resource 2, flags e0004200 base 0x0 size 0xa0000 search_global_resources: dev domain_0, resource 3, flags e0004200 base 0xc0000 size 0x6f40000 search_global_resources: dev dynamic PCI: 00:00.0, have_resources 1 #resources 0 search_global_resources: dev dynamic PCI: 00:01.0, have_resources 1 #resources 0 search_global_resources: dev dynamic PCI: 00:01.1, have_resources 1 #resources 1 search_global_resources: dev dynamic PCI: 00:01.1, resource 0, flags 60000100 base 0x1400 size 0x10 search_global_resources: dev dynamic PCI: 00:01.3, have_resources 1 #resources 0 search_global_resources: dev dynamic PCI: 00:02.0, have_resources 1 #resources 2 search_global_resources: dev dynamic PCI: 00:02.0, resource 0, flags 60001200 base 0xfc000000 size 0x2000000 search_global_resources: dev dynamic PCI: 00:02.0, resource 1, flags 60000200 base 0xfe000000 size 0x1000 search_global_resources: dev dynamic PCI: 00:03.0, have_resources 1 #resources 1 search_global_resources: dev dynamic PCI: 00:03.0, resource 0, flags 60000100 base 0x1000 size 0x100 Multiboot Information structure has been written. LAR: Attempting to open 'normal/option_table'. LAR: Start 0xfffc0000 len 0x40000 LAR: seen member normal/option_table@0xfffc0000, size 932 LAR: CHECK normal/option_table @ 0xfffc0000 start 0xfffc0050 len 932 reallen 932 compression 0 entry 0x00000000 loadaddress 0x00000000 search_global_resources: mask 4200 type 4200 search_global_resources: dev root, have_resources 0 #resources 2 search_global_resources: dev cpus, have_resources 0 #resources 0 search_global_resources: dev domain_0_bus_0_pci_0_0, have_resources 0 #resources 0 search_global_resources: dev domain_0_bus_0_pci_1_1, have_resources 0 #resources 0 search_global_resources: dev domain_0_bus_0, have_resources 0 #resources 0 search_global_resources: dev domain_0, have_resources 1 #resources 4 search_global_resources: dev domain_0, resource 0, flags 40040100 base 0x0 size 0x0 search_global_resources: dev domain_0, resource 1, flags 40040200 base 0x0 size 0x0 search_global_resources: dev domain_0, resource 2, flags e0004200 base 0x0 size 0xa0000 lb_memory_range: start 0x0 size 0xa0000 search_global_resources: dev domain_0, resource 3, flags e0004200 base 0xc0000 size 0x6f40000 lb_memory_range: start 0xc0000 size 0x6f40000 search_global_resources: dev dynamic PCI: 00:00.0, have_resources 1 #resources 0 search_global_resources: dev dynamic PCI: 00:01.0, have_resources 1 #resources 0 search_global_resources: dev dynamic PCI: 00:01.1, have_resources 1 #resources 1 search_global_resources: dev dynamic PCI: 00:01.1, resource 0, flags 60000100 base 0x1400 size 0x10 search_global_resources: dev dynamic PCI: 00:01.3, have_resources 1 #resources 0 search_global_resources: dev dynamic PCI: 00:02.0, have_resources 1 #resources 2 search_global_resources: dev dynamic PCI: 00:02.0, resource 0, flags 60001200 base 0xfc000000 size 0x2000000 search_global_resources: dev dynamic PCI: 00:02.0, resource 1, flags 60000200 base 0xfe000000 size 0x1000 search_global_resources: dev dynamic PCI: 00:03.0, have_resources 1 #resources 1 search_global_resources: dev dynamic PCI: 00:03.0, resource 0, flags 60000100 base 0x1000 size 0x100 lb_cleanup_memory_ranges: # entries 2 #0: base 0x00000000 size 0xa0000 #1: base 0x000c0000 size 0x6f40000 lb_memory_range: start 0x0 size 0x500 lb_cleanup_memory_ranges: # entries 3 #0: base 0x00000500 size 0x9fb00 #1: base 0x000c0000 size 0x6f40000 #2: base 0x00000000 size 0x500 lb_memory_range: start 0xf0000 size 0xd0 lb_cleanup_memory_ranges: # entries 5 #0: base 0x00000000 size 0x500 #1: base 0x00000500 size 0x9fb00 #2: base 0x000c0000 size 0x30000 #3: base 0x000f00d0 size 0x6f0ff30 #4: base 0x000f0000 size 0xd0 Wrote coreboot table at: 0x00000500 - 0x00000ad0 checksum 140e Show all devs... root(Root Device): enabled 1 have_resources 0 cpus(CPU: 00): enabled 1 have_resources 0 domain_0_bus_0_pci_0_0(PCI: 00:00.0): enabled 1 have_resources 0 domain_0_bus_0_pci_1_1(PCI: 00:01.1): enabled 1 have_resources 0 domain_0_bus_0(PCI_BUS: 0000): enabled 1 have_resources 0 domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 1 dynamic PCI: 00:00.0(PCI: 00:00.0): enabled 1 have_resources 1 dynamic PCI: 00:01.0(PCI: 00:01.0): enabled 1 have_resources 1 dynamic PCI: 00:01.1(PCI: 00:01.1): enabled 1 have_resources 1 dynamic PCI: 00:01.3(PCI: 00:01.3): enabled 1 have_resources 1 dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1 have_resources 1 dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1 have_resources 1 Stage2 code done. LAR: Attempting to open 'normal/payload/segment0'. LAR: Start 0xfffc0000 len 0x40000 LAR: seen member normal/option_table@0xfffc0000, size 932 LAR: seen member normal/initram/segment0@0xfffc0400, size 420 LAR: seen member normal/stage2/segment0@0xfffc0600, size 1 LAR: seen member normal/stage2/segment1@0xfffc0660, size 16161 LAR: seen member normal/stage2/segment2@0xfffc45e0, size 311 LAR: seen member bootblock@0xffffafc0, size 20480 LAR: File not found! LAR: load_file: No such file 'normal/payload/segment0' LAR: load_file_segments: Failed for normal/payload Before handoff to payload, lowest stack is 0x0008bf50 FATAL: No usable payload found.

2 3

r1012 - in coreboot-v3: arch/x86 include include/arch/x86 lib
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: hailfinger Date: 2008-11-13 02:28:32 +0100 (Thu, 13 Nov 2008) New Revision: 1012 Modified: coreboot-v3/arch/x86/Kconfig coreboot-v3/arch/x86/stage1.c coreboot-v3/include/arch/x86/cpu.h coreboot-v3/include/globalvars.h coreboot-v3/lib/console.c Log: We are woefully unaware about how much stack v3 really uses. This is a complete rewrite of my earlier stack checker proposal. It works for CAR and RAM, has better abstraction and actually gives us nice results. The stack checker is default off due to its rather measurable impact on boot speed. Diagnostic messages are printed on first initialization, directly after RAM init and directly before passing control to the payload. Sample qemu log is attached. Extract from that log follows: coreboot-3.0.986 Fri Nov 7 04:04:37 CET 2008 starting... (console_loglevel=8) Initial lowest stack is 0x0008fe98 Choosing fallback boot. [...] Done RAM init code After RAM init, lowest stack is 0x0008fe30 Done printk() buffer move [...] LAR: load_file_segments: Failed for normal/payload Before handoff to payload, lowest stack is 0x0008bf50 FATAL: No usable payload found. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/arch/x86/Kconfig =================================================================== --- coreboot-v3/arch/x86/Kconfig 2008-11-13 01:04:35 UTC (rev 1011) +++ coreboot-v3/arch/x86/Kconfig 2008-11-13 01:28:32 UTC (rev 1012) @@ -239,4 +239,13 @@ help Test the CAR area after it has been set up. +config CHECK_STACK_USAGE + bool "Check stack usage" + default n + help + Continuously monitor stack usage and keep statistics. + The monitoring code is invoked from printk because printk is + a leaf function and consumes quite a bit of stack for itself. + This slows down booting a LOT. + endmenu Modified: coreboot-v3/arch/x86/stage1.c =================================================================== --- coreboot-v3/arch/x86/stage1.c 2008-11-13 01:04:35 UTC (rev 1011) +++ coreboot-v3/arch/x86/stage1.c 2008-11-13 01:28:32 UTC (rev 1012) @@ -105,6 +105,28 @@ } +#ifdef CONFIG_CHECK_STACK_USAGE +/* STACKFILL_BYTE could be a special value like 0x6b. Just make sure the stage0 + * code fills the complete CAR area with it. And the stack switching needs to + * overwrite the unused parts of the stack with STACKFILL_BYTE as well. + */ +#define STACKFILL_BYTE 0x0 +void check_stack() +{ + unsigned long stacksize, i; + char *lowestaddr; + if (global_vars()->ram_available) + stacksize = RAM_STACK_SIZE; + else + stacksize = CAR_STACK_SIZE; + lowestaddr = bottom_of_stack() - stacksize; + for (i = 0; i < stacksize; i++) + if (lowestaddr[i] != STACKFILL_BYTE) + break; + global_vars()->loweststack = lowestaddr + i; +} +#endif + void dump_mem_range(int msg_level, unsigned char *buf, int size) { int i; @@ -194,6 +216,10 @@ */ console_init(); +#ifdef CONFIG_CHECK_STACK_USAGE + printk(BIOS_DEBUG, "Initial lowest stack is %p\n", + global_vars()->loweststack); +#endif if (bist!=0) { printk(BIOS_INFO, "BIST FAILED: %08x", bist); die(""); @@ -227,6 +253,10 @@ die("Failed RAM init code\n"); printk(BIOS_DEBUG, "Done RAM init code\n"); +#ifdef CONFIG_CHECK_STACK_USAGE + printk(BIOS_DEBUG, "After RAM init, lowest stack is %p\n", + global_vars()->loweststack); +#endif /* Switch the stack location from CAR to RAM, rebuild the stack, * disable CAR and continue at stage1_phase3(). This is all wrapped in @@ -299,6 +329,9 @@ mem->map[0].type = LB_MEM_RAM; #endif /* CONFIG_PAYLOAD_ELF_LOADER */ + /* Provide an easy way to check whether RAM is available. */ + global_vars()->ram_available = 1; + // location and size of image. init_archive(&archive); @@ -318,6 +351,10 @@ #endif /* CONFIG_PAYLOAD_ELF_LOADER */ entry = load_file_segments(&archive, "normal/payload"); +#ifdef CONFIG_CHECK_STACK_USAGE + printk(BIOS_DEBUG, "Before handoff to payload, lowest stack is %p\n", + global_vars()->loweststack); +#endif if (entry != (void*)-1) { /* Final coreboot call before handing off to the payload. */ mainboard_pre_payload(); Modified: coreboot-v3/include/arch/x86/cpu.h =================================================================== --- coreboot-v3/include/arch/x86/cpu.h 2008-11-13 01:04:35 UTC (rev 1011) +++ coreboot-v3/include/arch/x86/cpu.h 2008-11-13 01:28:32 UTC (rev 1012) @@ -265,6 +265,7 @@ EXPORT_SYMBOL(bottom_of_stack); struct global_vars * global_vars(void); EXPORT_SYMBOL(global_vars); +void check_stack(void); #define CAR_STACK_BASE (CONFIG_CARBASE + CONFIG_CARSIZE - 4) #define RAM_STACK_BASE 0x88ffc @@ -278,6 +279,8 @@ #else #define CAR_STACK_SIZE (CONFIG_CARSIZE - 4) #endif +/* To be honest, this limit is arbitrary and only used for stack checking. */ +#define RAM_STACK_SIZE (65536 - 4) /* resource maps. These started out as special for the K8 but now have more general usage */ /* it's not totally clear that the type and union are a great idea, but see the v2 code: Modified: coreboot-v3/include/globalvars.h =================================================================== --- coreboot-v3/include/globalvars.h 2008-11-13 01:04:35 UTC (rev 1011) +++ coreboot-v3/include/globalvars.h 2008-11-13 01:28:32 UTC (rev 1012) @@ -63,6 +63,10 @@ struct sys_info sys_info; /* has the spd hardware been set up? */ int spd_inited; + int ram_available; +#ifdef CONFIG_CHECK_STACK_USAGE + void *loweststack; +#endif }; #endif /* GLOBALVARS_H */ Modified: coreboot-v3/lib/console.c =================================================================== --- coreboot-v3/lib/console.c 2008-11-13 01:04:35 UTC (rev 1011) +++ coreboot-v3/lib/console.c 2008-11-13 01:28:32 UTC (rev 1012) @@ -150,6 +150,9 @@ i += vtxprintf(console_tx_byte, (void *)0, fmt, args); va_end(args); +#ifdef CONFIG_CHECK_STACK_USAGE + check_stack(); +#endif return i; }

1 0

r1011 - in coreboot-v3/mainboard: artecgroup/dbe61 artecgroup/dbe62 pcengines/alix1c
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: stuge Date: 2008-11-13 02:04:35 +0100 (Thu, 13 Nov 2008) New Revision: 1011 Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c coreboot-v3/mainboard/artecgroup/dbe62/initram.c coreboot-v3/mainboard/pcengines/alix1c/initram.c Log: Remove insignificant unused spd_devices arrays. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-11-13 00:04:55 UTC (rev 1010) +++ coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-11-13 01:04:35 UTC (rev 1011) @@ -143,9 +143,6 @@ */ int main(void) { - u8 smb_devices[] = { - DIMM0, DIMM1 - }; printk(BIOS_DEBUG, "Hi there from stage1\n"); post_code(POST_START_OF_MAIN); Modified: coreboot-v3/mainboard/artecgroup/dbe62/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/initram.c 2008-11-13 00:04:55 UTC (rev 1010) +++ coreboot-v3/mainboard/artecgroup/dbe62/initram.c 2008-11-13 01:04:35 UTC (rev 1011) @@ -125,9 +125,6 @@ { void dumplxmsrs(void); - u8 smb_devices[] = { - DIMM0, DIMM1 - }; printk(BIOS_DEBUG, "Hi there from stage1\n"); post_code(POST_START_OF_MAIN); Modified: coreboot-v3/mainboard/pcengines/alix1c/initram.c =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/initram.c 2008-11-13 00:04:55 UTC (rev 1010) +++ coreboot-v3/mainboard/pcengines/alix1c/initram.c 2008-11-13 01:04:35 UTC (rev 1011) @@ -133,9 +133,6 @@ */ int main(void) { - u8 smb_devices[] = { - DIMM0, DIMM1 - }; printk(BIOS_DEBUG, "Hi there from stage1\n"); post_code(POST_START_OF_MAIN);

1 0

[PATCH 1/5] Return the count of failures from ram_check.
by Mart Raudsepp 12 Nov '08

12 Nov '08

Return the count of failures from ram_check. Will be necessary for DBE61 automatic memory size selection. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- include/lib.h | 2 +- lib/ramtest.c | 10 +++++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/include/lib.h b/include/lib.h index 31c685d..2132b2f 100644 --- a/include/lib.h +++ b/include/lib.h @@ -50,6 +50,6 @@ void beep_short(void); void beep_long(void); /* Optional ramtest. */ -void ram_check(unsigned long start, unsigned long stop); +int ram_check(unsigned long start, unsigned long stop); #endif /* LIB_H */ diff --git a/lib/ramtest.c b/lib/ramtest.c index 8a0f4b1..02a4bdb 100644 --- a/lib/ramtest.c +++ b/lib/ramtest.c @@ -84,7 +84,7 @@ static void ram_fill(unsigned long start, unsigned long stop) * @param start The beginning of the RAM area. * @param stop The end of the RAM area. */ -static void ram_verify(unsigned long start, unsigned long stop) +static int ram_verify(unsigned long start, unsigned long stop) { unsigned long addr, value; int i = 0; @@ -112,6 +112,7 @@ static void ram_verify(unsigned long start, unsigned long stop) /* Print whether or not the verify failed. */ printk(BIOS_DEBUG, "\nDRAM range %sverified.", i ? "_NOT_ " : ""); + return i; } /** @@ -123,11 +124,14 @@ static void ram_verify(unsigned long start, unsigned long stop) * * @param start The beginning of the RAM area. * @param stop The end of the RAM area. + * @return verify failure count */ -void ram_check(unsigned long start, unsigned long stop) +int ram_check(unsigned long start, unsigned long stop) { + int result; printk(BIOS_DEBUG, "Testing DRAM: %lx-%lx\n", start, stop); ram_fill(start, stop); - ram_verify(start, stop); + result = ram_verify(start, stop); printk(BIOS_DEBUG, "Done.\n"); + return result; } -- 1.6.0.2

2 1

[PATCH 0/5] Patches for getting DBE61A memory to work
by Mart Raudsepp 12 Nov '08

12 Nov '08

Hello, The following patches (in subsequent mails) make DBE61A memory setup work for me, while keeping DBE61C working as well from the same build result ROM. It appears to pass memtest86+ as long as I tested (at least one full pass for each), but only if it starts up. Sometimes it gives me "Unexpected Interrupt - Halting" at start, but memtest86+ with serial port support compiled in is known to be cranky like that. Either way, before these patches it wouldn't even reach the payload anyway on DBE61A. With Regards, Mart Raudsepp Artec Design LLC

1 0

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coreboot November 2008