coreboot November 2008

coreboot@coreboot.org

76 participants
490 discussions

r3752 build service
by coreboot information 14 Nov '08

14 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3752 to the coreboot source repository and caused the following changes: Change Log: drop dead code in sb600 hda Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of intel:jarrell has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3752 - trunk/coreboot-v2/src/southbridge/amd/sb600
by svn＠coreboot.org 14 Nov '08

14 Nov '08

Author: stepan Date: 2008-11-14 14:43:26 +0100 (Fri, 14 Nov 2008) New Revision: 3752 Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_hda.c Log: drop dead code in sb600 hda Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_hda.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_hda.c 2008-11-12 20:38:51 UTC (rev 3751) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_hda.c 2008-11-14 13:43:26 UTC (rev 3752) @@ -267,8 +267,7 @@ u32 codec_mask; /* SM Setting */ - device_t hda_dev; - hda_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + /* Set routing pin */ pci_write_config32(dev, 0xf8, 0x0); pci_write_config8(dev, 0xfc, 0xAA);

1 0

[PATCH] remove some dead code from sb600-hda.c
by Stefan Reinauer 14 Nov '08

14 Nov '08

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

2 1

r1019 - in coreboot-v3: arch/x86 arch/x86/intel/core2 arch/x86/via mainboard/jetway/j7f2 mainboard/kontron/986lcd-m southbridge/intel/i82801gx
by svn＠coreboot.org 14 Nov '08

14 Nov '08

Author: rminnich Date: 2008-11-14 06:05:24 +0100 (Fri, 14 Nov 2008) New Revision: 1019 Added: coreboot-v3/arch/x86/intel/core2/stage1.c Modified: coreboot-v3/arch/x86/Makefile coreboot-v3/arch/x86/via/stage1.c coreboot-v3/mainboard/jetway/j7f2/stage1.c coreboot-v3/mainboard/kontron/986lcd-m/initram.c coreboot-v3/mainboard/kontron/986lcd-m/stage1_debug.c coreboot-v3/southbridge/intel/i82801gx/libsmbus.c Log: Add core2 stage1.c dependency Index: arch/x86/intel/core2/stage1.c Initial core2 disable_car and stop_ap disable_car is wrong but we can fix that tomorrow -- it's core 2 day on friday! Index: arch/x86/via/stage1.c Add empty stop_ap() Index: mainboard/kontron/986lcd-m/stage1_debug.c Cleanup Index: mainboard/kontron/986lcd-m/initram.c Cleanup Index: mainboard/jetway/j7f2/stage1.c Remove definition of stop_ap; this belongs in the cpu! Index: southbridge/intel/i82801gx/libsmbus.c Fix definition of TIMEOUT (i.e. remove it) Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/arch/x86/Makefile =================================================================== --- coreboot-v3/arch/x86/Makefile 2008-11-13 17:55:39 UTC (rev 1018) +++ coreboot-v3/arch/x86/Makefile 2008-11-14 05:05:24 UTC (rev 1019) @@ -125,7 +125,7 @@ else ifeq ($(CONFIG_CPU_INTEL_CORE2),y) STAGE0_CAR_OBJ = intel/core2/stage0.o - #STAGE0_ARCH_X86_SRC += intel/core2/stage1.c + STAGE0_ARCH_X86_SRC += intel/core2/stage1.c else ifeq ($(CONFIG_CPU_VIA_C7),y) STAGE0_CAR_OBJ = via/stage0.o Added: coreboot-v3/arch/x86/intel/core2/stage1.c =================================================================== --- coreboot-v3/arch/x86/intel/core2/stage1.c (rev 0) +++ coreboot-v3/arch/x86/intel/core2/stage1.c 2008-11-14 05:05:24 UTC (rev 1019) @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <msr.h> +#include <macros.h> +#include <cpu.h> +#include <stage1.h> +#include <globalvars.h> +#include <string.h> +#include <mtrr.h> + +/** + * Disable Cache As RAM (CAR) after memory is setup. + */ +void disable_car(void) +{ + printk(BIOS_DEBUG, "disable_car entry\n"); + /* Determine new global variable location. Stack organization from top + * Top 4 bytes are reserved + * Pointer to global variables + * Global variables + * + * Align the result to 8 bytes + */ + struct global_vars *const newlocation = (struct global_vars *)((RAM_STACK_BASE - sizeof(struct global_vars *) - sizeof(struct global_vars)) & ~0x7); + /* Copy global variables to new location. */ + memcpy(newlocation, global_vars(), sizeof(struct global_vars)); + printk(BIOS_DEBUG, "disable_car global_vars copy done\n"); + /* Set the new global variable pointer. */ + *(struct global_vars **)(RAM_STACK_BASE - sizeof(struct global_vars *)) = newlocation; + + printk(BIOS_DEBUG, "disable_car global_vars pointer adjusted\n"); + printk(BIOS_DEBUG, "entering asm code now\n"); + + __asm__ __volatile__( + " movl %[newesp], %%esp \n" + + /* We don't need cache as ram for now on */ + /* disable cache */ + " movl %%cr0, %%eax \n" + " orl $(0x1<<30),%%eax \n" + " movl %%eax, %%cr0 \n" + + /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/ + /* clear sth */ + " xorl %%eax, %%eax \n" + " xorl %%edx, %%edx \n" + " movl $0x201, %%ecx \n" + " wrmsr \n" + " movl $0x200, %%ecx \n" + " wrmsr \n" + + /* Set the default memory type and disable fixed and enable variable MTRRs */ + " movl %[_MTRRdefType_MSR], %%ecx \n" + " xorl %%edx, %%edx \n" + /* Enable Variable and Disable Fixed MTRRs */ + " movl $0x00000800, %%eax \n" + " wrmsr \n" + + /* enable cache */ + " movl %%cr0, %%eax \n" + " andl $0x9fffffff,%%eax \n" + " movl %%eax, %%cr0 \n" + + " wbinvd \n" + + " call stage1_phase3 \n" + :: [newesp] "i" (newlocation), + [_MTRRdefType_MSR] "i" (MTRRdefType_MSR) + : "memory"); +} + +void stop_ap(void) +{ +} + Modified: coreboot-v3/arch/x86/via/stage1.c =================================================================== --- coreboot-v3/arch/x86/via/stage1.c 2008-11-13 17:55:39 UTC (rev 1018) +++ coreboot-v3/arch/x86/via/stage1.c 2008-11-14 05:05:24 UTC (rev 1019) @@ -90,3 +90,8 @@ [_MTRRdefType_MSR] "i" (MTRRdefType_MSR) : "memory"); } + +void stop_ap(void) +{ +} + Modified: coreboot-v3/mainboard/jetway/j7f2/stage1.c =================================================================== --- coreboot-v3/mainboard/jetway/j7f2/stage1.c 2008-11-13 17:55:39 UTC (rev 1018) +++ coreboot-v3/mainboard/jetway/j7f2/stage1.c 2008-11-14 05:05:24 UTC (rev 1019) @@ -28,12 +28,6 @@ #include <superio/fintek/f71805f/f71805f.h> #include <northbridge/via/cn700/cn700.h> -/* Placeholders, build fails without them */ -void stop_ap(void) -{ - //int noop; -} - void hardware_stage1(void) { u32 dev; Modified: coreboot-v3/mainboard/kontron/986lcd-m/initram.c =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/initram.c 2008-11-13 17:55:39 UTC (rev 1018) +++ coreboot-v3/mainboard/kontron/986lcd-m/initram.c 2008-11-14 05:05:24 UTC (rev 1019) @@ -33,7 +33,6 @@ #include <string.h> #include <msr.h> #include <io.h> -#include <amd/k8/k8.h> #include <mc146818rtc.h> #include <spd.h> @@ -73,6 +72,92 @@ return do_smbus_read_byte(device, address); } +static void early_ich7_init(void) +{ + u8 reg8; + u32 reg32; + + // program secondary mlt XXX byte? + pci_conf1_write_config8(PCI_BDF(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_conf1_read_config8(PCI_BDF(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_conf1_write_config8(PCI_BDF(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_conf1_read_config8(PCI_BDF(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_conf1_write_config8(PCI_BDF(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_conf1_read_config32(PCI_BDF(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_conf1_write_config32(PCI_BDF(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_conf1_read_config32(PCI_BDF(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_conf1_write_config32(PCI_BDF(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} +static void rcba_config(void) +{ + /* Set up virtual channel 0 */ + //RCBA32(0x0014) = 0x80000001; + //RCBA32(0x001c) = 0x03128010; + + /* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042210; + /* Device 1d interrupt pin register */ + RCBA32(0x310c) = 0x00214321; + + /* dev irq route register */ + RCBA16(0x3140) = 0x0132; + RCBA16(0x3142) = 0x3241; + RCBA16(0x3144) = 0x0237; + RCBA16(0x3146) = 0x3210; + RCBA16(0x3148) = 0x3210; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Disable unused devices */ + RCBA32(0x3418) = 0x000e0063; + + /* Enable PCIe Root Port Clock Gate */ + // RCBA32(0x341c) = 0x00000001; +} + + + /** * main for initram for the AMD DBM690T * @param init_detected Used to indicate that we have been started via init @@ -89,6 +174,11 @@ */ int main(void) { + void i945_early_initialization(void); + void enable_smbus(void); + int fixup_i945_errata(void); + void i945_late_initialization(void); + if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; @@ -102,7 +192,7 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if DEFAULT_CONSOLE_LOGLEVEL > 8 +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif Modified: coreboot-v3/mainboard/kontron/986lcd-m/stage1_debug.c =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/stage1_debug.c 2008-11-13 17:55:39 UTC (rev 1018) +++ coreboot-v3/mainboard/kontron/986lcd-m/stage1_debug.c 2008-11-14 05:05:24 UTC (rev 1019) @@ -25,7 +25,6 @@ #include <msr.h> #include <legacy.h> #include <device/pci_ids.h> -#include <statictree.h> #include <config.h> #define SMBUS_MEM_DEVICE_START 0x50 Modified: coreboot-v3/southbridge/intel/i82801gx/libsmbus.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/libsmbus.c 2008-11-13 17:55:39 UTC (rev 1018) +++ coreboot-v3/southbridge/intel/i82801gx/libsmbus.c 2008-11-14 05:05:24 UTC (rev 1019) @@ -32,8 +32,8 @@ #include "i82801gx.h" /* this is very chipset-specific. */ -#define SMBUS_TIMEOUT (100*1000*10) /* These are common functions used in stage 1 and stage2 */ +#warning why do we have an smbus_delay here void smbus_delay(void) { inb(0x80);

1 0

patch: allow dts include files to have nodes
by ron minnich 13 Nov '08

13 Nov '08

per IRC discussions. ron

3 8

PCI interrupts and VGA?
by Myles Watson 13 Nov '08

13 Nov '08

I'm attaching the config dumps for v2 and v3. I've modified the v2 dump by taking out the subsystem vendor and device IDs because I don't think they affect functionality and they confuse the issue. There are relatively few differences left, but I'm not sure what's the most important one. Some of the differences are: 1. v2 sets interrupts, v3 doesn't (when and where should that happen?) 2. v2 enables the other core in the Opteron, v3 doesn't yet (low priority for now) It looks like the bridges are all set up correctly, but the VGA area 0xa0000-0xbffff isn't getting to the VGA card (If you look at the other mapping, it's not updated) The current status is: - Coreboot boots to the payload - VGA ROM is run - Screen turns black (initializes) (that means that the VGA IOs in the 0x3xx range are getting there.) - No output on screen Thanks, Myles

2 1

[buildrom][patch] dbm690t headless fix
by Marc Jones 13 Nov '08

13 Nov '08

I think that this is the right way to fix this. The make was stopping if we tried to make a headless version. Marc -- http://marcjstuff.blogspot.com/

2 2

r253 - buildrom-devel/packages/roms
by svn＠coreboot.org 13 Nov '08

13 Nov '08

Author: mjones Date: 2008-11-13 19:55:51 +0100 (Thu, 13 Nov 2008) New Revision: 253 Modified: buildrom-devel/packages/roms/amd_r690.mk Log: Skip the VBIOS check if building a headless version. Signed-off-by: Marc Jones <marcj303(a)yahoo.com> Acked-by: Jordan Crouse <jordan(a)cosmicpenguin.net> Modified: buildrom-devel/packages/roms/amd_r690.mk =================================================================== --- buildrom-devel/packages/roms/amd_r690.mk 2008-11-11 21:16:21 UTC (rev 252) +++ buildrom-devel/packages/roms/amd_r690.mk 2008-11-13 18:55:51 UTC (rev 253) @@ -2,7 +2,6 @@ R690_TARGET_ROM := $(shell basename $(AMD_R690_VBIOS_LOCATION)) OPTIONROM_TARGETS += $(OUTPUT_DIR)/roms/$(R690_TARGET_ROM) CBV2_PREPEND := $(OUTPUT_DIR)/roms/$(R690_TARGET_ROM) -endif $(AMD_R690_VBIOS_LOCATION): @ $(BIN_DIR)/show-instructions.sh \ @@ -14,3 +13,4 @@ $(OUTPUT_DIR)/roms/$(R690_TARGET_ROM): $(AMD_R690_VBIOS_LOCATION) @ mkdir -p $(OUTPUT_DIR)/roms @ cp $< $@ +endif

1 0

[PATCH 4/5] artecgroup/dbe61: Get DBE61A RAM setup and timing working.
by Mart Raudsepp 13 Nov '08

13 Nov '08

artecgroup/dbe61: Get DBE61A RAM setup and timing working. * Uncomment the dbe61a SPD table * Modify spd_read_byte to support a DIMM SPD address at DIMM_DBE61A that outputs data from dbe61a SPD table instead of dbe61c; approach tip from Marc Jones * In main() after setting up DBE61C 256MB RAM, run a ram_check, and if that returns a greater than zero verify error count set up 128MB for DBE61A instead * Tweak the dbe61a SPD table to result in LX MSR values as known to work in Artec v2 branch - this is DBE62/DBE61C values, with density and NUM_COLUMNS halved, and some timings tweaked according to the v2 results. Now memtest86+ is quite happy on both DBE61C and DBE61A. Note that it should be better to ram_check in the high memory areas, but that doesn't seem to currently work. Low memory check seems fine for the immediate time being, as the results appear shifted there as well with the wrong size/timing setup. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- mainboard/artecgroup/dbe61/Makefile | 3 +- mainboard/artecgroup/dbe61/initram.c | 73 +++++++++++++++++++++++----------- 2 files changed, 51 insertions(+), 25 deletions(-) diff --git a/mainboard/artecgroup/dbe61/Makefile b/mainboard/artecgroup/dbe61/Makefile index 9febdf4..1493b9d 100644 --- a/mainboard/artecgroup/dbe61/Makefile +++ b/mainboard/artecgroup/dbe61/Makefile @@ -23,7 +23,8 @@ STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \ - $(src)/arch/x86/geodelx/geodelx.c + $(src)/arch/x86/geodelx/geodelx.c \ + $(src)/lib/ramtest.c STAGE2_MAINBOARD_SRC = diff --git a/mainboard/artecgroup/dbe61/initram.c b/mainboard/artecgroup/dbe61/initram.c index d454e46..d8612de 100644 --- a/mainboard/artecgroup/dbe61/initram.c +++ b/mainboard/artecgroup/dbe61/initram.c @@ -37,6 +37,7 @@ #define PLLMSRLO 0x02000030 #define DIMM_DBE61C ((u8) 0xA0) #define DIMM_EMPTY ((u8) 0xA2) +#define DIMM_DBE61A ((u8) 0xA4) struct spd_entry { u8 address; @@ -44,6 +45,7 @@ struct spd_entry { }; /* Save space by using a short list of SPD values used by Geode LX Memory init */ + /* Fake SPD for DBE61C - 256MB. Same memory chip, and therefore same SPD entries, as for DBE62. */ /* Micron MT46V32M16 */ static const struct spd_entry spd_table_dbe61c[] = { @@ -67,35 +69,33 @@ static const struct spd_entry spd_table_dbe61c[] = { {SPD_tRCD, 15}, }; -#if 0 -/* Fake SPD for DBE61A - 128MB. Not working yet */ +/* Fake SPD for DBE61A - 128MB */ /* Micron MT46V16M16 */ static const struct spd_entry spd_table_dbe61a[] = { - {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, - {SPD_BANK_DENSITY, 0x40}, - {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, {SPD_MEMORY_TYPE, 7}, - {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */ - {SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */ - {SPD_NUM_BANKS_PER_SDRAM, 4}, + {SPD_NUM_ROWS, 13}, + {SPD_tRFC, 0x85}, + {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, + {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x20}, + {SPD_tRAS, 0x35}, + {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x7}, /*0x <= 7},*/ + {SPD_MIN_RAS_TO_CAS_DELAY, 0x58}, + {SPD_tRRD, 0x3c}, + {SPD_tRP, 0x58}, {SPD_PRIMARY_SDRAM_WIDTH, 8}, - {SPD_NUM_DIMM_BANKS, 1}, /* ALIX1.C is 1 bank. */ - {SPD_NUM_COLUMNS, 0xa}, - {SPD_NUM_ROWS, 3}, - {SPD_REFRESH, 0x3a}, - {SPD_SDRAM_CYCLE_TIME_2ND, 60}, - {SPD_SDRAM_CYCLE_TIME_3RD, 75}, - {SPD_tRAS, 40}, + {SPD_NUM_BANKS_PER_SDRAM, 0x4}, + {SPD_NUM_COLUMNS, 0x9}, /* 4kB */ + {SPD_NUM_DIMM_BANKS, 0x1}, + {SPD_REFRESH, 0x82}, + {SPD_SDRAM_CYCLE_TIME_2ND, 0x0}, + {SPD_SDRAM_CYCLE_TIME_3RD, 0x0}, {SPD_tRCD, 15}, - {SPD_tRFC, 70}, - {SPD_tRP, 15}, - {SPD_tRRD, 10}, }; -#endif /** * Given an SMBUS device, and an address in that device, return the value of SPD - * for that device. In this mainboard, the only one that can return is DIMM_DBE61C. + * for that device. In this mainboard, the only one that can return is DIMM_DBE61A + * and DIMM_DBE61C. * @param device The device number * @param address The address in SPD rom to return the value of * @returns The value @@ -111,12 +111,23 @@ u8 spd_read_byte(u16 device, u8 address) for (i = 0; i < ARRAY_SIZE(spd_table_dbe61c); i++) { if (spd_table_dbe61c[i].address == address) { ret = spd_table_dbe61c[i].data; - break; + break; } } if (i == ARRAY_SIZE(spd_table_dbe61c)) - printk(BIOS_DEBUG, " addr %02x does not exist in SPD table", + printk(BIOS_DEBUG, " addr %02x does not exist in DBE61C SPD table", + address); + } else if (device == DIMM_DBE61A) { + for (i = 0; i < ARRAY_SIZE(spd_table_dbe61a); i++) { + if (spd_table_dbe61a[i].address == address) { + ret = spd_table_dbe61a[i].data; + break; + } + } + + if (i == ARRAY_SIZE(spd_table_dbe61a)) + printk(BIOS_DEBUG, " addr %02x does not exist in DBE61A SPD table", address); } @@ -151,8 +162,8 @@ static void initialize_ram(u8 dimm0, u8 dimm1) } /** - * main for initram for the PC Engines Alix 1C. It might seem that you - * could somehow do these functions in, e.g., the cpu code, but the + * main for initram for the Artec Group ThinCan DBE61. It might seem that + * you could somehow do these functions in, e.g., the cpu code, but the * order of operations and what those operations are is VERY strongly * mainboard dependent. It's best to leave it in the mainboard code. */ @@ -170,7 +181,21 @@ int main(void) pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO); printk(BIOS_DEBUG, "done pll reset\n"); + printk(BIOS_INFO, "Trying 256MB RAM\n"); initialize_ram(DIMM_DBE61C, DIMM_EMPTY); + /* FIXME: Would like to check around 188MB and 88MB, but that high always + fails, even if everything works fine for a memtest86+ payload */ + if (ram_check(596*1024, 608*1024) == 0) { + printk(BIOS_INFO, "DRAM 256MB configuration OK\n"); + } else { + printk(BIOS_INFO, "Trying 128MB RAM\n"); + initialize_ram(DIMM_DBE61A, DIMM_EMPTY); + + if (ram_check(596*1024, 608*1024) == 0) + printk(BIOS_INFO, "DRAM 128MB configuration OK\n"); + else + printk(BIOS_INFO, "DRAM configuration failed\n"); + } /* Check low memory */ /*ram_check(0x00000000, 640*1024); */ -- 1.6.0.2

3 3

r1018 - coreboot-v3/mainboard/artecgroup/dbe61
by svn＠coreboot.org 13 Nov '08

13 Nov '08

Author: mraudsepp Date: 2008-11-13 18:55:39 +0100 (Thu, 13 Nov 2008) New Revision: 1018 Modified: coreboot-v3/mainboard/artecgroup/dbe61/Makefile coreboot-v3/mainboard/artecgroup/dbe61/initram.c Log: artecgroup/dbe61: Get DBE61A RAM setup and timing working. * Uncomment the dbe61a SPD table * Modify spd_read_byte to support a DIMM SPD address at DIMM_DBE61A that outputs data from dbe61a SPD table instead of dbe61c; approach tip from Marc Jones * In main() after setting up DBE61C 256MB RAM, run a ram_check, and if that returns a greater than zero verify error count set up 128MB for DBE61A instead * Tweak the dbe61a SPD table to result in LX MSR values as known to work in Artec v2 branch - this is DBE62/DBE61C values, with density and NUM_COLUMNS halved, and some timings tweaked according to the v2 results. Now memtest86+ is quite happy on both DBE61C and DBE61A. Note that it should be better to ram_check in the high memory areas, but that doesn't seem to currently work. Low memory check seems fine for the immediate time being, as the results appear shifted there as well with the wrong size/timing setup. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Good enough for now. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/mainboard/artecgroup/dbe61/Makefile =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/Makefile 2008-11-13 17:42:52 UTC (rev 1017) +++ coreboot-v3/mainboard/artecgroup/dbe61/Makefile 2008-11-13 17:55:39 UTC (rev 1018) @@ -23,7 +23,8 @@ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \ - $(src)/arch/x86/geodelx/geodelx.c + $(src)/arch/x86/geodelx/geodelx.c \ + $(src)/lib/ramtest.c STAGE2_MAINBOARD_SRC = Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-11-13 17:42:52 UTC (rev 1017) +++ coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-11-13 17:55:39 UTC (rev 1018) @@ -37,6 +37,7 @@ #define PLLMSRLO 0x02000030 #define DIMM_DBE61C ((u8) 0xA0) #define DIMM_EMPTY ((u8) 0xA2) +#define DIMM_DBE61A ((u8) 0xA4) struct spd_entry { u8 address; @@ -44,6 +45,7 @@ }; /* Save space by using a short list of SPD values used by Geode LX Memory init */ + /* Fake SPD for DBE61C - 256MB. Same memory chip, and therefore same SPD entries, as for DBE62. */ /* Micron MT46V32M16 */ static const struct spd_entry spd_table_dbe61c[] = { @@ -67,35 +69,33 @@ {SPD_tRCD, 15}, }; -#if 0 -/* Fake SPD for DBE61A - 128MB. Not working yet */ +/* Fake SPD for DBE61A - 128MB */ /* Micron MT46V16M16 */ static const struct spd_entry spd_table_dbe61a[] = { + {SPD_MEMORY_TYPE, 7}, + {SPD_NUM_ROWS, 13}, + {SPD_tRFC, 0x85}, {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, - {SPD_BANK_DENSITY, 0x40}, - {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, - {SPD_MEMORY_TYPE, 7}, - {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */ - {SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */ - {SPD_NUM_BANKS_PER_SDRAM, 4}, + {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x20}, + {SPD_tRAS, 0x35}, + {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x7}, /*0x <= 7},*/ + {SPD_MIN_RAS_TO_CAS_DELAY, 0x58}, + {SPD_tRRD, 0x3c}, + {SPD_tRP, 0x58}, {SPD_PRIMARY_SDRAM_WIDTH, 8}, - {SPD_NUM_DIMM_BANKS, 1}, /* ALIX1.C is 1 bank. */ - {SPD_NUM_COLUMNS, 0xa}, - {SPD_NUM_ROWS, 3}, - {SPD_REFRESH, 0x3a}, - {SPD_SDRAM_CYCLE_TIME_2ND, 60}, - {SPD_SDRAM_CYCLE_TIME_3RD, 75}, - {SPD_tRAS, 40}, + {SPD_NUM_BANKS_PER_SDRAM, 0x4}, + {SPD_NUM_COLUMNS, 0x9}, /* 4kB */ + {SPD_NUM_DIMM_BANKS, 0x1}, + {SPD_REFRESH, 0x82}, + {SPD_SDRAM_CYCLE_TIME_2ND, 0x0}, + {SPD_SDRAM_CYCLE_TIME_3RD, 0x0}, {SPD_tRCD, 15}, - {SPD_tRFC, 70}, - {SPD_tRP, 15}, - {SPD_tRRD, 10}, }; -#endif /** * Given an SMBUS device, and an address in that device, return the value of SPD - * for that device. In this mainboard, the only one that can return is DIMM_DBE61C. + * for that device. In this mainboard, the only one that can return is DIMM_DBE61A + * and DIMM_DBE61C. * @param device The device number * @param address The address in SPD rom to return the value of * @returns The value @@ -111,13 +111,24 @@ for (i = 0; i < ARRAY_SIZE(spd_table_dbe61c); i++) { if (spd_table_dbe61c[i].address == address) { ret = spd_table_dbe61c[i].data; - break; + break; } } if (i == ARRAY_SIZE(spd_table_dbe61c)) - printk(BIOS_DEBUG, " addr %02x does not exist in SPD table", + printk(BIOS_DEBUG, " addr %02x does not exist in DBE61C SPD table", address); + } else if (device == DIMM_DBE61A) { + for (i = 0; i < ARRAY_SIZE(spd_table_dbe61a); i++) { + if (spd_table_dbe61a[i].address == address) { + ret = spd_table_dbe61a[i].data; + break; + } + } + + if (i == ARRAY_SIZE(spd_table_dbe61a)) + printk(BIOS_DEBUG, " addr %02x does not exist in DBE61A SPD table", + address); } printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret); @@ -151,8 +162,8 @@ } /** - * main for initram for the PC Engines Alix 1C. It might seem that you - * could somehow do these functions in, e.g., the cpu code, but the + * main for initram for the Artec Group ThinCan DBE61. It might seem that + * you could somehow do these functions in, e.g., the cpu code, but the * order of operations and what those operations are is VERY strongly * mainboard dependent. It's best to leave it in the mainboard code. */ @@ -170,8 +181,22 @@ pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO); printk(BIOS_DEBUG, "done pll reset\n"); + printk(BIOS_INFO, "Trying 256MB RAM\n"); initialize_ram(DIMM_DBE61C, DIMM_EMPTY); + /* FIXME: Would like to check around 188MB and 88MB, but that high always + fails, even if everything works fine for a memtest86+ payload */ + if (ram_check(596*1024, 608*1024) == 0) { + printk(BIOS_INFO, "DRAM 256MB configuration OK\n"); + } else { + printk(BIOS_INFO, "Trying 128MB RAM\n"); + initialize_ram(DIMM_DBE61A, DIMM_EMPTY); + if (ram_check(596*1024, 608*1024) == 0) + printk(BIOS_INFO, "DRAM 128MB configuration OK\n"); + else + printk(BIOS_INFO, "DRAM configuration failed\n"); + } + /* Check low memory */ /*ram_check(0x00000000, 640*1024); */

1 0

← Newer
1
...
23
24
25
26
27
28
29
...
49
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot November 2008