coreboot November 2008

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r1017 - in coreboot-v3: mainboard/kontron/986lcd-m southbridge/intel/i82801gx
by svn＠coreboot.org 13 Nov '08

13 Nov '08

Author: rminnich Date: 2008-11-13 18:42:52 +0100 (Thu, 13 Nov 2008) New Revision: 1017 Added: coreboot-v3/southbridge/intel/i82801gx/libsmbus.c coreboot-v3/southbridge/intel/i82801gx/usb_ehci.dts Modified: coreboot-v3/mainboard/kontron/986lcd-m/Makefile coreboot-v3/mainboard/kontron/986lcd-m/dts coreboot-v3/southbridge/intel/i82801gx/Makefile Log: fix compile errors and Ron's Makefile mistake. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/mainboard/kontron/986lcd-m/Makefile =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/Makefile 2008-11-13 17:14:16 UTC (rev 1016) +++ coreboot-v3/mainboard/kontron/986lcd-m/Makefile 2008-11-13 17:42:52 UTC (rev 1017) @@ -28,18 +28,7 @@ INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/intel/i945/raminit.c \ -STAGE2_CHIPSET_SRC=\ - $(src)/southbridge/intel/i82801gx/ac97.c \ - $(src)/southbridge/intel/i82801gx/lpc.c \ - $(src)/southbridge/intel/i82801gx/nic.c \ - $(src)/southbridge/intel/i82801gx/pci.c \ - $(src)/southbridge/intel/i82801gx/pcie.c \ - $(src)/southbridge/intel/i82801gx/sata.c \ - $(src)/southbridge/intel/i82801gx/smbus.c \ - $(src)/southbridge/intel/i82801gx/usb_ehci.c \ - $(src)/southbridge/intel/i82801gx/usb.c \ - $(src)/southbridge/intel/i82801gx/watchdog.c -# $(src)/southbridge/intel/i82801gx/libsmbus.c \ +STAGE2_CHIPSET_SRC= STAGE2_MAINBOARD_SRC = Modified: coreboot-v3/mainboard/kontron/986lcd-m/dts =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-11-13 17:14:16 UTC (rev 1016) +++ coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-11-13 17:42:52 UTC (rev 1017) @@ -181,7 +181,10 @@ pci@1f,0{/* which ich? */ /config/("southbridge/intel/i82801gx/ich7m_dh_lpc.dts"); }; - pci@1f,2{ + pci@1f,1{ + /config/("southbridge/intel/i82801gx/ide.dts"); + }; + pci@1f,2{ /config/("southbridge/intel/i82801gx/sata.dts"); }; pci@1f,3{ Modified: coreboot-v3/southbridge/intel/i82801gx/Makefile =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/Makefile 2008-11-13 17:14:16 UTC (rev 1016) +++ coreboot-v3/southbridge/intel/i82801gx/Makefile 2008-11-13 17:42:52 UTC (rev 1017) @@ -24,9 +24,20 @@ STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82801gx/i82801gx.c STAGE2_CHIPSET_SRC += \ - + $(src)/southbridge/intel/i82801gx/ac97.c \ + $(src)/southbridge/intel/i82801gx/lpc.c \ + $(src)/southbridge/intel/i82801gx/nic.c \ + $(src)/southbridge/intel/i82801gx/pci.c \ + $(src)/southbridge/intel/i82801gx/pcie.c \ + $(src)/southbridge/intel/i82801gx/sata.c \ + $(src)/southbridge/intel/i82801gx/smbus.c \ + $(src)/southbridge/intel/i82801gx/usb_ehci.c \ + $(src)/southbridge/intel/i82801gx/usb.c \ + $(src)/southbridge/intel/i82801gx/watchdog.c \ + $(src)/southbridge/intel/i82801gx/libsmbus.c \ + STAGE0_CHIPSET_SRC += \ $(src)/southbridge/intel/i82801gx/stage1_smbus.c \ -# $(src)/southbridge/intel/i82801gx/libsmbus.c \ + $(src)/southbridge/intel/i82801gx/libsmbus.c \ endif Added: coreboot-v3/southbridge/intel/i82801gx/libsmbus.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/libsmbus.c (rev 0) +++ coreboot-v3/southbridge/intel/i82801gx/libsmbus.c 2008-11-13 17:42:52 UTC (rev 1017) @@ -0,0 +1,193 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Yinghai Lu <yinghailu(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci.h> +#include <statictree.h> +#include <config.h> +#include <io.h> +#include <device/smbus_def.h> +#include "i82801gx.h" + +/* this is very chipset-specific. */ +#define SMBUS_TIMEOUT (100*1000*10) +/* These are common functions used in stage 1 and stage2 */ +void smbus_delay(void) +{ + inb(0x80); +} + +int smbus_wait_until_ready(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while (byte & 1); + return loops ? 0 : -1; +} + +int smbus_wait_until_done(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); + return loops ? 0 : -1; +} + +int smbus_wait_until_blk_done(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while ((byte & (1 << 7)) == 0); + return loops ? 0 : -1; +} + +int do_smbus_read_byte(unsigned device, unsigned address) +{ + unsigned char global_status_register; + unsigned char byte; + + if (smbus_wait_until_ready() < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + /* Set the device I'm talking to */ + outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + /* Set up for a byte data read */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (SMBUS_IO_BASE + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* Clear the data byte... */ + outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Start the command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), + SMBUS_IO_BASE + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done() < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(3 << 5); + + /* Read results of transaction */ + byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + if (global_status_register != (1 << 1)) { + return SMBUS_ERROR; + } + return byte; +} + +/* This function is neither used nor tested by me (Corey Osgood), the author +(Yinghai) probably tested/used it on i82801er */ +int do_smbus_write_block(u16 device, unsigned int length, unsigned int cmd, + unsigned data1, unsigned data2) +{ + u8 byte; + u8 stat; + int i; + + printk(BIOS_ERR, "Untested smbus_write_block called\n"); + /* Clear the PM timeout flags, SECOND_TO_STS */ + outw(inw(0x0400 + 0x66), 0x0400 + 0x66); + + if (smbus_wait_until_ready() < 0) { + return -2; + } + + /* Setup transaction */ + /* Obtain ownership */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + for (stat = 0; (stat & 0x40) == 0;) { + stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } + /* Clear the done bit */ + outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); + + /* Set the command address */ + outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + + /* Set the block length */ + outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Try sending out the first byte of data here */ + byte = (data1 >> (0)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + /* Issue a block write command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40, + SMBUS_IO_BASE + SMBHSTCTL); + + for (i = 0; i < length; i++) { + + /* Poll for transaction completion */ + if (smbus_wait_until_blk_done() < 0) { + return -3; + } + + /* Load the next byte */ + if (i > 3) + byte = (data2 >> (i % 4)) & 0x0ff; + else + byte = (data1 >> (i)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + + /* Clear the done bit */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + SMBUS_IO_BASE + SMBHSTSTAT); + } + + printk(BIOS_DEBUG, "SMBUS Block complete\n"); + + return 0; +} Added: coreboot-v3/southbridge/intel/i82801gx/usb_ehci.dts =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/usb_ehci.dts (rev 0) +++ coreboot-v3/southbridge/intel/i82801gx/usb_ehci.dts 2008-11-13 17:42:52 UTC (rev 1017) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "i82801gx_usb_ehci"; +};

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r1016 - coreboot-v3/mainboard/artecgroup/dbe61
by svn＠coreboot.org 13 Nov '08

13 Nov '08

Author: mraudsepp Date: 2008-11-13 18:14:16 +0100 (Thu, 13 Nov 2008) New Revision: 1016 Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c Log: artecgroup/dbe61: Gather RAM initialization function calls to one helper function. Then we can later use it for re-initializing for different SPD without code duplication. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-11-13 17:12:34 UTC (rev 1015) +++ coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-11-13 17:14:16 UTC (rev 1016) @@ -135,6 +135,21 @@ /* Early mainboard specific GPIO setup */ } +static void initialize_ram(u8 dimm0, u8 dimm1) +{ + cpu_reg_init(0, dimm0, dimm1, DRAM_UNTERMINATED); + printk(BIOS_DEBUG, "done cpu reg init\n"); + + sdram_set_registers(); + printk(BIOS_DEBUG, "done sdram set registers\n"); + + sdram_set_spd_registers(dimm0, dimm1); + printk(BIOS_DEBUG, "done sdram set spd registers\n"); + + sdram_enable(dimm0, dimm1); + printk(BIOS_DEBUG, "done sdram enable\n"); +} + /** * main for initram for the PC Engines Alix 1C. It might seem that you * could somehow do these functions in, e.g., the cpu code, but the @@ -155,18 +170,8 @@ pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO); printk(BIOS_DEBUG, "done pll reset\n"); - cpu_reg_init(0, DIMM_DBE61C, DIMM_EMPTY, DRAM_UNTERMINATED); - printk(BIOS_DEBUG, "done cpu reg init\n"); + initialize_ram(DIMM_DBE61C, DIMM_EMPTY); - sdram_set_registers(); - printk(BIOS_DEBUG, "done sdram set registers\n"); - - sdram_set_spd_registers(DIMM_DBE61C, DIMM_EMPTY); - printk(BIOS_DEBUG, "done sdram set spd registers\n"); - - sdram_enable(DIMM_DBE61C, DIMM_EMPTY); - printk(BIOS_DEBUG, "done sdram enable\n"); - /* Check low memory */ /*ram_check(0x00000000, 640*1024); */

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r1015 - coreboot-v3/mainboard/artecgroup/dbe61
by svn＠coreboot.org 13 Nov '08

13 Nov '08

Author: mraudsepp Date: 2008-11-13 18:12:34 +0100 (Thu, 13 Nov 2008) New Revision: 1015 Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c Log: artecgroup/dbe61: Use dbe61c specific variables and macros instead of generic ones This is in preparation of dbe61a handling addition. Uses DIMM_DBE61C and DIMM_EMPTY instead of generic DIMM0/DIMM1, and spd_table_dbe61c instead of spd_table. Also removes a completely unused smb_devices structure definition. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-11-13 17:04:11 UTC (rev 1014) +++ coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-11-13 17:12:34 UTC (rev 1015) @@ -35,8 +35,8 @@ #define MANUALCONF 0 /* Do automatic strapped PLL config */ #define PLLMSRHI 0x00001490 /* manual settings for the PLL */ #define PLLMSRLO 0x02000030 -#define DIMM0 ((u8) 0xA0) -#define DIMM1 ((u8) 0xA2) +#define DIMM_DBE61C ((u8) 0xA0) +#define DIMM_EMPTY ((u8) 0xA2) struct spd_entry { u8 address; @@ -46,7 +46,7 @@ /* Save space by using a short list of SPD values used by Geode LX Memory init */ /* Fake SPD for DBE61C - 256MB. Same memory chip, and therefore same SPD entries, as for DBE62. */ /* Micron MT46V32M16 */ -static const struct spd_entry spd_table[] = { +static const struct spd_entry spd_table_dbe61c[] = { {SPD_MEMORY_TYPE, 7}, {SPD_NUM_ROWS, 13}, {SPD_tRFC, 0x4b}, @@ -95,7 +95,7 @@ /** * Given an SMBUS device, and an address in that device, return the value of SPD - * for that device. In this mainboard, the only one that can return is DIMM0. + * for that device. In this mainboard, the only one that can return is DIMM_DBE61C. * @param device The device number * @param address The address in SPD rom to return the value of * @returns The value @@ -107,15 +107,15 @@ u8 ret = 0xff; printk(BIOS_DEBUG, "spd_read_byte dev %04x", device); - if (device == DIMM0) { - for (i = 0; i < ARRAY_SIZE(spd_table); i++) { - if (spd_table[i].address == address) { - ret = spd_table[i].data; + if (device == DIMM_DBE61C) { + for (i = 0; i < ARRAY_SIZE(spd_table_dbe61c); i++) { + if (spd_table_dbe61c[i].address == address) { + ret = spd_table_dbe61c[i].data; break; } } - if (i == ARRAY_SIZE(spd_table)) + if (i == ARRAY_SIZE(spd_table_dbe61c)) printk(BIOS_DEBUG, " addr %02x does not exist in SPD table", address); } @@ -155,16 +155,16 @@ pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO); printk(BIOS_DEBUG, "done pll reset\n"); - cpu_reg_init(0, DIMM0, DIMM1, DRAM_UNTERMINATED); + cpu_reg_init(0, DIMM_DBE61C, DIMM_EMPTY, DRAM_UNTERMINATED); printk(BIOS_DEBUG, "done cpu reg init\n"); sdram_set_registers(); printk(BIOS_DEBUG, "done sdram set registers\n"); - sdram_set_spd_registers(DIMM0, DIMM1); + sdram_set_spd_registers(DIMM_DBE61C, DIMM_EMPTY); printk(BIOS_DEBUG, "done sdram set spd registers\n"); - sdram_enable(DIMM0, DIMM1); + sdram_enable(DIMM_DBE61C, DIMM_EMPTY); printk(BIOS_DEBUG, "done sdram enable\n"); /* Check low memory */

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r1014 - in coreboot-v3: include lib
by svn＠coreboot.org 13 Nov '08

13 Nov '08

Author: mraudsepp Date: 2008-11-13 18:04:11 +0100 (Thu, 13 Nov 2008) New Revision: 1014 Modified: coreboot-v3/include/lib.h coreboot-v3/lib/ramtest.c Log: Return the count of failures from ram_check. Will be necessary for DBE61 automatic memory size selection. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/include/lib.h =================================================================== --- coreboot-v3/include/lib.h 2008-11-13 01:53:55 UTC (rev 1013) +++ coreboot-v3/include/lib.h 2008-11-13 17:04:11 UTC (rev 1014) @@ -50,6 +50,6 @@ void beep_long(void); /* Optional ramtest. */ -void ram_check(unsigned long start, unsigned long stop); +int ram_check(unsigned long start, unsigned long stop); #endif /* LIB_H */ Modified: coreboot-v3/lib/ramtest.c =================================================================== --- coreboot-v3/lib/ramtest.c 2008-11-13 01:53:55 UTC (rev 1013) +++ coreboot-v3/lib/ramtest.c 2008-11-13 17:04:11 UTC (rev 1014) @@ -84,7 +84,7 @@ * @param start The beginning of the RAM area. * @param stop The end of the RAM area. */ -static void ram_verify(unsigned long start, unsigned long stop) +static int ram_verify(unsigned long start, unsigned long stop) { unsigned long addr, value; int i = 0; @@ -112,6 +112,7 @@ /* Print whether or not the verify failed. */ printk(BIOS_DEBUG, "\nDRAM range %sverified.", i ? "_NOT_ " : ""); + return i; } /** @@ -123,11 +124,14 @@ * * @param start The beginning of the RAM area. * @param stop The end of the RAM area. + * @return verify failure count */ -void ram_check(unsigned long start, unsigned long stop) +int ram_check(unsigned long start, unsigned long stop) { + int result; printk(BIOS_DEBUG, "Testing DRAM: %lx-%lx\n", start, stop); ram_fill(start, stop); - ram_verify(start, stop); + result = ram_verify(start, stop); printk(BIOS_DEBUG, "Done.\n"); + return result; }

1 0

Is this a correct way to read PCI control space register?
by FENG Yu Ning 13 Nov '08

13 Nov '08

# lspci -xxxnns 0:0.0 00:00.0 Host bridge [0600]: Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub [8086:2770] 00: 86 80 70 27 06 00 90 20 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 53 4e 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 40: 01 90 d1 fe 01 40 d1 fe 03 00 00 f0 01 80 d1 fe 50: 00 00 02 00 03 00 00 00 00 00 00 00 00 00 00 00 60: 01 30 d1 fe 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 11 11 11 11 33 33 00 ff 03 00 00 40 1a 39 00 a0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 91 00 00 00 e0: 09 00 09 71 cb e1 9b 98 07 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 It is the byte at offset 8 makes me questioning. It is the revision identification register. This machine has a 945PL nb. According to Intel's doc(945x specification update 307503-010), the register should have a value of 82. Am I making mistake? BTW, is the 0xe7 byte, with a value of '98', the same byte as the 'reg8' in the following excerpt of v3/northbridge/intel/i945/stage1.c? static void i945_detect_chipset(void) { u8 reg8; printk(BIOS_INFO, "\n"); reg8 = (pci_conf1_read_config8(PCI_BDF(0, 0x00, 0), 0xe7) & 0x70) >> 4; yu ning

3 5

Spi flash
by Dupont Yves 13 Nov '08

13 Nov '08

Hello, I tried to dump my BIOS with flashrom on a SONY VAIO VGN-TX3XP. Verbose mode was enabled : - The southbridge is an ICH7 - it seems to be a SPI flash but the RDID command always returns 0xff. How can I identify my flash? thanks,

3 2

Re: [coreboot] Seabios stop at Harddisk boot.
by JasonZhao＠viatech.com.cn 13 Nov '08

13 Nov '08

I found (hint by ruik=Rudolf ?) it is due to the memory I reserved "004000 - 0000000000029000 = 2". After I remove it from coreboot-v2 coreboot_table.c. seabios+windows work fine. Seabios is very cool. I will try to install windows driver and try s3 then. ________________________________ From: Jason Zhao Sent: Thursday, November 13, 2008 3:30 PM To: 'Kevin O'Connor' Cc: coreboot(a)coreboot.org Subject: Seabios stop at Harddisk boot. The same Coreboot and the same board had boot Linux ok. I try seabios then. Vga has normal output on screen. After I choose to boot from Harddisk, it stop at "fail handle_15XX:314(00000086):" Any idea about this? ------------------------------------------------------------------------ ---------------------------------------------------------------- Copying ACPI RSDP from 1bef0000 to 000ff330 Found 1 cpu(s) SMBIOS table addr=0x000ff350 ram_size=0x1bef0000 Scan for VGA option rom Running option rom at 0000c000:00000003 Turning on vga console Starting SeaBIOS keyboard initialized e820 map has 7 items: 0: 0000000000000000 - 0000000000004000 = 1 1: 0000000000004000 - 0000000000029000 = 2 (((((((((I reserved this, can remove it if needed.)))))))))) 2: 0000000000029000 - 000000000009fc00 = 1 3: 000000000009fc00 - 00000000000a0000 = 2 4: 00000000000f0000 - 0000000000100000 = 2 5: 0000000000100000 - 000000001bef0000 = 1 6: 000000001bef0000 - 000000001bf00000 = 2 final bios_table_addr: 0x000ff45a (used 48%) ATA controller 0 at 000001f0/000003f0 ATA controller 1 at 00000170/00000370 ata1-0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 ata1 master: ST3120213A ATA-7 Hard-Disk (111 GiBytes) ata1 slave: Unknown device Scan for option roms Press F12 for boot menu. Select boot device: 1. Floppy 2. Hard Disk 3. CD-Rom (((((((((I chose Hard Disk)))))))))) Changing serial settings was 00000003/00000002 now 00000003/00000000 enter handle_19: NULL Booting from Hard Disk... Booting from 00000000:00007c00 enter handle_12: a=00000000 b=00000000 c=00000000 d=00000080 si=00002118 di=0000402c ds=00000000 es=00000000 ip=000024c1 cs=00000000 f=00000297 r=00001fd2 enter handle_12: a=00000000 b=00000000 c=00000000 d=00022780 si=00002118 di=00054480 ds=00000000 es=00000000 ip=00008a01 cs=00000000 f=00000297 r=00001fd2 fail get_device:610(00000001): a=00004100 b=000055aa c=fffabad4 d=00054581 si=00067fc8 di=00000081 ds=00000000 es=00000000 ip=000088b5 cs=00000000 f=00000246 r=00001fd2 fail get_device:610(00000001): a=00000800 b=00000000 c=fffabad4 d=00054581 si=00067fc8 di=00000081 ds=00000000 es=00000000 ip=000088e9 cs=00000000 f=00000246 r=00001fd2 fail handle_15XX:314(00000086): a=000000c0 b=00000000 c=fffaba03 d=00000001 si=00054538 di=00067fc8 ds=00000000 es=00000000 ip=00008ab6 cs=00000000 f=00000246 r=00001fd2 ------------------------------------------------------------------------ ------------------------------

3 2

Seabios stop at Harddisk boot.
by JasonZhao＠viatech.com.cn 13 Nov '08

13 Nov '08

The same Coreboot and the same board had boot Linux ok. I try seabios then. Vga has normal output on screen. After I choose to boot from Harddisk, it stop at "fail handle_15XX:314(00000086):" Any idea about this? ------------------------------------------------------------------------ ---------------------------------------------------------------- Copying ACPI RSDP from 1bef0000 to 000ff330 Found 1 cpu(s) SMBIOS table addr=0x000ff350 ram_size=0x1bef0000 Scan for VGA option rom Running option rom at 0000c000:00000003 Turning on vga console Starting SeaBIOS keyboard initialized e820 map has 7 items: 0: 0000000000000000 - 0000000000004000 = 1 1: 0000000000004000 - 0000000000029000 = 2 (((((((((I reserved this, can remove it if needed.)))))))))) 2: 0000000000029000 - 000000000009fc00 = 1 3: 000000000009fc00 - 00000000000a0000 = 2 4: 00000000000f0000 - 0000000000100000 = 2 5: 0000000000100000 - 000000001bef0000 = 1 6: 000000001bef0000 - 000000001bf00000 = 2 final bios_table_addr: 0x000ff45a (used 48%) ATA controller 0 at 000001f0/000003f0 ATA controller 1 at 00000170/00000370 ata1-0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 ata1 master: ST3120213A ATA-7 Hard-Disk (111 GiBytes) ata1 slave: Unknown device Scan for option roms Press F12 for boot menu. Select boot device: 1. Floppy 2. Hard Disk 3. CD-Rom (((((((((I chose Hard Disk)))))))))) Changing serial settings was 00000003/00000002 now 00000003/00000000 enter handle_19: NULL Booting from Hard Disk... Booting from 00000000:00007c00 enter handle_12: a=00000000 b=00000000 c=00000000 d=00000080 si=00002118 di=0000402c ds=00000000 es=00000000 ip=000024c1 cs=00000000 f=00000297 r=00001fd2 enter handle_12: a=00000000 b=00000000 c=00000000 d=00022780 si=00002118 di=00054480 ds=00000000 es=00000000 ip=00008a01 cs=00000000 f=00000297 r=00001fd2 fail get_device:610(00000001): a=00004100 b=000055aa c=fffabad4 d=00054581 si=00067fc8 di=00000081 ds=00000000 es=00000000 ip=000088b5 cs=00000000 f=00000246 r=00001fd2 fail get_device:610(00000001): a=00000800 b=00000000 c=fffabad4 d=00054581 si=00067fc8 di=00000081 ds=00000000 es=00000000 ip=000088e9 cs=00000000 f=00000246 r=00001fd2 fail handle_15XX:314(00000086): a=000000c0 b=00000000 c=fffaba03 d=00000001 si=00054538 di=00067fc8 ds=00000000 es=00000000 ip=00008ab6 cs=00000000 f=00000246 r=00001fd2 ------------------------------------------------------------------------ ------------------------------

2 1

GA-M57SLI-S4 ECC memory.
by John Danks 13 Nov '08

13 Nov '08

Can somebody give a definite answer whether the GA-M57SLI-S4 supports ECC RAM. Did Gigabyte put the necessary traces on the motherboard? There are conflicting results with the Gigabyte Specifications[1] stating that ECC is supported, where as Crucial[2] and Kingston[3] both state that ECC is NOT supported. Does Coreboot support ECC RAM on this board? The GA-M57SLI-S4 tutorial lists ECC RAM as "untested". With the board being EOL I am in the process of retiring these workstations, and resuscitating them as servers with additional RAM. As a workstation ECC RAM did not matter, but now with the extended uptimes I feel it worth replacing memory with ECC RAM. Thanks John. [1] http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI… [2] http://www.crucial.com/eu/store/listparts.aspx?model=GA-M57SLI-S4 [3] http://www.ec.kingston.com/ecom/configurator_new/modelsinfo.asp?SysID=&mfr=…

1 0

[PATCH 3/5] artecgroup/dbe61: Gather RAM initialization function calls to one helper function.
by Mart Raudsepp 13 Nov '08

13 Nov '08

artecgroup/dbe61: Gather RAM initialization function calls to one helper function. Then we can later use it for re-initializing for different SPD without code duplication. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- mainboard/artecgroup/dbe61/initram.c | 27 ++++++++++++++++----------- 1 files changed, 16 insertions(+), 11 deletions(-) diff --git a/mainboard/artecgroup/dbe61/initram.c b/mainboard/artecgroup/dbe61/initram.c index 4a89247..d454e46 100644 --- a/mainboard/artecgroup/dbe61/initram.c +++ b/mainboard/artecgroup/dbe61/initram.c @@ -135,6 +135,21 @@ static void mb_gpio_init(void) /* Early mainboard specific GPIO setup */ } +static void initialize_ram(u8 dimm0, u8 dimm1) +{ + cpu_reg_init(0, dimm0, dimm1, DRAM_UNTERMINATED); + printk(BIOS_DEBUG, "done cpu reg init\n"); + + sdram_set_registers(); + printk(BIOS_DEBUG, "done sdram set registers\n"); + + sdram_set_spd_registers(dimm0, dimm1); + printk(BIOS_DEBUG, "done sdram set spd registers\n"); + + sdram_enable(dimm0, dimm1); + printk(BIOS_DEBUG, "done sdram enable\n"); +} + /** * main for initram for the PC Engines Alix 1C. It might seem that you * could somehow do these functions in, e.g., the cpu code, but the @@ -155,17 +170,7 @@ int main(void) pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO); printk(BIOS_DEBUG, "done pll reset\n"); - cpu_reg_init(0, DIMM_DBE61C, DIMM_EMPTY, DRAM_UNTERMINATED); - printk(BIOS_DEBUG, "done cpu reg init\n"); - - sdram_set_registers(); - printk(BIOS_DEBUG, "done sdram set registers\n"); - - sdram_set_spd_registers(DIMM_DBE61C, DIMM_EMPTY); - printk(BIOS_DEBUG, "done sdram set spd registers\n"); - - sdram_enable(DIMM_DBE61C, DIMM_EMPTY); - printk(BIOS_DEBUG, "done sdram enable\n"); + initialize_ram(DIMM_DBE61C, DIMM_EMPTY); /* Check low memory */ /*ram_check(0x00000000, 640*1024); */ -- 1.6.0.2

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coreboot November 2008