coreboot November 2008

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[PATCH] Fix v3 VIA C7 CAR disable
by Carl-Daniel Hailfinger 13 Nov '08

13 Nov '08

The VIA C7 CAR disable code in v3 had a nasty bug which caused the processor to reset. Fix this bug and actually disable CAR. With this patch v3 has better C7 CAR code than v2 (which skips two key MTRRs). Thanks to Corey Osgood for testing countless debug patches. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Attached for Gmail users. Index: corebootv3-via_car/arch/x86/via/stage1.c =================================================================== --- corebootv3-via_car/arch/x86/via/stage1.c (Revision 980) +++ corebootv3-via_car/arch/x86/via/stage1.c (Arbeitskopie) @@ -56,22 +56,20 @@ __asm__ __volatile__( " movl %[newesp], %%esp \n" -#if ENABLE_BROKEN_CAR_DISABLING /* We don't need cache as ram for now on */ /* disable cache */ " movl %%cr0, %%eax \n" " orl $(0x1<<30),%%eax \n" " movl %%eax, %%cr0 \n" - /* The MTRR setup below causes the machine to reset. Must investigate. */ /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/ - " movl %[_SYSCFG_MSR], %%ecx \n" - " rdmsr \n" - " andl %[_SYSCFG_MSR_newval], %%eax\n" -// " andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %%eax\n" /* clear sth */ + " xorl %%eax, %%eax \n" + " xorl %%edx, %%edx \n" + " movl $0x201, %%ecx \n" " wrmsr \n" -#warning Must clear MTRR 0x200 and 0x201 + " movl $0x200, %%ecx \n" + " wrmsr \n" /* Set the default memory type and disable fixed and enable variable MTRRs */ " movl %[_MTRRdefType_MSR], %%ecx \n" @@ -84,16 +82,11 @@ " movl %%cr0, %%eax \n" " andl $0x9fffffff,%%eax \n" " movl %%eax, %%cr0 \n" -#endif " wbinvd \n" " call stage1_phase3 \n" :: [newesp] "i" (newlocation), - [_SYSCFG_MSR] "i" (SYSCFG_MSR), - [_SYSCFG_MSR_newval] "i" (~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), - [_SYSCFG_MSR_MtrrFixDramModEn] "i" (SYSCFG_MSR_MtrrFixDramModEn), - [_SYSCFG_MSR_MtrrFixDramEn] "i" (SYSCFG_MSR_MtrrFixDramEn), [_MTRRdefType_MSR] "i" (MTRRdefType_MSR) : "memory"); } -- http://www.hailfinger.org/

2 3

r1010 - coreboot-v3/arch/x86/via
by svn＠coreboot.org 13 Nov '08

13 Nov '08

Author: hailfinger Date: 2008-11-13 01:04:55 +0100 (Thu, 13 Nov 2008) New Revision: 1010 Modified: coreboot-v3/arch/x86/via/stage1.c Log: The VIA C7 CAR disable code in v3 had a nasty bug which caused the processor to reset. Fix this bug and actually disable CAR. With this patch v3 has better C7 CAR code than v2 (which skips two key MTRRs). Thanks to Corey Osgood for testing countless debug patches. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/via/stage1.c =================================================================== --- coreboot-v3/arch/x86/via/stage1.c 2008-11-12 23:09:42 UTC (rev 1009) +++ coreboot-v3/arch/x86/via/stage1.c 2008-11-13 00:04:55 UTC (rev 1010) @@ -56,22 +56,20 @@ __asm__ __volatile__( " movl %[newesp], %%esp \n" -#if ENABLE_BROKEN_CAR_DISABLING /* We don't need cache as ram for now on */ /* disable cache */ " movl %%cr0, %%eax \n" " orl $(0x1<<30),%%eax \n" " movl %%eax, %%cr0 \n" - /* The MTRR setup below causes the machine to reset. Must investigate. */ /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/ - " movl %[_SYSCFG_MSR], %%ecx \n" - " rdmsr \n" - " andl %[_SYSCFG_MSR_newval], %%eax\n" -// " andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %%eax\n" /* clear sth */ + " xorl %%eax, %%eax \n" + " xorl %%edx, %%edx \n" + " movl $0x201, %%ecx \n" " wrmsr \n" -#warning Must clear MTRR 0x200 and 0x201 + " movl $0x200, %%ecx \n" + " wrmsr \n" /* Set the default memory type and disable fixed and enable variable MTRRs */ " movl %[_MTRRdefType_MSR], %%ecx \n" @@ -84,16 +82,11 @@ " movl %%cr0, %%eax \n" " andl $0x9fffffff,%%eax \n" " movl %%eax, %%cr0 \n" -#endif " wbinvd \n" " call stage1_phase3 \n" :: [newesp] "i" (newlocation), - [_SYSCFG_MSR] "i" (SYSCFG_MSR), - [_SYSCFG_MSR_newval] "i" (~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), - [_SYSCFG_MSR_MtrrFixDramModEn] "i" (SYSCFG_MSR_MtrrFixDramModEn), - [_SYSCFG_MSR_MtrrFixDramEn] "i" (SYSCFG_MSR_MtrrFixDramEn), [_MTRRdefType_MSR] "i" (MTRRdefType_MSR) : "memory"); }

1 0

[PATCH] Be silent in ram_check in non-debug loglevels
by Mart Raudsepp 13 Nov '08

13 Nov '08

As DBE61 support now runs ram_check for non-debug purposes and has expected failures on DBE61A, downgrade the per-address looped fail notification printk and other messages from BIOS_ERR to BIOS_DEBUG. Document that if something is wanted to be reported in non-debug loglevels, one should do so in the caller based on the return value. Tweak a debug string in ram_verify to be more descriptive. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- lib/ramtest.c | 8 +++++--- 1 files changed, 5 insertions(+), 3 deletions(-) diff --git a/lib/ramtest.c b/lib/ramtest.c index 02a4bdb..8d5c419 100644 --- a/lib/ramtest.c +++ b/lib/ramtest.c @@ -97,11 +97,11 @@ static int ram_verify(unsigned long start, unsigned long stop) value = ram_read_phys(addr); if (value != addr) { /* Display address with error. */ - printk(BIOS_ERR, "Fail @%lx Read value=%lx\n", + printk(BIOS_DEBUG, "Fail @%lx Read value=%lx\n", addr, value); /* Abort after 256 verify errors. */ if (++i > 256) { - printk(BIOS_ERR, "Aborting.\n"); + printk(BIOS_DEBUG, "256 errors seen, aborting.\n"); break; } } @@ -111,7 +111,7 @@ static int ram_verify(unsigned long start, unsigned long stop) printk(BIOS_DEBUG, "%lx\r", addr); /* Print whether or not the verify failed. */ - printk(BIOS_DEBUG, "\nDRAM range %sverified.", i ? "_NOT_ " : ""); + printk(BIOS_DEBUG, "\nDRAM range %sverified.\n", i ? "_NOT_ " : ""); return i; } @@ -121,6 +121,8 @@ static int ram_verify(unsigned long start, unsigned long stop) * * This is much more of a "Is my DRAM properly configured?" test than * a "Is my DRAM faulty?" test, though. + * If you want to show a message of the result in non-debug loglevels, be sure + * to do so yourself based on the return value. * * @param start The beginning of the RAM area. * @param stop The end of the RAM area. -- 1.6.0.2 --=-D7GKVhhl0mDDnt69pmSX--

1 0

r1009 - in coreboot-v3: mainboard/kontron/986lcd-m northbridge/intel/i945 southbridge/intel/i82801gx
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: rminnich Date: 2008-11-13 00:09:42 +0100 (Thu, 13 Nov 2008) New Revision: 1009 Modified: coreboot-v3/mainboard/kontron/986lcd-m/Makefile coreboot-v3/mainboard/kontron/986lcd-m/dts coreboot-v3/northbridge/intel/i945/northbridge.c coreboot-v3/southbridge/intel/i82801gx/Makefile coreboot-v3/southbridge/intel/i82801gx/ac97.c coreboot-v3/southbridge/intel/i82801gx/lpc.c coreboot-v3/southbridge/intel/i82801gx/nic.c coreboot-v3/southbridge/intel/i82801gx/pci.c coreboot-v3/southbridge/intel/i82801gx/pcie.c coreboot-v3/southbridge/intel/i82801gx/sata.c coreboot-v3/southbridge/intel/i82801gx/sata.dts coreboot-v3/southbridge/intel/i82801gx/smbus.c Log: Fewer errors. The weird part: I had to move all the i82801gx south files to be compiled to the mainboard. Why? Because the board doesn't use ide support. So you can't compile that in, it's not in the dts. the mainboard Makefile picks the southbridge .c's to use. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/kontron/986lcd-m/Makefile =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/Makefile 2008-11-12 22:43:50 UTC (rev 1008) +++ coreboot-v3/mainboard/kontron/986lcd-m/Makefile 2008-11-12 23:09:42 UTC (rev 1009) @@ -28,6 +28,18 @@ INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/intel/i945/raminit.c \ +STAGE2_CHIPSET_SRC=\ + $(src)/southbridge/intel/i82801gx/ac97.c \ + $(src)/southbridge/intel/i82801gx/lpc.c \ + $(src)/southbridge/intel/i82801gx/nic.c \ + $(src)/southbridge/intel/i82801gx/pci.c \ + $(src)/southbridge/intel/i82801gx/pcie.c \ + $(src)/southbridge/intel/i82801gx/sata.c \ + $(src)/southbridge/intel/i82801gx/smbus.c \ + $(src)/southbridge/intel/i82801gx/usb_ehci.c \ + $(src)/southbridge/intel/i82801gx/usb.c \ + $(src)/southbridge/intel/i82801gx/watchdog.c +# $(src)/southbridge/intel/i82801gx/libsmbus.c \ STAGE2_MAINBOARD_SRC = Modified: coreboot-v3/mainboard/kontron/986lcd-m/dts =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-11-12 22:43:50 UTC (rev 1008) +++ coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-11-12 23:09:42 UTC (rev 1009) @@ -181,6 +181,13 @@ pci@1f,0{/* which ich? */ /config/("southbridge/intel/i82801gx/ich7m_dh_lpc.dts"); }; + pci@1f,2{ + /config/("southbridge/intel/i82801gx/sata.dts"); + }; + pci@1f,3{ + /config/("southbridge/intel/i82801gx/smbus.dts"); + }; + }; ioport@2e { /config/("superio/winbond/w83627thg/dts"); Modified: coreboot-v3/northbridge/intel/i945/northbridge.c =================================================================== --- coreboot-v3/northbridge/intel/i945/northbridge.c 2008-11-12 22:43:50 UTC (rev 1008) +++ coreboot-v3/northbridge/intel/i945/northbridge.c 2008-11-12 23:09:42 UTC (rev 1009) @@ -28,7 +28,7 @@ #include <config.h> #include "i945.h" -static void ram_resource(struct device * dev, unsigned long index, unsigned long basek, +static void i945_ram_resource(struct device * dev, unsigned long index, unsigned long basek, unsigned long sizek) { struct resource *resource; @@ -40,7 +40,7 @@ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void pci_domain_read_resources(struct device * dev) +static void I945_pci_domain_read_resources(struct device * dev) { struct resource *resource; @@ -90,7 +90,7 @@ return tolm; } -static void pci_domain_set_resources(struct device * dev) +static void I945_pci_domain_set_resources(struct device * dev) { u32 pci_tolm; u8 tolud, reg8; @@ -152,22 +152,22 @@ /* The following needs to be 2 lines, otherwise the second * number is always 0 */ - printk(BIOS_INFO, "Available memory: %dK", tomk); - printk(BIOS_INFO, " (%dM)\n", (tomk >> 10)); + printk(BIOS_INFO, "Available memory: %lldK", tomk); + printk(BIOS_INFO, " (%lldM)\n", (tomk >> 10)); tolmk = tomk; /* Report the memory regions */ - ram_resource(dev, 3, 0, 640); - ram_resource(dev, 4, 768, (tolmk - 768)); + i945_ram_resource(dev, 3, 0, 640); + i945_ram_resource(dev, 4, 768, (tolmk - 768)); if (tomk > 4 * 1024 * 1024) { - ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024); + i945_ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024); } assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(struct device * dev, unsigned int max) +static unsigned int i945_pci_domain_scan_bus(struct device * dev, unsigned int max) { max = pci_scan_bus(&dev->link[0], 0, 0xff, max); /* TODO We could determine how many PCIe busses we need in @@ -176,15 +176,16 @@ return max; } +#warning get number of 945 pci domain ops struct device_operations i945_pci_domain_ops = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_INTEL, - .device = anumber}}}, + .device = 0x6789}}}, .constructor = default_device_constructor, .reset_bus = pci_bus_reset, - .phase3_scan = pci_domain_scan_bus, - .phase4_read_resources = pci_domain_read_resources, - .phase4_set_resources = pci_domain_set_resources, + .phase3_scan = i945_pci_domain_scan_bus, + .phase4_read_resources = I945_pci_domain_read_resources, + .phase4_set_resources = I945_pci_domain_set_resources, .phase5_enable_resources = enable_childrens_resources, .phase6_init = NULL, .ops_pci = &pci_dev_ops_pci, @@ -208,8 +209,8 @@ resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08x-0x%08x.\n", - resource->base, (resource->base + resource->size)); + printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08llx.\n", + (u64) resource->base, (u64) (resource->base + resource->size)); } static void mc_set_resources(struct device * dev) @@ -260,7 +261,7 @@ } #warning get a number of the 945 mc -struct device_operations i945_mc_ops = { +struct device_operations i945_cpu_ops = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_INTEL, .device = 0x1233}}}, @@ -268,6 +269,6 @@ .phase4_read_resources = cpu_bus_noop, .phase4_set_resources = cpu_bus_noop, .phase5_enable_resources = cpu_bus_noop, - .phase6_init = Ncpu_bus_initULL, + .phase6_init = cpu_bus_init, .ops_pci = &intel_pci_ops, }; Modified: coreboot-v3/southbridge/intel/i82801gx/Makefile =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/Makefile 2008-11-12 22:43:50 UTC (rev 1008) +++ coreboot-v3/southbridge/intel/i82801gx/Makefile 2008-11-12 23:09:42 UTC (rev 1009) @@ -24,18 +24,6 @@ STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82801gx/i82801gx.c STAGE2_CHIPSET_SRC += \ - $(src)/southbridge/intel/i82801gx/ac97.c \ - $(src)/southbridge/intel/i82801gx/ide.c \ - $(src)/southbridge/intel/i82801gx/lpc.c \ - $(src)/southbridge/intel/i82801gx/nic.c \ - $(src)/southbridge/intel/i82801gx/pci.c \ - $(src)/southbridge/intel/i82801gx/pcie.c \ - $(src)/southbridge/intel/i82801gx/sata.c \ - $(src)/southbridge/intel/i82801gx/smbus.c \ - $(src)/southbridge/intel/i82801gx/usb_ehci.c \ - $(src)/southbridge/intel/i82801gx/usb.c \ - $(src)/southbridge/intel/i82801gx/watchdog.c -# $(src)/southbridge/intel/i82801gx/libsmbus.c \ STAGE0_CHIPSET_SRC += \ $(src)/southbridge/intel/i82801gx/stage1_smbus.c \ Modified: coreboot-v3/southbridge/intel/i82801gx/ac97.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/ac97.c 2008-11-12 22:43:50 UTC (rev 1008) +++ coreboot-v3/southbridge/intel/i82801gx/ac97.c 2008-11-12 23:09:42 UTC (rev 1009) @@ -38,7 +38,7 @@ { // XXX init modem? } - +void i82801gx_enable(struct device * dev); /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ /* Note: 82801GU (ICH7-U) doesn't have AC97 audio. */ struct device_operations ac97audio = { Modified: coreboot-v3/southbridge/intel/i82801gx/lpc.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/lpc.c 2008-11-12 22:43:50 UTC (rev 1008) +++ coreboot-v3/southbridge/intel/i82801gx/lpc.c 2008-11-12 23:09:42 UTC (rev 1009) @@ -25,6 +25,7 @@ #include <msr.h> #include <legacy.h> #include <device/pci_ids.h> +#include <io.h> #include <statictree.h> #include <config.h> #include "i82801gx.h" @@ -144,7 +145,7 @@ reg8 |= (3 << 4); /* avoid #S4 assertions */ pci_write_config8(dev, GEN_PMCON_3, reg8); - printk_info("Set power %s after power failure.\n", pwr_on ? "on" : "off"); + printk(BIOS_INFO, "Set power %s after power failure.\n", pwr_on ? "on" : "off"); /* Set up NMI on errors. */ reg8 = inb(0x61); @@ -329,7 +330,7 @@ static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, }; - +void i82801gx_enable(struct device * dev); /* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ struct device_operations ich7_ich7r_ich7dh_lpc = { .id = {.type = DEVICE_ID_PCI, Modified: coreboot-v3/southbridge/intel/i82801gx/nic.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/nic.c 2008-11-12 22:43:50 UTC (rev 1008) +++ coreboot-v3/southbridge/intel/i82801gx/nic.c 2008-11-12 23:09:42 UTC (rev 1009) @@ -38,7 +38,7 @@ /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ /* Note: 82801GU (ICH7-U) doesn't have a NIC. */ /* PCI ID loaded from EEPROM. If EEPROM is 0, 0x27dc is used. */ -struct device_operations = { +struct device_operations i82801gx_nic= { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_INTEL, .device = 0x27dc}}}, Modified: coreboot-v3/southbridge/intel/i82801gx/pci.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/pci.c 2008-11-12 22:43:50 UTC (rev 1008) +++ coreboot-v3/southbridge/intel/i82801gx/pci.c 2008-11-12 23:09:42 UTC (rev 1009) @@ -61,7 +61,7 @@ /* Set the subsystem vendor and device id for mainboard devices */ ops = ops_pci(dev); if (dev->on_mainboard && ops && ops->set_subsystem) { - printk_debug("%s subsystem <- %02x/%02x\n", + printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n", dev_path(dev), MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); @@ -77,7 +77,7 @@ */ command = pci_read_config16(dev, PCI_COMMAND); command |= dev->command; - printk_debug("%s cmd <- %02x\n", dev_path(dev), command); + printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command); pci_write_config16(dev, PCI_COMMAND, command); #endif } @@ -93,7 +93,7 @@ ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); ctrl |= dev->link[0].bridge_ctrl; ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */ - printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); + printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); /* This is the reason we need our own pci_bus_enable_resources */ @@ -102,7 +102,7 @@ enable_childrens_resources(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device * dev, u16 vendor, u16 device) { #if 0 /* Currently disabled because it causes a "BAR 9" memory resource @@ -110,7 +110,7 @@ */ u32 pci_id; - printk_debug("Setting PCI bridge subsystem ID\n"); + printk(BIOS_DEBUG, "Setting PCI bridge subsystem ID\n"); pci_id = pci_read_config32(dev, 0); pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_id ); #endif Modified: coreboot-v3/southbridge/intel/i82801gx/pcie.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/pcie.c 2008-11-12 22:43:50 UTC (rev 1008) +++ coreboot-v3/southbridge/intel/i82801gx/pcie.c 2008-11-12 23:09:42 UTC (rev 1009) @@ -67,7 +67,7 @@ printk(BIOS_DEBUG, " PMLU32 = 0x%08x\n", reg32); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device * dev, u16 vendor, u16 device) { u32 pci_id; Modified: coreboot-v3/southbridge/intel/i82801gx/sata.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/sata.c 2008-11-12 22:43:50 UTC (rev 1008) +++ coreboot-v3/southbridge/intel/i82801gx/sata.c 2008-11-12 23:09:42 UTC (rev 1009) @@ -29,7 +29,7 @@ #include <config.h> #include "i82801gx.h" -typedef struct southbridge_intel_i82801gx_config config_t; +typedef struct southbridge_intel_i82801gx_sata_config config_t; static void sata_init(struct device *dev) { @@ -139,16 +139,7 @@ pci_write_config32(dev, 0xa4, reg32); pci_write_config8(dev, 0xa0, 0x00); } - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = , - .init = , - .scan_bus = 0, - .enable = i82801gx_enable, -}; - +void i82801gx_enable(struct device * dev); /* Desktop Non-AHCI and Non-RAID Mode */ /* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ struct device_operations i82801gx_sata_normal_driver = { Modified: coreboot-v3/southbridge/intel/i82801gx/sata.dts =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/sata.dts 2008-11-12 22:43:50 UTC (rev 1008) +++ coreboot-v3/southbridge/intel/i82801gx/sata.dts 2008-11-12 23:09:42 UTC (rev 1009) @@ -20,4 +20,9 @@ { device_operations = "i82801gx_sata_normal_driver"; + ide_legacy_combined = "0"; + ide_enable_primary = "0"; + ide_enable_secondary = "0"; + sata_ahci = "0"; }; + Modified: coreboot-v3/southbridge/intel/i82801gx/smbus.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/smbus.c 2008-11-12 22:43:50 UTC (rev 1008) +++ coreboot-v3/southbridge/intel/i82801gx/smbus.c 2008-11-12 23:09:42 UTC (rev 1009) @@ -25,12 +25,13 @@ #include <msr.h> #include <legacy.h> #include <device/pci_ids.h> +#include <device/smbus.h> #include <statictree.h> #include <config.h> #include "i82801gx.h" -#include "i82801_smbus.h" +#include "i82801gx_smbus.h" -int smbus_read_byte(struct bus *bus, device_t dev, u8 address) +int smbus_read_byte(struct bus *bus, struct device * dev, u8 address) { u16 device; struct resource *res; @@ -44,6 +45,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .read_byte = smbus_read_byte, }; +void i82801gx_enable(struct device * dev) /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */ struct device_operations i82801gx_smbus = {

1 0

r1008 - in coreboot-v3: arch/x86/intel/core2 mainboard/kontron/986lcd-m northbridge/intel/i945 southbridge/intel/i82801gx
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: rminnich Date: 2008-11-12 23:43:50 +0100 (Wed, 12 Nov 2008) New Revision: 1008 Modified: coreboot-v3/arch/x86/intel/core2/stage0.S coreboot-v3/mainboard/kontron/986lcd-m/Makefile coreboot-v3/northbridge/intel/i945/Makefile coreboot-v3/northbridge/intel/i945/northbridge.c coreboot-v3/southbridge/intel/i82801gx/Makefile coreboot-v3/southbridge/intel/i82801gx/usb.c Log: I'm committing often as I don't want people to run over each other (and I am waiting on BlueGene to schedule me and keep getting called away ... waiting for 1024 procs takes patience!) Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/intel/core2/stage0.S =================================================================== --- coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-12 22:23:46 UTC (rev 1007) +++ coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-12 22:43:50 UTC (rev 1008) @@ -18,12 +18,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE -#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE -#define post_code(x) intel_chip_post_macro(x) +#define ASSEMBLY +#define CACHE_AS_RAM_SIZE CONFIG_CARSIZE +#define CACHE_AS_RAM_BASE CONFIG_CARBASE -#include <cpu/x86/mtrr.h> -#include <cpu/amd/mtrr.h> +#include <mtrr.h> #include <macros.h> @@ -67,7 +66,7 @@ cache_as_ram: #if USE_FALLBACK_IMAGE == 1 - post_code(0x20) + port80_post(0x20) /* Send INIT IPI to all excluding ourself */ movl $0x000C4500, %eax @@ -164,11 +163,11 @@ movl %esp, %ebp pushl %eax - post_code(0x23) + port80_post(0x23) call stage1_phase1 - post_code(0x2f) + port80_post(0x2f) error: hlt jmp error Modified: coreboot-v3/mainboard/kontron/986lcd-m/Makefile =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/Makefile 2008-11-12 22:23:46 UTC (rev 1007) +++ coreboot-v3/mainboard/kontron/986lcd-m/Makefile 2008-11-12 22:43:50 UTC (rev 1008) @@ -26,7 +26,7 @@ INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ - $(src)/northbridge/northbridge/intel/i945/raminit.c \ + $(src)/northbridge/intel/i945/raminit.c \ STAGE2_MAINBOARD_SRC = Modified: coreboot-v3/northbridge/intel/i945/Makefile =================================================================== --- coreboot-v3/northbridge/intel/i945/Makefile 2008-11-12 22:23:46 UTC (rev 1007) +++ coreboot-v3/northbridge/intel/i945/Makefile 2008-11-12 22:43:50 UTC (rev 1008) @@ -21,11 +21,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I945),y) -STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i945/get_sblk_pci1234.c \ - $(src)/northbridge/intel/i945/common.c \ - $(src)/northbridge/intel/i945/cpu.c \ - $(src)/northbridge/intel/i945/domain.c \ - $(src)/northbridge/intel/i945/pci.c \ - $(src)/northbridge/intel/i945/util.c +STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i945/northbridge.c \ endif Modified: coreboot-v3/northbridge/intel/i945/northbridge.c =================================================================== --- coreboot-v3/northbridge/intel/i945/northbridge.c 2008-11-12 22:23:46 UTC (rev 1007) +++ coreboot-v3/northbridge/intel/i945/northbridge.c 2008-11-12 22:43:50 UTC (rev 1008) @@ -259,10 +259,11 @@ { } +#warning get a number of the 945 mc struct device_operations i945_mc_ops = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_INTEL, - .device = anu,ber}}}, + .device = 0x1233}}}, .constructor = default_device_constructor, .phase4_read_resources = cpu_bus_noop, .phase4_set_resources = cpu_bus_noop, Modified: coreboot-v3/southbridge/intel/i82801gx/Makefile =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/Makefile 2008-11-12 22:23:46 UTC (rev 1007) +++ coreboot-v3/southbridge/intel/i82801gx/Makefile 2008-11-12 22:43:50 UTC (rev 1008) @@ -32,13 +32,13 @@ $(src)/southbridge/intel/i82801gx/pcie.c \ $(src)/southbridge/intel/i82801gx/sata.c \ $(src)/southbridge/intel/i82801gx/smbus.c \ - $(src)/southbridge/intel/i82801gx/libsmbus.c \ $(src)/southbridge/intel/i82801gx/usb_ehci.c \ $(src)/southbridge/intel/i82801gx/usb.c \ $(src)/southbridge/intel/i82801gx/watchdog.c +# $(src)/southbridge/intel/i82801gx/libsmbus.c \ STAGE0_CHIPSET_SRC += \ $(src)/southbridge/intel/i82801gx/stage1_smbus.c \ - $(src)/southbridge/intel/i82801gx/libsmbus.c \ +# $(src)/southbridge/intel/i82801gx/libsmbus.c \ endif Modified: coreboot-v3/southbridge/intel/i82801gx/usb.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/usb.c 2008-11-12 22:23:46 UTC (rev 1007) +++ coreboot-v3/southbridge/intel/i82801gx/usb.c 2008-11-12 22:43:50 UTC (rev 1008) @@ -46,6 +46,7 @@ printk(BIOS_DEBUG, "done.\n"); } +void i82801gx_enable(struct device * dev); /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */ struct device_operations i82801gb_usb1 = {

1 0

r1007 - in coreboot-v3: mainboard/kontron/986lcd-m northbridge/intel/i945 southbridge/intel/i82801gx
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: rminnich Date: 2008-11-12 23:23:46 +0100 (Wed, 12 Nov 2008) New Revision: 1007 Added: coreboot-v3/southbridge/intel/i82801gx/pcie1.dts Modified: coreboot-v3/mainboard/kontron/986lcd-m/dts coreboot-v3/mainboard/kontron/986lcd-m/stage1.c coreboot-v3/northbridge/intel/i945/bus.dts coreboot-v3/northbridge/intel/i945/mc.dts coreboot-v3/northbridge/intel/i945/northbridge.dts Log: more cleanup, and an attempt at a mainboard dts for the kontron. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/kontron/986lcd-m/dts =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-11-12 18:30:13 UTC (rev 1006) +++ coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-11-12 22:23:46 UTC (rev 1007) @@ -35,7 +35,7 @@ end device pci 02.1 on end # display controller - chip southbridge/intel/i82801gx + chip southbridge/intel/i82801gx/i82801gx register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x1" @@ -138,53 +138,52 @@ */ /{ - device_operations="dbm690t"; - mainboard_vendor = "AMD"; - mainboard_name = "Serengeti"; + mainboard_vendor = "kontron"; + mainboard_name = "986lcd-m"; cpus { }; apic@0 { }; domain@0 { - /config/("northbridge/amd/k8/domain"); - pci@1,0{ - }; + /config/("northbridge/intel/i945/northbridge.dts"); /* guesses; we need a real lspci */ - pci0@18,0 { - /config/("northbridge/amd/k8/pci"); - /* make sure that the ht device is first, as it controls many other things. */ - pci0 { - /config/("southbridge/amd/rs690/ht.dts"); - }; - pci1{ - /config/("southbridge/amd/rs690/gfx.dts"); - }; - pci2{ - /config/("southbridge/amd/rs690/pcie.dts"); - }; - pci4{ - /config/("southbridge/amd/sb600/hda.dts"); - }; - pci5{ - /config/("southbridge/amd/sb600/usb.dts"); - }; - pci6{ - /config/("southbridge/amd/sb600/usb2.dts"); - }; + pci@0,0 { + /config/("northbridge/intel/i945/bus.dts"); + pci@1b,0 { + /config/("southbridge/intel/i82801gx/ac97audio.dts"); + }; + pci@1c,0 { + /config/("southbridge/intel/i82801gx/pcie1.dts"); + }; + pci@1c,1 { + /config/("southbridge/intel/i82801gx/pcie2.dts"); + }; + pci@1c,2{ + /config/("southbridge/intel/i82801gx/pcie3.dts"); + }; + pci@1d,0{ + /config/("southbridge/intel/i82801gx/usb1.dts"); + }; + pci@1d,1{ + /config/("southbridge/intel/i82801gx/usb2.dts"); + }; + pci@1d,2{ + /config/("southbridge/intel/i82801gx/usb3.dts"); + }; + pci@1d,3{ + /config/("southbridge/intel/i82801gx/usb4.dts"); + }; + pci@1d,7{ + /config/("southbridge/intel/i82801gx/usb_ehci.dts"); + }; + pci@1e,0{ + /config/("southbridge/intel/i82801gx/pci.dts"); + }; + pci@1f,0{/* which ich? */ + /config/("southbridge/intel/i82801gx/ich7m_dh_lpc.dts"); + }; }; - pci1@18,0 { - /config/("northbridge/amd/k8/pci"); - }; - pci2@18,0 { - /config/("northbridge/amd/k8/pci"); - /* just for illustrating link #2 */ - pci@2,0{ - }; - }; - pci@18,1 {}; - pci@18,2 {}; - pci@18,3 {}; ioport@2e { - /config/("superio/ite/it8712f/dts"); + /config/("superio/winbond/w83627thg/dts"); com1enable = "1"; }; }; Modified: coreboot-v3/mainboard/kontron/986lcd-m/stage1.c =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/stage1.c 2008-11-12 18:30:13 UTC (rev 1006) +++ coreboot-v3/mainboard/kontron/986lcd-m/stage1.c 2008-11-12 22:23:46 UTC (rev 1007) @@ -287,7 +287,6 @@ reg32 |= (5 << 16); RCBA32(0x2034) = reg32; } -#warning need to fix up hardware_stage1 and move parts to initram.c void hardware_stage1(void) { void early_superio_config_w83627thg(void); Modified: coreboot-v3/northbridge/intel/i945/bus.dts =================================================================== --- coreboot-v3/northbridge/intel/i945/bus.dts 2008-11-12 18:30:13 UTC (rev 1006) +++ coreboot-v3/northbridge/intel/i945/bus.dts 2008-11-12 22:23:46 UTC (rev 1007) @@ -17,7 +17,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -\ { device_operations = "i945_bus_ops"; }; Modified: coreboot-v3/northbridge/intel/i945/mc.dts =================================================================== --- coreboot-v3/northbridge/intel/i945/mc.dts 2008-11-12 18:30:13 UTC (rev 1006) +++ coreboot-v3/northbridge/intel/i945/mc.dts 2008-11-12 22:23:46 UTC (rev 1007) @@ -17,7 +17,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -\ { device_operations = "i945_mc_ops"; }; Modified: coreboot-v3/northbridge/intel/i945/northbridge.dts =================================================================== --- coreboot-v3/northbridge/intel/i945/northbridge.dts 2008-11-12 18:30:13 UTC (rev 1006) +++ coreboot-v3/northbridge/intel/i945/northbridge.dts 2008-11-12 22:23:46 UTC (rev 1007) @@ -17,7 +17,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -\ { device_operations = "i945_pci_domain_ops"; }; Added: coreboot-v3/southbridge/intel/i82801gx/pcie1.dts =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/pcie1.dts (rev 0) +++ coreboot-v3/southbridge/intel/i82801gx/pcie1.dts 2008-11-12 22:23:46 UTC (rev 1007) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "i82801gx_pcie_port1"; +};

1 0

### Bios
by Steve Spano 12 Nov '08

12 Nov '08

Hello Is anyone aware of a 2Mbyte PLCC32 BIOS flash prom that can be used with the AMD LX800 / CS5536? I would like to use coreboot V2 to directly launch the Linux kernel as an ELF payload and then use a YAFFS2 filesystem to access a NAND flash on the IDE bus. Any thoughts would also be appreciated - thank you Steve Spano, President Finger Lakes Engineering

5 8

r3751 build service
by coreboot information 12 Nov '08

12 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "mjones" checked in revision 3751 to the coreboot source repository and caused the following changes: Change Log: Add another AM2 cpuid to the name string. Also, colapse the cases for duplicate strings to save some space. Signed-off-by: Marc Jones <marcj303(a)yahoo.com> Acked-by: Chris Lingard <chris(a)stockwith.co.uk> Build Log: Compilation of intel:jarrell has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3751&device=jarrell&vendor… Compilation of supermicro:x6dhr_ig has been fixed If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

AMD Athlon(tm) dual core processor, (X2 AM2 ,,,,)
by Chris Lingard 12 Nov '08

12 Nov '08

Coreboot fails to identify this cpu correctly, so I hacked processer_name .c as follows u32 Test; Test = cpuid_ebx(0x80000001); printk_debug("cpuid_ebx %x\n", Test); BrandId = Test & 0xffff; Test = cpuid_eax(0x80000001); printk_debug("cpuid_eax %x\n", Test); Socket = (Test & 0x00000030) >> 4; // 00b = S1g1, 01b = F (1207), 11b = AM2 Test = cpuid_ecx(0x80000008); printk_debug("cpuid_ecx %x\n", Test); CmpCap = Test & 0x03; // Number of CPU cores Each core is tested and both return the following. cpuid_ebx 9a3 cpuid_eax 40f33 cpuid_ecx 1 After a bit of desk checking, either a shift is wrong, or the lookup value in the following case statement is wrong. The following hack fixes it /* Original code commented out, the second shift is increaed by 1 PwrLmt = ((BrandId >> 14) & 0x01) | ((BrandId >> 5) & 0x0e); // BrandId[8:6,14] */ PwrLmt = ((BrandId >> 14) & 0x01) | ((BrandId >> 6) & 0x0e); // BrandId[8:6,14] On the other hand the value in the case statement case 0x31046: processor_name_string = "AMD Athlon(tm) 64 X2 Dual Core Processor TT00+"; should be 0x3104c I do not know which The above module tests each core for number of cores, so this will always be 1. It treats it as a two CPU machine. Does this make any difference? The calculation for number of cores could be dropped. Chris Lingard

2 5

r3751 - trunk/coreboot-v2/src/cpu/amd/model_fxx
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: mjones Date: 2008-11-12 21:38:51 +0100 (Wed, 12 Nov 2008) New Revision: 3751 Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/processor_name.c Log: Add another AM2 cpuid to the name string. Also, colapse the cases for duplicate strings to save some space. Signed-off-by: Marc Jones <marcj303(a)yahoo.com> Acked-by: Chris Lingard <chris(a)stockwith.co.uk> Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/processor_name.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/processor_name.c 2008-11-12 19:08:58 UTC (rev 3750) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/processor_name.c 2008-11-12 20:38:51 UTC (rev 3751) @@ -233,17 +233,11 @@ break; /* Socket AM2 */ case 0x30044: - processor_name_string = - "AMD Athlon(tm) 64 Processor TT00+"; - break; case 0x30048: processor_name_string = "AMD Athlon(tm) 64 Processor TT00+"; break; case 0x30064: - processor_name_string = - "AMD Sempron(tm) Processor TT00+"; - break; case 0x30068: processor_name_string = "AMD Sempron(tm) Processor TT00+"; @@ -257,14 +251,9 @@ "Dual-Core AMD Opteron(tm) Processor 12RR SE"; break; case 0x31042: - processor_name_string = - "AMD Athlon(tm) 64 X2 Dual Core Processor TT00+"; - break; case 0x31046: - processor_name_string = - "AMD Athlon(tm) 64 X2 Dual Core Processor TT00+"; - break; case 0x31048: + case 0x3104c: processor_name_string = "AMD Athlon(tm) 64 X2 Dual Core Processor TT00+"; break;

1 0

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coreboot November 2008