coreboot November 2008

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Re: [coreboot] r1002 - in coreboot-v3/arch/x86: . intel/core2
by Carl-Daniel Hailfinger 12 Nov '08

12 Nov '08

On 12.11.2008 15:12, svn(a)coreboot.org wrote: > Author: stepan > Date: 2008-11-12 15:12:32 +0100 (Wed, 12 Nov 2008) > New Revision: 1002 > > Added: > coreboot-v3/arch/x86/intel/core2/stage0.S > Modified: > coreboot-v3/arch/x86/Makefile > Log: > initial intel core car code. > > Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> > Acked-by: Stefan Reinauer <stepan(a)coresystems.de> > Hey, that's unfair! ;-) I was working on exactly the same piece of code. Oh well. I'll prepare my cleanup patches for v3, then. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 2

r1003 - coreboot-v3/mainboard/kontron
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: stepan Date: 2008-11-12 17:57:33 +0100 (Wed, 12 Nov 2008) New Revision: 1003 Added: coreboot-v3/mainboard/kontron/Kconfig Log: fix make menuconfig Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: coreboot-v3/mainboard/kontron/Kconfig =================================================================== --- coreboot-v3/mainboard/kontron/Kconfig (rev 0) +++ coreboot-v3/mainboard/kontron/Kconfig 2008-11-12 16:57:33 UTC (rev 1003) @@ -0,0 +1,44 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 coresystems GmbH +## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_KONTRON + +config BOARD_KONTRON_986LCD_M + bool "986LCD-M" + select ARCH_X86 + select CPU_INTEL_CORE2 + select OPTION_TABLE + select NORTHBRIDGE_INTEL_I945 + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + help + Kontron 986LCD-M Series mainboards + +endchoice + +config MAINBOARD_DIR + string + default kontron/986lcd-m + depends BOARD_KONTRON_986LCD_M +

1 0

"make AVOIDCOMBINE=1" in seabils@git and prompt error
by JasonZhao＠viatech.com.cn 12 Nov '08

12 Nov '08

I have try this make command today and yesterday, and the result (below) tell me that "out/bios.bin.elf" Is not found. Can any body send me a usable version of seabios source. I know it is better to call for help on IRC, but I can not connect it. (Since irc.freenode.net has dynamic IP address, VIA's firewall can not open a port for all IP.) ------------------------------------------------------------------------ -------------------------------------------- root@jason-desktop:/home/jason/Public/seabios1111# make AVOIDCOMBINE=1 Compiling whole program out/blob.16.s In file included from out/blob.16.s.tmp.c:3: out/../src/floppy.c: In function 'floppy_drive_setup': out/../src/floppy.c:70: warning: dereferencing type-punned pointer will break strict-aliasing rules out/../src/floppy.c:73: warning: dereferencing type-punned pointer will break strict-aliasing rules In file included from out/blob.16.s.tmp.c:4: out/../src/ata.c: In function 'ata_reset': out/../src/ata.c:118: warning: dereferencing type-punned pointer will break strict-aliasing rules out/../src/ata.c:119: warning: dereferencing type-punned pointer will break strict-aliasing rules .... .... Many lines .... out/../src/pcibios.c: In function 'handle_1ab10e': out/../src/pcibios.c:120: warning: dereferencing type-punned pointer will break strict-aliasing rules out/../src/pcibios.c:127: warning: dereferencing type-punned pointer will break strict-aliasing rules out/../src/pcibios.c:128: warning: dereferencing type-punned pointer will break strict-aliasing rules out/../src/pcibios.c:137: warning: dereferencing type-punned pointer will break strict-aliasing rules out/../src/pcibios.c:138: warning: dereferencing type-punned pointer will break strict-aliasing rules out/../src/pcibios.c:144: warning: dereferencing type-punned pointer will break strict-aliasing rules Moving data sections to text in out/font.16.s Generating assembler for src/cbt.c Moving data sections to text in out/cbt.16.s Generating assembler for src/floppy_dbt.c Moving data sections to text in out/floppy_dbt.16.s Generating 16bit layout of out/romlayout16.o Compiling whole program out/romlayout32.o Precompiling src/rombios32.lds.S Linking (no relocs) out/rom32.o Precompiling src/rombios16.lds.S Linking out/rom16.o Precompiling src/rombios.lds.S Linking out/rom.o Prepping out/bios.bin.elf : No such file or directory make: *** [out/bios.bin.elf] Error 127 ------------------------------------------------------------------------ --------------------------------------------

3 5

r1002 - in coreboot-v3/arch/x86: . intel/core2
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: stepan Date: 2008-11-12 15:12:32 +0100 (Wed, 12 Nov 2008) New Revision: 1002 Added: coreboot-v3/arch/x86/intel/core2/stage0.S Modified: coreboot-v3/arch/x86/Makefile Log: initial intel core car code. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/arch/x86/Makefile =================================================================== --- coreboot-v3/arch/x86/Makefile 2008-11-12 14:11:34 UTC (rev 1001) +++ coreboot-v3/arch/x86/Makefile 2008-11-12 14:12:32 UTC (rev 1002) @@ -123,6 +123,10 @@ STAGE0_CAR_OBJ = amd/stage0.o STAGE0_ARCH_X86_SRC += amd/k8/stage1.c else +ifeq ($(CONFIG_CPU_INTEL_CORE2),y) + STAGE0_CAR_OBJ = intel/core2/stage0.o + #STAGE0_ARCH_X86_SRC += intel/core2/stage1.c +else ifeq ($(CONFIG_CPU_VIA_C7),y) STAGE0_CAR_OBJ = via/stage0.o STAGE0_ARCH_X86_SRC += via/stage1.c @@ -130,6 +134,7 @@ endif endif endif +endif ifeq ($(CONFIG_PAYLOAD_NO_PREPARSE_ELF), y) PARSEELF = Added: coreboot-v3/arch/x86/intel/core2/stage0.S =================================================================== --- coreboot-v3/arch/x86/intel/core2/stage0.S (rev 0) +++ coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-12 14:12:32 UTC (rev 1002) @@ -0,0 +1,190 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE +#define post_code(x) intel_chip_post_macro(x) + +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> + +#include <macros.h> + +#define ROM_CODE_SEG 0x08 +#define ROM_DATA_SEG 0x10 + +#define CACHE_RAM_CODE_SEG 0x18 +#define CACHE_RAM_DATA_SEG 0x20 + + /* When we come here we are in protected mode. We expand the stack + * and copy the data segment from ROM to the memory. + * + * After that, we call the chipset bootstrap routine that + * does what is left of the chipset initialization. + * + * NOTE: Aligned to 4 so that we are sure that the prefetch + * cache will be reloaded. + */ + + .align 4 + .globl protected_stage0 +protected_stage0: + /* This code was used by v2. TODO. */ + lgdt %cs:gdtptr + ljmp $ROM_CODE_SEG, $__protected_stage0 + +.globl __protected_stage0 +__protected_stage0: + /* Save the BIST result. */ + movl %eax, %ebp + + port80_post(0x01) + + movw $ROM_DATA_SEG, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs + +cache_as_ram: +#if USE_FALLBACK_IMAGE == 1 + + post_code(0x20) + + /* Send INIT IPI to all excluding ourself */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + /* Zero out all Fixed Range and Variable Range MTRRs */ + movl $mtrr_table, %esi + movl $( (mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + /* Configure the default memory type to uncacheable */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + /* Set cache as ram base address */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + /* Set cache as ram mask */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax + movl $0x0000000f, %edx + wrmsr + + /* Enable MTRR */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $(1 << 11), %eax + wrmsr + + /* Enable L2 Cache */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr + + /* CR0.CD = 0, CR0.NW = 0 */ + movl %cr0, %eax + andl $( ~( (1 << 30) | (1 << 29) ) ), %eax + invd + movl %eax, %cr0 + + /* Clear the cache memory reagion */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + //movl $0x23322332, %eax + xorl %eax, %eax + rep stosl +#endif + + /* Enable Cache As RAM mode by disabling cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + +#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0000000f, %edx + movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + wrmsr +#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ + + /* enable cache */ + movl %cr0, %eax + andl $( ~( (1 << 30) | (1 << 29) ) ), %eax + movl %eax, %cr0 + + /* Set up stack pointer */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl %eax, %esp + + /* Restore the BIST result */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + call stage1_phase1 + + post_code(0x2f) +error: + hlt + jmp error + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F +mtrr_table_end: + + +#include "../../stage0_common.S"

1 0

r1001 - coreboot-v3/mainboard/kontron
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: stepan Date: 2008-11-12 15:11:34 +0100 (Wed, 12 Nov 2008) New Revision: 1001 Added: coreboot-v3/mainboard/kontron/986lcd-m/ Removed: coreboot-v3/mainboard/kontron/9861lcd-m/ Log: Rename mainboard directory to its supposed name. (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de>

1 0

Libpayload out files
by Gregg C Levine 12 Nov '08

12 Nov '08

Hello! I've successfully built the libpayload that's current as of 45 minutes ago, (I ran svn update on it at 11:30PM ET). It built properly without any problems, and even allowed me to create it as a multi-boot library. Now the questions, earlier we had a discussion regarding the ability to boot it from a Grub2 prompt, and even from a Grub-Legacy prompt after it booted Grub2. Typically they boot elf images. Here: Any suggestions for creating an image that way? -- Gregg C Levine hansolofalcon(a)worldnet.att.net "The Force will be with you always." Obi-Wan Kenobi

2 1

r1000 - in coreboot-v3: include/device mainboard/kontron/9861lcd-m southbridge/intel/i82801gx
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: rminnich Date: 2008-11-12 05:10:45 +0100 (Wed, 12 Nov 2008) New Revision: 1000 Modified: coreboot-v3/include/device/pci_ids.h coreboot-v3/include/device/pnp.h coreboot-v3/mainboard/kontron/9861lcd-m/stage1.c coreboot-v3/mainboard/kontron/9861lcd-m/stage1_debug.c coreboot-v3/southbridge/intel/i82801gx/Makefile coreboot-v3/southbridge/intel/i82801gx/i82801gx.h coreboot-v3/southbridge/intel/i82801gx/i82801gx_smbus.h coreboot-v3/southbridge/intel/i82801gx/ide.c coreboot-v3/southbridge/intel/i82801gx/stage1_smbus.c coreboot-v3/southbridge/intel/i82801gx/usb_ehci.c coreboot-v3/southbridge/intel/i82801gx/watchdog.c Log: Stage 1 mostly works. Stage 2 needs lots of twiddling. cpu setup is nonexistent. No car either. Work remains ... Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/include/device/pci_ids.h =================================================================== --- coreboot-v3/include/device/pci_ids.h 2008-11-12 02:04:08 UTC (rev 999) +++ coreboot-v3/include/device/pci_ids.h 2008-11-12 04:10:45 UTC (rev 1000) @@ -235,6 +235,8 @@ #define PCI_VENDOR_ID_CIRRUS 0x1013 #define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 /* Used by QEMU */ +#define PCI_VENDOR_ID_INTEL 0x8086 + #define PCI_VENDOR_ID_NVIDIA 0x10de #define PCI_DEVICE_ID_NVIDIA_MCP55_LPC 0x0360 #define PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE 0x0361 Modified: coreboot-v3/include/device/pnp.h =================================================================== --- coreboot-v3/include/device/pnp.h 2008-11-12 02:04:08 UTC (rev 999) +++ coreboot-v3/include/device/pnp.h 2008-11-12 04:10:45 UTC (rev 1000) @@ -31,7 +31,7 @@ void rawpnp_set_logical_device(u16 port, u8 ldn); void rawpnp_set_enable(u16 port, int enable); void rawpnp_set_iobase(u16 port, u8 index, u16 iobase); -void rawpnp_set_irq(u16 port, unsigned index, unsigned irq); + /* Primitive pnp resource manipulation */ void pnp_write_config(struct device * dev, u8 reg, u8 value); u8 pnp_read_config(struct device * dev, u8 reg); Modified: coreboot-v3/mainboard/kontron/9861lcd-m/stage1.c =================================================================== --- coreboot-v3/mainboard/kontron/9861lcd-m/stage1.c 2008-11-12 02:04:08 UTC (rev 999) +++ coreboot-v3/mainboard/kontron/9861lcd-m/stage1.c 2008-11-12 04:10:45 UTC (rev 1000) @@ -123,14 +123,14 @@ rawpnp_set_logical_device(port, ldn); rawpnp_set_enable(port, 0); rawpnp_set_iobase(port, PNP_IDX_IO0, 0x3f8); - rawpnp_set_irq(port, PNP_IDX_IRQ0, 4); + rawpnp_write_config(port, PNP_IDX_IRQ0, 4); rawpnp_set_enable(port, 1); ldn = W83627THG_SP2; rawpnp_set_logical_device(port, ldn); rawpnp_set_enable(port, 0); rawpnp_set_iobase(port, PNP_IDX_IO0, 0x2f8); - rawpnp_set_irq(port, PNP_IDX_IRQ0, 3); + rawpnp_write_config(port, PNP_IDX_IRQ0, 3); // rawpnp_write_config(dev, 0xf1, 4); // IRMODE0 rawpnp_set_enable(port, 1); @@ -176,14 +176,14 @@ rawpnp_set_logical_device(port, ldn); // Set COM3 to sane non-conflicting values rawpnp_set_enable(port, 0); rawpnp_set_iobase(port, PNP_IDX_IO0, 0x3e8); - rawpnp_set_irq(port, PNP_IDX_IRQ0, 11); + rawpnp_write_config(port, PNP_IDX_IRQ0, 11); rawpnp_set_enable(port, 1); ldn = W83627THG_SP2; rawpnp_set_logical_device(port, ldn); // Set COM4 to sane non-conflicting values rawpnp_set_enable(port, 0); rawpnp_set_iobase(port, PNP_IDX_IO0, 0x2e8); - rawpnp_set_irq(port, PNP_IDX_IRQ0, 10); + rawpnp_write_config(port, PNP_IDX_IRQ0, 10); rawpnp_set_enable(port, 1); ldn = W83627THG_FDC; Modified: coreboot-v3/mainboard/kontron/9861lcd-m/stage1_debug.c =================================================================== --- coreboot-v3/mainboard/kontron/9861lcd-m/stage1_debug.c 2008-11-12 02:04:08 UTC (rev 999) +++ coreboot-v3/mainboard/kontron/9861lcd-m/stage1_debug.c 2008-11-12 04:10:45 UTC (rev 1000) @@ -89,6 +89,7 @@ void dump_spd_registers(u16 start, u16 end, int inc) { + int smbus_read_byte(u16 device, u16 address); u16 device; device = start; while(device <= end) { Modified: coreboot-v3/southbridge/intel/i82801gx/Makefile =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/Makefile 2008-11-12 02:04:08 UTC (rev 999) +++ coreboot-v3/southbridge/intel/i82801gx/Makefile 2008-11-12 04:10:45 UTC (rev 1000) @@ -32,11 +32,13 @@ $(src)/southbridge/intel/i82801gx/pcie.c \ $(src)/southbridge/intel/i82801gx/sata.c \ $(src)/southbridge/intel/i82801gx/smbus.c \ + $(src)/southbridge/intel/i82801gx/libsmbus.c \ $(src)/southbridge/intel/i82801gx/usb_ehci.c \ $(src)/southbridge/intel/i82801gx/usb.c \ $(src)/southbridge/intel/i82801gx/watchdog.c STAGE0_CHIPSET_SRC += \ - $(src)/southbridge/intel/i82801gx/stage1_smbus.c + $(src)/southbridge/intel/i82801gx/stage1_smbus.c \ + $(src)/southbridge/intel/i82801gx/libsmbus.c \ endif Modified: coreboot-v3/southbridge/intel/i82801gx/i82801gx.h =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/i82801gx.h 2008-11-12 02:04:08 UTC (rev 999) +++ coreboot-v3/southbridge/intel/i82801gx/i82801gx.h 2008-11-12 04:10:45 UTC (rev 1000) @@ -21,9 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H #define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H -#include "chip.h" -extern void i82801gx_enable(device_t dev); - +/* warning: included in stage1 and stage2 */ #define PCI_DMA_CFG 0x90 #define SERIRQ_CNTL 0x64 #define GEN_CNTL 0xd0 Modified: coreboot-v3/southbridge/intel/i82801gx/i82801gx_smbus.h =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/i82801gx_smbus.h 2008-11-12 02:04:08 UTC (rev 999) +++ coreboot-v3/southbridge/intel/i82801gx/i82801gx_smbus.h 2008-11-12 04:10:45 UTC (rev 1000) @@ -18,170 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <device/smbus_def.h> - -static void smbus_delay(void) -{ - inb(0x80); -} - -static int smbus_wait_until_ready(void) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } while (byte & 1); - return loops ? 0 : -1; -} - -static int smbus_wait_until_done(void) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); - return loops ? 0 : -1; -} - -static int smbus_wait_until_blk_done(void) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } while ((byte & (1 << 7)) == 0); - return loops ? 0 : -1; -} - -static int do_smbus_read_byte(unsigned device, unsigned address) -{ - unsigned char global_status_register; - unsigned char byte; - - if (smbus_wait_until_ready() < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - /* Setup transaction */ - /* Disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - /* Set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); - /* Set the command/address... */ - outb(address & 0xff, SMBUS_IO_BASE + SMBHSTCMD); - /* Set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (SMBUS_IO_BASE + SMBHSTCTL)); - /* Clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* Clear the data byte... */ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - - /* Start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), - SMBUS_IO_BASE + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_until_done() < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); - - /* Ignore the "In Use" status... */ - global_status_register &= ~(3 << 5); - - /* Read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); - if (global_status_register != (1 << 1)) { - return SMBUS_ERROR; - } - return byte; -} - -/* This function is neither used nor tested by me (Corey Osgood), the author -(Yinghai) probably tested/used it on i82801er */ -static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, - unsigned data1, unsigned data2) -{ - unsigned char byte; - unsigned char stat; - int i; - -#if CONFIG_USE_PRINTK_IN_CAR - printk_err("Untested smbus_write_block called\r\n"); -#else - print_err("Untested smbus_write_block called\r\n"); -#endif - - /* Clear the PM timeout flags, SECOND_TO_STS */ - outw(inw(0x0400 + 0x66), 0x0400 + 0x66); - - if (smbus_wait_until_ready() < 0) { - return -2; - } - - /* Setup transaction */ - /* Obtain ownership */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - for (stat = 0; (stat & 0x40) == 0;) { - stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } - /* Clear the done bit */ - outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); - /* Disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - - /* Set the device I'm talking too */ - outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); - - /* Set the command address */ - outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD); - - /* Set the block length */ - outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0); - - /* Try sending out the first byte of data here */ - byte = (data1 >> (0)) & 0x0ff; - outb(byte, SMBUS_IO_BASE + SMBBLKDAT); - /* Issue a block write command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40, - SMBUS_IO_BASE + SMBHSTCTL); - - for (i = 0; i < length; i++) { - - /* Poll for transaction completion */ - if (smbus_wait_until_blk_done() < 0) { - return -3; - } - - /* Load the next byte */ - if (i > 3) - byte = (data2 >> (i % 4)) & 0x0ff; - else - byte = (data1 >> (i)) & 0x0ff; - outb(byte, SMBUS_IO_BASE + SMBBLKDAT); - - /* Clear the done bit */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), - SMBUS_IO_BASE + SMBHSTSTAT); - } - -#if CONFIG_USE_PRINTK_IN_CAR - printk_debug("SMBUS Block complete\r\n"); -#else - print_debug("SMBUS Block complete\r\n"); -#endif - return 0; -} +void smbus_delay(void); +int smbus_wait_until_ready(void); +int smbus_wait_until_done(void); +int smbus_wait_until_blk_done(void); +int do_smbus_read_byte(unsigned device, unsigned address); Modified: coreboot-v3/southbridge/intel/i82801gx/ide.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/ide.c 2008-11-12 02:04:08 UTC (rev 999) +++ coreboot-v3/southbridge/intel/i82801gx/ide.c 2008-11-12 04:10:45 UTC (rev 1000) @@ -29,7 +29,7 @@ #include <config.h> #include "i82801gx.h" -typedef struct southbridge_intel_i82801gx_config config_t; +typedef struct southbridge_intel_i82801gx_ide_dts_config config_t; static void ide_init(struct device *dev) { @@ -58,7 +58,7 @@ ideTimingConfig |= (3 << 8); // RCT = 1 clock ideTimingConfig |= (1 << 1); // IE0 ideTimingConfig |= (1 << 0); // TIME0 - printk_debug("IDE0 "); + printk(BIOS_DEBUG, "IDE0 "); } pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); @@ -72,7 +72,7 @@ ideTimingConfig |= (3 << 8); // RCT = 1 clock ideTimingConfig |= (1 << 1); // IE0 ideTimingConfig |= (1 << 0); // TIME0 - printk_debug("IDE1 "); + printk(BIOS_DEBUG, "IDE1 "); } pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); @@ -87,7 +87,7 @@ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config32(dev, INTR_LN, 0xff); /* Int 15 */ } - +void i82801gx_enable(struct device * dev); struct device_operations i82801gx_ide = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_INTEL, Modified: coreboot-v3/southbridge/intel/i82801gx/stage1_smbus.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/stage1_smbus.c 2008-11-12 02:04:08 UTC (rev 999) +++ coreboot-v3/southbridge/intel/i82801gx/stage1_smbus.c 2008-11-12 04:10:45 UTC (rev 1000) @@ -29,7 +29,6 @@ #include <config.h> #include <io.h> #include "i82801gx.h" -#include "i82801gx_smbus.h" static void enable_smbus(void) { @@ -58,11 +57,13 @@ /* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled.\r\n"); + printk(BIOS_DEBUG, "SMBus controller enabled.\r\n"); } +/* some prototypes are hand-declared since the include files are still a little too stage-2 oriented */ int smbus_read_byte(u16 device, u16 address) { + int do_smbus_read_byte(unsigned device, unsigned address); return do_smbus_read_byte(device, address); } Modified: coreboot-v3/southbridge/intel/i82801gx/usb_ehci.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/usb_ehci.c 2008-11-12 02:04:08 UTC (rev 999) +++ coreboot-v3/southbridge/intel/i82801gx/usb_ehci.c 2008-11-12 04:10:45 UTC (rev 1000) @@ -72,6 +72,7 @@ }; /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */ +void i82801gx_enable(struct device * dev); struct device_operations i82801gx_usb_ehci = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_INTEL, Modified: coreboot-v3/southbridge/intel/i82801gx/watchdog.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/watchdog.c 2008-11-12 02:04:08 UTC (rev 999) +++ coreboot-v3/southbridge/intel/i82801gx/watchdog.c 2008-11-12 04:10:45 UTC (rev 1000) @@ -23,6 +23,7 @@ #include <console.h> #include <device/pci.h> #include <msr.h> +#include <io.h> #include <legacy.h> #include <device/pci_ids.h> #include <statictree.h>

1 0

unrv2b delay (v2)
by Arne Georg Gleditsch 12 Nov '08

12 Nov '08

Hi, The unrv2b uncompression algorithm appears to behave very badly in the absence of a proper cache. Instrumentation indicates somehting like ~180 i-stream cacheline requests for _every_ d-stream cacheline request during decompression. The following patch copies the unrv2b function to DRAM before performing the actual decompression, reducing the run-time from 12.5s to 50ms in my environment. The patch is somewhat rough, and assumes that (1) the unrv2b function is less than 1k in size, and (2) that placing a copy of the function just after the decompress destination is unproblematic. It works well for me, though. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> -- Arne.

7 11

r999 - coreboot-v3/mainboard/kontron/9861lcd-m
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: rminnich Date: 2008-11-12 03:04:08 +0100 (Wed, 12 Nov 2008) New Revision: 999 Modified: coreboot-v3/mainboard/kontron/9861lcd-m/Makefile coreboot-v3/mainboard/kontron/9861lcd-m/stage1_debug.c Log: stage1_debug.c now compiles. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/kontron/9861lcd-m/Makefile =================================================================== --- coreboot-v3/mainboard/kontron/9861lcd-m/Makefile 2008-11-12 01:39:00 UTC (rev 998) +++ coreboot-v3/mainboard/kontron/9861lcd-m/Makefile 2008-11-12 02:04:08 UTC (rev 999) @@ -22,7 +22,7 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \ $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ - $(src)/arch/x86/stage1_debug.c \ + $(src)/mainboard/$(MAINBOARDDIR)/stage1_debug.c \ INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ Modified: coreboot-v3/mainboard/kontron/9861lcd-m/stage1_debug.c =================================================================== --- coreboot-v3/mainboard/kontron/9861lcd-m/stage1_debug.c 2008-11-12 01:39:00 UTC (rev 998) +++ coreboot-v3/mainboard/kontron/9861lcd-m/stage1_debug.c 2008-11-12 02:04:08 UTC (rev 999) @@ -18,57 +18,66 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, * MA 02110-1301 USA */ +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> #define SMBUS_MEM_DEVICE_START 0x50 #define SMBUS_MEM_DEVICE_END 0x53 #define SMBUS_MEM_DEVICE_INC 1 -static void print_pci_devices(void) + void print_pci_devices(void) { - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); + u32 dev; + for(dev = PCI_BDF(0, 0, 0); + dev <= PCI_BDF(0, 0x1f, 0x7); + dev += PCI_BDF(0,0,1)) { + u32 id; + id = pci_conf1_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0x0000)) { continue; } - printk_debug("PCI: %02x:%02x.%02x", (dev >> 20) & 0xff, + printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7); - printk_debug(" [%04x:%04x]\r\n", id &0xffff, id >> 16); + printk(BIOS_DEBUG, " [%04x:%04x]\n", id &0xffff, id >> 16); } } -static void dump_pci_device(unsigned dev) + void dump_pci_device(u32 dev) { int i; - printk_debug("PCI: %02x:%02x.%02x\r\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7); + printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7); for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { - printk_debug("%02x:", i); + printk(BIOS_DEBUG, "%02x:", i); } - val = pci_read_config8(dev, i); - printk_debug(" %02x", val); + val = pci_conf1_read_config8(dev, i); + printk(BIOS_DEBUG, " %02x", val); if ((i & 0x0f) == 0x0f) { - printk_debug("\r\n"); + printk(BIOS_DEBUG, "\n"); } } } -static void dump_pci_devices(void) + void dump_pci_devices(void) { - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); + u32 dev; + for(dev = PCI_BDF(0, 0, 0); + dev <= PCI_BDF(0, 0x1f, 0x7); + dev += PCI_BDF(0,0,1)) { + u32 id; + id = pci_conf1_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0x0000)) { @@ -78,40 +87,40 @@ } } -void dump_spd_registers(void) +void dump_spd_registers(u16 start, u16 end, int inc) { - unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + u16 device; + device = start; + while(device <= end) { int status = 0; int i; - printk_debug("\r\ndimm %02x", device); + printk(BIOS_DEBUG, "\ndimm %02x", device); for(i = 0; (i < 256) ; i++) { if ((i % 16) == 0) { - printk_debug("\r\n%02x: ", i); + printk(BIOS_DEBUG, "\n%02x: ", i); } status = smbus_read_byte(device, i); if (status < 0) { - printk_debug("bad device: %02x\r\n", -status); + printk(BIOS_DEBUG, "bad device: %02x\n", -status); break; } - printk_debug("%02x ", status); + printk(BIOS_DEBUG, "%02x ", status); } - device += SMBUS_MEM_DEVICE_INC; - printk_debug("\r\n"); + device += inc; + printk(BIOS_DEBUG, "\n"); } } -static void dump_mem(unsigned start, unsigned end) + void dump_mem(unsigned start, unsigned end) { unsigned i; - print_debug("dump_mem:"); + printk(BIOS_DEBUG, "dump_mem:"); for(i=start;i<end;i++) { if((i & 0xf)==0) { - printk_debug("\r\n%08x:", i); + printk(BIOS_DEBUG, "\n%08x:", i); } - printk_debug(" %02x", (unsigned char)*((unsigned char *)i)); + printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); } - print_debug("\r\n"); + printk(BIOS_DEBUG, "\n"); }

1 0

r998 - in coreboot-v3: . include/device mainboard/kontron/9861lcd-m
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: rminnich Date: 2008-11-12 02:39:00 +0100 (Wed, 12 Nov 2008) New Revision: 998 Modified: coreboot-v3/Kconfig coreboot-v3/include/device/pnp.h coreboot-v3/mainboard/kontron/9861lcd-m/stage1.c Log: Yes, starting to build. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/Kconfig =================================================================== --- coreboot-v3/Kconfig 2008-11-12 01:16:22 UTC (rev 997) +++ coreboot-v3/Kconfig 2008-11-12 01:39:00 UTC (rev 998) @@ -120,6 +120,8 @@ # Super I/Os: config SUPERIO_WINBOND_W83627HF boolean +config SUPERIO_WINBOND_W83627THG + boolean config SUPERIO_FINTEK_F71805F boolean config SUPERIO_ITE_IT8716F Modified: coreboot-v3/include/device/pnp.h =================================================================== --- coreboot-v3/include/device/pnp.h 2008-11-12 01:16:22 UTC (rev 997) +++ coreboot-v3/include/device/pnp.h 2008-11-12 01:39:00 UTC (rev 998) @@ -31,7 +31,7 @@ void rawpnp_set_logical_device(u16 port, u8 ldn); void rawpnp_set_enable(u16 port, int enable); void rawpnp_set_iobase(u16 port, u8 index, u16 iobase); - +void rawpnp_set_irq(u16 port, unsigned index, unsigned irq); /* Primitive pnp resource manipulation */ void pnp_write_config(struct device * dev, u8 reg, u8 value); u8 pnp_read_config(struct device * dev, u8 reg); Modified: coreboot-v3/mainboard/kontron/9861lcd-m/stage1.c =================================================================== --- coreboot-v3/mainboard/kontron/9861lcd-m/stage1.c 2008-11-12 01:16:22 UTC (rev 997) +++ coreboot-v3/mainboard/kontron/9861lcd-m/stage1.c 2008-11-12 01:39:00 UTC (rev 998) @@ -24,12 +24,15 @@ #include <lib.h> #include <console.h> #include <device/device.h> +#include <device/pnp.h> #include <cpu.h> #include <device/pci.h> #include <string.h> #include <msr.h> #include <io.h> +#include <uart8250.h> #include <arch/x86/msr.h> +#include <arch/x86/lapic.h> #include "superio/winbond/w83627thg/w83627thg.h" @@ -111,91 +114,93 @@ */ static void early_superio_config_w83627thg(void) { - u32 dev; + u16 port; + u8 ldn; - dev=PNP_DEV(0x2e, W83627THG_SP1); - pnp_enter_ext_func_mode(dev); + port = 0x2e; + ldn = W83627THG_SP1; + rawpnp_enter_ext_func_mode(port); + rawpnp_set_logical_device(port, ldn); + rawpnp_set_enable(port, 0); + rawpnp_set_iobase(port, PNP_IDX_IO0, 0x3f8); + rawpnp_set_irq(port, PNP_IDX_IRQ0, 4); + rawpnp_set_enable(port, 1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 4); - pnp_set_enable(dev, 1); + ldn = W83627THG_SP2; + rawpnp_set_logical_device(port, ldn); + rawpnp_set_enable(port, 0); + rawpnp_set_iobase(port, PNP_IDX_IO0, 0x2f8); + rawpnp_set_irq(port, PNP_IDX_IRQ0, 3); + // rawpnp_write_config(dev, 0xf1, 4); // IRMODE0 + rawpnp_set_enable(port, 1); - dev=PNP_DEV(0x2e, W83627THG_SP2); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 3); - // pnp_write_config(dev, 0xf1, 4); // IRMODE0 - pnp_set_enable(dev, 1); + ldn = W83627THG_KBC; + rawpnp_set_logical_device(port, ldn); + rawpnp_set_enable(port, 0); + rawpnp_set_iobase(port, PNP_IDX_IO0, 0x60); + rawpnp_set_iobase(port, PNP_IDX_IO1, 0x64); + // rawpnp_write_config(port, 0xf0, 0x82); + rawpnp_set_enable(port, 1); - dev=PNP_DEV(0x2e, W83627THG_KBC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); - pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - // pnp_write_config(dev, 0xf0, 0x82); - pnp_set_enable(dev, 1); + ldn = W83627THG_GAME_MIDI_GPIO1; + rawpnp_set_logical_device(port, ldn); + rawpnp_set_enable(port, 0); + rawpnp_write_config(port, 0xf5, 0xff); // invert all GPIOs + rawpnp_set_enable(port, 1); - dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs - pnp_set_enable(dev, 1); + ldn = W83627THG_GPIO2; + rawpnp_set_logical_device(port, ldn); + rawpnp_set_enable(port, 1); // Just enable it - dev=PNP_DEV(0x2e, W83627THG_GPIO2); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); // Just enable it + ldn = W83627THG_GPIO3; + rawpnp_set_logical_device(port, ldn); + rawpnp_set_enable(port, 0); + rawpnp_write_config(port, 0xf0, 0xfb); // GPIO bit 2 is output + rawpnp_write_config(port, 0xf1, 0x00); // GPIO bit 2 is 0 + rawpnp_write_config(port, 0x30, 0x03); // Enable GPIO3+4. rawpnp_set_enable is not sufficient - dev=PNP_DEV(0x2e, W83627THG_GPIO3); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output - pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 - pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient + ldn = W83627THG_FDC; + rawpnp_set_logical_device(port, ldn); + rawpnp_set_enable(port, 0); - dev=PNP_DEV(0x2e, W83627THG_FDC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); + ldn = W83627THG_PP; + rawpnp_set_logical_device(port, ldn); + rawpnp_set_enable(port, 0); - dev=PNP_DEV(0x2e, W83627THG_PP); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); + rawpnp_exit_ext_func_mode(port); - pnp_exit_ext_func_mode(dev); + port = 0x2e; + ldn = W83627THG_SP1; + rawpnp_enter_ext_func_mode(port); - dev=PNP_DEV(0x4e, W83627THG_SP1); - pnp_enter_ext_func_mode(dev); + rawpnp_set_logical_device(port, ldn); // Set COM3 to sane non-conflicting values + rawpnp_set_enable(port, 0); + rawpnp_set_iobase(port, PNP_IDX_IO0, 0x3e8); + rawpnp_set_irq(port, PNP_IDX_IRQ0, 11); + rawpnp_set_enable(port, 1); - pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 11); - pnp_set_enable(dev, 1); + ldn = W83627THG_SP2; + rawpnp_set_logical_device(port, ldn); // Set COM4 to sane non-conflicting values + rawpnp_set_enable(port, 0); + rawpnp_set_iobase(port, PNP_IDX_IO0, 0x2e8); + rawpnp_set_irq(port, PNP_IDX_IRQ0, 10); + rawpnp_set_enable(port, 1); - dev=PNP_DEV(0x4e, W83627THG_SP2); - pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 10); - pnp_set_enable(dev, 1); + ldn = W83627THG_FDC; + rawpnp_set_logical_device(port, ldn); + rawpnp_set_enable(port, 0); - dev=PNP_DEV(0x4e, W83627THG_FDC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); + ldn = W83627THG_PP; + rawpnp_set_logical_device(port, ldn); + rawpnp_set_enable(port, 0); - dev=PNP_DEV(0x4e, W83627THG_PP); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); + ldn = W83627THG_KBC; + rawpnp_set_logical_device(port, ldn); + rawpnp_set_enable(port, 0); + rawpnp_set_iobase(port, PNP_IDX_IO0, 0x00); + rawpnp_set_iobase(port, PNP_IDX_IO1, 0x00); - dev=PNP_DEV(0x4e, W83627THG_KBC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); - pnp_set_iobase(dev, PNP_IDX_IO1, 0x00); - - pnp_exit_ext_func_mode(dev); + rawpnp_exit_ext_func_mode(port); } static void rcba_config(void) @@ -231,8 +236,8 @@ static void early_ich7_init(void) { - uint8_t reg8; - uint32_t reg32; + u8 reg8; + u32 reg32; // program secondary mlt XXX byte? pci_conf1_write_config8(PCI_BDF(0, 0x1e, 0), 0x1b, 0x20); @@ -285,24 +290,22 @@ #warning need to fix up hardware_stage1 and move parts to initram.c void hardware_stage1(void) { + void early_superio_config_w83627thg(void); + void ich7_enable_lpc(void); int boot_mode = 0; - if (bist == 0) { - enable_lapic(); - } + enable_lapic(); ich7_enable_lpc(); early_superio_config_w83627thg(); /* Set up the console */ - uart_init(); +#warning need to know how to call uart8250_init +// uart8250_init(); console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); +} - -} void mainboard_pre_payload(void) { banner(BIOS_DEBUG, "mainboard_pre_payload: done");

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coreboot November 2008