coreboot November 2008

coreboot@coreboot.org

76 participants
490 discussions

r3750 build service
by coreboot information 12 Nov '08

12 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3750 to the coreboot source repository and caused the following changes: Change Log: Add detection support for ITE IT8228E, IT8711F, IT8722F, IT8761E, IT8780F, and Fintek F71863FG. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of supermicro:x6dhr_ig has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3750&device=x6dhr_ig&vendo… Compilation of via:epia-m has been fixed If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[PATCH] superiotool: Detect more Fintek/ITE chips
by Uwe Hermann 12 Nov '08

12 Nov '08

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

r3750 - trunk/util/superiotool
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: uwe Date: 2008-11-12 20:08:58 +0100 (Wed, 12 Nov 2008) New Revision: 3750 Modified: trunk/util/superiotool/fintek.c trunk/util/superiotool/ite.c Log: Add detection support for ITE IT8228E, IT8711F, IT8722F, IT8761E, IT8780F, and Fintek F71863FG. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/superiotool/fintek.c =================================================================== --- trunk/util/superiotool/fintek.c 2008-11-11 23:41:08 UTC (rev 3749) +++ trunk/util/superiotool/fintek.c 2008-11-12 19:08:58 UTC (rev 3750) @@ -2,7 +2,7 @@ * This file is part of the superiotool project. * * Copyright (C) 2006 coresystems GmbH <info(a)coresystems.de> - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2007-2008 Uwe Hermann <uwe(a)hermann-uwe.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -30,7 +30,7 @@ #define FINTEK_VENDOR_ID 0x3419 static const struct superio_registers reg_table[] = { - {0x0106, "F71862FG", { + {0x0106, "F71862FG / F71863FG", { /* Same ID? Datasheet typo? */ {EOT}}}, {0x4103, "F71872F/FG / F71806F/FG", { /* Same ID? Datasheet typo? */ {EOT}}}, Modified: trunk/util/superiotool/ite.c =================================================================== --- trunk/util/superiotool/ite.c 2008-11-11 23:41:08 UTC (rev 3749) +++ trunk/util/superiotool/ite.c 2008-11-12 19:08:58 UTC (rev 3750) @@ -2,7 +2,7 @@ * This file is part of the superiotool project. * * Copyright (C) 2007 Carl-Daniel Hailfinger - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2007-2008 Uwe Hermann <uwe(a)hermann-uwe.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,6 +27,8 @@ #define ISA_PNP_ADDR 0x279 static const struct superio_registers reg_table[] = { + {0x8228, "IT8228E", { + {EOT}}}, {0x8661, "IT8661F/IT8770F", { {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x20,0x21,0x22, @@ -174,6 +176,8 @@ {EOT}}}, {0x8710, "IT8710F", { /* TODO: Not yet in sensors-detect */ {EOT}}}, + {0x8711, "IT8711F", { /* 0x8711 is a guess, not found in datasheet. */ + {EOT}}}, {0x8712, "IT8712F", { {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, @@ -325,6 +329,8 @@ {EOT}}}, {0x8720, "IT8720F", { /* From sensors-detect */ {EOT}}}, + {0x8722, "IT8722F", { + {EOT}}}, {0x8726, "IT8726F", { /* Datasheet wrongly says that the ID is 0x8716. */ {NOLDN, NULL, @@ -378,6 +384,10 @@ {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x00,EOT}}, {EOT}}}, + {0x8761, "IT8761E", { + {EOT}}}, + {0x8780, "IT8780F", { + {EOT}}}, {EOT} }; @@ -475,11 +485,6 @@ OUTB(initkey_mbpnp[i], port); } -/** - * IT871[01]F and IT8708F use 0x87, 0x87 - * IT8761F uses 0x87, 0x61, 0x55, 0x55/0xaa - * IT86xxF series uses different ports - */ static void enter_conf_mode_ite(uint16_t port) { OUTB(0x87, port); @@ -488,6 +493,22 @@ OUTB((port == 0x2e) ? 0x55 : 0xaa, port); } +static void enter_conf_mode_ite_it8761e(uint16_t port) +{ + OUTB(0x87, port); + OUTB(0x61, port); + OUTB(0x55, port); + OUTB((port == 0x2e) ? 0x55 : 0xaa, port); +} + +static void enter_conf_mode_ite_it8228e(uint16_t port) +{ + OUTB(0x82, port); + OUTB(0x28, port); + OUTB(0x55, port); + OUTB((port == 0x2e) ? 0x55 : 0xaa, port); +} + static void exit_conf_mode_ite(uint16_t port) { regwrite(port, 0x02, 0x02); @@ -542,9 +563,17 @@ exit_conf_mode_ite(port); } else { enter_conf_mode_ite(port); - probe_idregs_ite_helper("(init=0x87,0x01,0x55,0x55/0xaa) ", port); + probe_idregs_ite_helper("(init=standard) ", port); exit_conf_mode_ite(port); + enter_conf_mode_ite_it8761e(port); + probe_idregs_ite_helper("(init=it8761e) ", port); + exit_conf_mode_ite(port); + + enter_conf_mode_ite_it8228e(port); + probe_idregs_ite_helper("(init=it8228e) ", port); + exit_conf_mode_ite(port); + enter_conf_mode_winbond_fintek_ite_8787(port); probe_idregs_ite_helper("(init=0x87,0x87) ", port); exit_conf_mode_winbond_fintek_ite_8787(port);

1 0

[PATCH] artecgroup/dbe61: Set up NAND and USB power handling settings
by Mart Raudsepp 12 Nov '08

12 Nov '08

artecgroup/dbe61: Set up NAND and USB power handling settings Also upper-cases the hex in lpc_serirq_polarity as all other Geode boards have it as such, and remove parts of the commented out reference v2 setup block that should be handled by this change now. Oddly enough the USB power handling setting (that was to get the other pair of USB ports powered during DBE62 work) actually make memtest work, while without it it gets unexpected interrupt halts. The SPD commit earlier missed this local change as an unrelated one. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- mainboard/artecgroup/dbe61/dts | 15 +++++---------- 1 files changed, 5 insertions(+), 10 deletions(-) diff --git a/mainboard/artecgroup/dbe61/dts b/mainboard/artecgroup/dbe61/dts index 69a6217..291764a 100644 --- a/mainboard/artecgroup/dbe61/dts +++ b/mainboard/artecgroup/dbe61/dts @@ -22,14 +22,8 @@ /* chip southbridge/amd/cs5536_lx - register "enable_ide_nand_flash" = "0" - - register "isa_irq" = "0" #register "flash_irq" = "14" - ## IDE IRQ - register "enable_ide_irq" = "0" - register "audio_irq" = "5" register "usb_irq" = "7" @@ -55,9 +49,6 @@ # Configure KEL Emulation IRQ, 0 to disable register "kel_emul_irq" = "0" - device pci f.0 on end # ISA Bridge - device pci f.1 on end # Flash controller - device pci f.2 off end # IDE controller device pci f.3 on end # Audio device pci f.4 on end # OHCI device pci f.5 on end # EHCI @@ -95,12 +86,14 @@ end * Each bit is an IRQ 0-15. */ lpc_serirq_enable = "0x00001002"; /* LPC IRQ polarity. Each bit is an IRQ 0-15. */ - lpc_serirq_polarity = "0x0000effd"; + lpc_serirq_polarity = "0x0000EFFD"; /* 0:continuous 1:quiet */ lpc_serirq_mode = "1"; /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. * See virtual PIC spec. */ enable_gpio_int_route = "0x0D0C0700"; + /* 0:IDE; 1:FLASH on CS0, 2:FLASH on CS1, 3:FLASH on CS2, 4:FLASH on CS3. */ + enable_ide_nand_flash = "2"; /* COM1 settings */ com1_enable = "0"; com1_address = "0x2f8"; @@ -109,6 +102,8 @@ end com2_enable = "1"; com2_address = "0x3f8"; com2_irq = "4"; + /* USB Port Power Handling setting. */ + pph = "0xf5"; }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); -- 1.6.0.2

2 3

r1006 - coreboot-v3/mainboard/artecgroup/dbe61
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: mraudsepp Date: 2008-11-12 19:30:13 +0100 (Wed, 12 Nov 2008) New Revision: 1006 Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts Log: artecgroup/dbe61: Set up NAND and USB power handling settings Also upper-cases the hex in lpc_serirq_polarity as all other Geode boards have it as such, and remove parts of the commented out reference v2 setup block that should be handled by this change now. The USB power handling setting is meant to get the second pair of USB ports to be powered on, as this changed done by Ron to DBE62 fixed DBE62's third and fourth USB port to be usable. Oddly the USB power handling setting also makes memtest work, while without it memtest gets unexpected interrupt halts right after it loads up. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-11-12 18:26:59 UTC (rev 1005) +++ coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-11-12 18:30:13 UTC (rev 1006) @@ -22,14 +22,8 @@ /* chip southbridge/amd/cs5536_lx - register "enable_ide_nand_flash" = "0" - - register "isa_irq" = "0" #register "flash_irq" = "14" - ## IDE IRQ - register "enable_ide_irq" = "0" - register "audio_irq" = "5" register "usb_irq" = "7" @@ -55,9 +49,6 @@ # Configure KEL Emulation IRQ, 0 to disable register "kel_emul_irq" = "0" - device pci f.0 on end # ISA Bridge - device pci f.1 on end # Flash controller - device pci f.2 off end # IDE controller device pci f.3 on end # Audio device pci f.4 on end # OHCI device pci f.5 on end # EHCI @@ -95,12 +86,14 @@ * Each bit is an IRQ 0-15. */ lpc_serirq_enable = "0x00001002"; /* LPC IRQ polarity. Each bit is an IRQ 0-15. */ - lpc_serirq_polarity = "0x0000effd"; + lpc_serirq_polarity = "0x0000EFFD"; /* 0:continuous 1:quiet */ lpc_serirq_mode = "1"; /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. * See virtual PIC spec. */ enable_gpio_int_route = "0x0D0C0700"; + /* 0:IDE; 1:FLASH on CS0, 2:FLASH on CS1, 3:FLASH on CS2, 4:FLASH on CS3. */ + enable_ide_nand_flash = "2"; /* COM1 settings */ com1_enable = "0"; com1_address = "0x2f8"; @@ -109,6 +102,8 @@ com2_enable = "1"; com2_address = "0x3f8"; com2_irq = "4"; + /* USB Port Power Handling setting. */ + pph = "0xf5"; }; pci@f,2 { /config/("southbridge/amd/cs5536/ide");

1 0

r1005 - coreboot-v3/mainboard/artecgroup/dbe61
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: mraudsepp Date: 2008-11-12 19:26:59 +0100 (Wed, 12 Nov 2008) New Revision: 1005 Modified: coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.h Log: artecgroup/dbe61: Use correct interrupt router location Changes the interrupt router location to what all other Geode board ports are using, and doesn't exclusively devote any IRQs for PCI usage, as no other Geode board does so. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.h =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.h 2008-11-12 17:04:15 UTC (rev 1004) +++ coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.h 2008-11-12 18:26:59 UTC (rev 1005) @@ -46,8 +46,8 @@ PIRQ_VERSION, /* u16 version */ 32 + 16 * IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x12 << 3) | 0x0, /* Where the interrupt router lies (dev) */ - 0x0800, /* IRQs devoted exclusively to PCI usage */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ 0x1022, /* Vendor */ 0x208f, /* Device */ 0, /* Crap (miniport) */

1 0

[PATCH] artecgroup/dbe61: Use correct interrupt router location
by Mart Raudsepp 12 Nov '08

12 Nov '08

artecgroup/dbe61: Use correct interrupt router location Changes the interrupt router location to what all other Geode board ports are using, and doesn't exclusively devote any IRQs for PCI usage, as no other Geode board does so. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- mainboard/artecgroup/dbe61/irq_tables.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/mainboard/artecgroup/dbe61/irq_tables.h b/mainboard/artecgroup/dbe61/irq_tables.h index 0a70e71..4649ef0 100644 --- a/mainboard/artecgroup/dbe61/irq_tables.h +++ b/mainboard/artecgroup/dbe61/irq_tables.h @@ -46,8 +46,8 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32 + 16 * IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x12 << 3) | 0x0, /* Where the interrupt router lies (dev) */ - 0x0800, /* IRQs devoted exclusively to PCI usage */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ 0x1022, /* Vendor */ 0x208f, /* Device */ 0, /* Crap (miniport) */ -- 1.6.0.2

2 1

Re: [coreboot] r994 - in coreboot-v3: . arch/x86 mainboard southbridge/intel/i82801gx
by Mart Raudsepp 12 Nov '08

12 Nov '08

Ühel kenal päeval, K, 2008-11-12 kell 01:38, kirjutas svn(a)coreboot.org: > Author: rminnich > Date: 2008-11-12 01:38:13 +0100 (Wed, 12 Nov 2008) > New Revision: 994 > > Modified: > coreboot-v3/Kconfig > coreboot-v3/arch/x86/Kconfig > coreboot-v3/mainboard/Kconfig > coreboot-v3/southbridge/intel/i82801gx/Makefile > Log: > Filling in core 2 support. > > This actually starts to get compile errors, instead of config errors. > Modified: coreboot-v3/mainboard/Kconfig > =================================================================== > --- coreboot-v3/mainboard/Kconfig 2008-11-12 00:22:42 UTC (rev 993) > +++ coreboot-v3/mainboard/Kconfig 2008-11-12 00:38:13 UTC (rev 994) > @@ -58,6 +58,11 @@ > help > Select this option for systems from Jetway. > > +config VENDOR_KONTRON > + bool "Kontron" > + help > + Select this option for systems from Kontron. > + > config VENDOR_EMULATION > bool "Emulated systems" > help > @@ -82,6 +87,7 @@ > source "mainboard/emulation/Kconfig" > source "mainboard/gigabyte/Kconfig" > source "mainboard/jetway/Kconfig" > +source "mainboard/kontron/Kconfig" > source "mainboard/pcengines/Kconfig" > source "mainboard/via/Kconfig" This, what seems to be unrelated change, breaks make menuconfig after distclean because no mainboard/kontron/Kconfig exists in SVN. Mart Raudsepp

2 1

[PATCH] Fix a build error when using bison-2.4
by Mart Raudsepp 12 Nov '08

12 Nov '08

This fixes one of the errors from using bison-2.4, but there are more. This one in details is the following error: BISON build/util/dtc/dtc-parser.tab.c HOSTCC build/util/dtc/dtc-parser.tab.o /home/leio/dev/coreboot-v3/util/dtc/dtc-parser.y: In function ‘yyuserAction’: /home/leio/dev/coreboot-v3/util/dtc/dtc-parser.y:154: error: expected ‘;’ before ‘}’ token make: *** [/home/leio/dev/coreboot-v3/build/util/dtc/dtc-parser.tab.o] Error 1 Note that 2.4.1 might be made to still work without the semi-colon for some languages, but I understand 2.5 then still won't work without one. As it builds fine with this change with bison-2.3, it should be safe to just add the semicolon. The remaining error is the following: /home/leio/dev/coreboot-v3/util/dtc/dtc-lexer.l: In function ‘yylex’: /home/leio/dev/coreboot-v3/util/dtc/dtc-lexer.l:73: error: ‘yylval’ undeclared (first use in this function) /home/leio/dev/coreboot-v3/util/dtc/dtc-lexer.l:73: error: (Each undeclared identifier is reported only once /home/leio/dev/coreboot-v3/util/dtc/dtc-lexer.l:73: error: for each function it appears in.) dtc-parser.tab.h doesn't seem to get an "extern YYSTYPE yylval" declaration, which per documentation should only happen for pure parser cases ("%define api.pure"), but I can't find any such declaration in dtc to cause the problem. Note that upstream dtc builds fine with bison-2.4 Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- util/dtc/dtc-parser.y | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/dtc/dtc-parser.y b/util/dtc/dtc-parser.y index 0ed970d..f150006 100644 --- a/util/dtc/dtc-parser.y +++ b/util/dtc/dtc-parser.y @@ -150,7 +150,7 @@ config: DT_CONFIG '(' if ((namelen > 4) && (! strncmp(&name[namelen-4], ".dts", 4))) $6->label[namelen-4] = '\0'; - $$ = $6 + $$ = $6; } | ; -- 1.6.0.2

2 2

r1004 - coreboot-v3/util/dtc
by svn＠coreboot.org 12 Nov '08

12 Nov '08

Author: mraudsepp Date: 2008-11-12 18:04:15 +0100 (Wed, 12 Nov 2008) New Revision: 1004 Modified: coreboot-v3/util/dtc/dtc-parser.y Log: Fix a build error when using bison-2.4 This fixes one of the errors from using bison-2.4, but there are more. This one in details is the following error: BISON build/util/dtc/dtc-parser.tab.c HOSTCC build/util/dtc/dtc-parser.tab.o /home/leio/dev/coreboot-v3/util/dtc/dtc-parser.y: In function ?\226?\128?\152yyuserAction?\226?\128?\153: /home/leio/dev/coreboot-v3/util/dtc/dtc-parser.y:154: error: expected ?\226?\128?\152;?\226?\128?\153 before ?\226?\128?\152}?\226?\128?\153 token make: *** [/home/leio/dev/coreboot-v3/build/util/dtc/dtc-parser.tab.o] Error 1 Note that 2.4.1 might be made to still work without the semi-colon for some languages, but I understand 2.5 then still won't work without one. As it builds fine with this change with bison-2.3, it should be safe to just add the semicolon. The remaining error is the following: /home/leio/dev/coreboot-v3/util/dtc/dtc-lexer.l: In function ?\226?\128?\152yylex?\226?\128?\153: /home/leio/dev/coreboot-v3/util/dtc/dtc-lexer.l:73: error: ?\226?\128?\152yylval?\226?\128?\153 undeclared (first use in this function) /home/leio/dev/coreboot-v3/util/dtc/dtc-lexer.l:73: error: (Each undeclared identifier is reported only once /home/leio/dev/coreboot-v3/util/dtc/dtc-lexer.l:73: error: for each function it appears in.) dtc-parser.tab.h doesn't seem to get an "extern YYSTYPE yylval" declaration, which per documentation should only happen for pure parser cases ("%define api.pure"), but I can't find any such declaration in dtc to cause the problem. Note that upstream dtc builds fine with bison-2.4 Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/util/dtc/dtc-parser.y =================================================================== --- coreboot-v3/util/dtc/dtc-parser.y 2008-11-12 16:57:33 UTC (rev 1003) +++ coreboot-v3/util/dtc/dtc-parser.y 2008-11-12 17:04:15 UTC (rev 1004) @@ -150,7 +150,7 @@ if ((namelen > 4) && (! strncmp(&name[namelen-4], ".dts", 4))) $6->label[namelen-4] = '\0'; - $$ = $6 + $$ = $6; } | ;

1 0

← Newer
1
...
27
28
29
30
31
32
33
...
49
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot November 2008