coreboot November 2008

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490 discussions

Re: [coreboot] r3754 - trunk/util/flashrom
by Peter Stuge 15 Nov '08

15 Nov '08

svn(a)coreboot.org wrote: > Log: > The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs. Then they do not belong in the flashrom code at all. //Peter

2 1

r1030 - coreboot-v3/superio/via/vt1211
by svn＠coreboot.org 15 Nov '08

15 Nov '08

Author: uwe Date: 2008-11-15 17:17:12 +0100 (Sat, 15 Nov 2008) New Revision: 1030 Removed: coreboot-v3/superio/via/vt1211/superio.c Modified: coreboot-v3/superio/via/vt1211/stage1.c Log: Drop non-working, copy-paste superio.c file (trivial). The build system isn't even using it so far, but if it would the build would break (and the code wouldn't work for this hardware). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: coreboot-v3/superio/via/vt1211/stage1.c =================================================================== --- coreboot-v3/superio/via/vt1211/stage1.c 2008-11-15 16:13:12 UTC (rev 1029) +++ coreboot-v3/superio/via/vt1211/stage1.c 2008-11-15 16:17:12 UTC (rev 1030) @@ -27,7 +27,7 @@ rawpnp_enter_ext_func_mode(dev); rawpnp_set_logical_device(dev, serial); rawpnp_set_enable(dev, 0); - rawpnp_set_iobase(dev, 2, (iobase>>2) & 0xff); + rawpnp_set_iobase(dev, 2, (iobase >> 2) & 0xff); rawpnp_set_enable(dev, 1); rawpnp_exit_ext_func_mode(dev); } Deleted: coreboot-v3/superio/via/vt1211/superio.c =================================================================== --- coreboot-v3/superio/via/vt1211/superio.c 2008-11-15 16:13:12 UTC (rev 1029) +++ coreboot-v3/superio/via/vt1211/superio.c 2008-11-15 16:17:12 UTC (rev 1030) @@ -1,216 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2000 AG Electronics Ltd. - * Copyright 2003-2004 Linux Networx - * Copyright 2004 Tyan - * By LYH change from PC87360 - * Copyright 2007 coresystems GmbH - * - * FIXME: This is total hack and slash of v2 code - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <io.h> -#include <lib.h> -#include <device/device.h> -#include <device/pnp.h> -#include <console.h> -#include <string.h> -//#include <bitops.h> -#include <uart8250.h> -#include <keyboard.h> -// #include <pc80/mc146818rtc.h> -#include <statictree.h> -#include "w83627hf.h" - -static void pnp_enter_ext_func_mode(struct device * dev) -{ - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(struct device * dev) -{ - outb(0xaa, dev->path.pnp.port); -} - -static void pnp_write_index(u16 port_base, u8 reg, u8 value) -{ - outb(reg, port_base); - outb(value, port_base + 1); -} - -static u8 pnp_read_index(u16 port_base, u8 reg) -{ - outb(reg, port_base); - return inb(port_base + 1); -} - -static void enable_hwm_smbus(struct device * dev) { - /* set the pin 91,92 as I2C bus */ - u8 reg, value; - reg = 0x2b; - value = pnp_read_config(dev, reg); - value &= 0x3f; - pnp_write_config(dev, reg, value); -} - -static void init_acpi(struct device * dev) -{ - u8 value = 0x20; - int power_on = 1; -#warning Fix CMOS handling - // get_option(&power_on, "power_on_after_fail"); - pnp_enter_ext_func_mode(dev); - pnp_write_index(dev->path.pnp.port,7,0x0a); - value = pnp_read_config(dev, 0xE4); - value &= ~(3<<5); - if(power_on) { - value |= (1<<5); - } - pnp_write_config(dev, 0xE4, value); - pnp_exit_ext_func_mode(dev); -} - -static void init_hwm(u16 base) -{ - u8 reg, value; - int i; - - unsigned hwm_reg_values[] = { - /* reg, mask, data */ - 0x40, 0xff, 0x81, /* start HWM */ - 0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */ - 0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */ - 0x4e, 0x80, 0x00, - 0x43, 0x00, 0xff, - 0x44, 0x00, 0x3f, - 0x4c, 0xbf, 0x18, - 0x4d, 0xff, 0x80 /* turn off beep */ - }; - - for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) { - reg = hwm_reg_values[i]; - value = pnp_read_index(base, reg); - value &= 0xff & hwm_reg_values[i+1]; - value |= 0xff & hwm_reg_values[i+2]; - - printk(BIOS_SPEW, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value); - - pnp_write_index(base, reg, value); - } -} - -static void w83627hf_init(struct device * dev) -{ - struct superio_winbond_w83627hf_dts_config *conf; - struct resource *res0, *res1; - struct pc_keyboard keyboard; - -#if 1 - printk(BIOS_ERR, "dummy init XXXX\n"); -#endif - - if (!dev->enabled) { - return; - } - - conf = dev->device_configuration; - switch(dev->path.pnp.device) { - case W83627HF_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); -#warning init_uart8250 - //init_uart8250(res0->base, &conf->com1); - break; - case W83627HF_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); -#warning init_uart8250 - //init_uart8250(res0->base, &conf->com2); - break; - case W83627HF_KBC: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &keyboard); - break; - case W83627HF_HWM: - res0 = find_resource(dev, PNP_IDX_IO0); -#define HWM_INDEX_PORT 5 - init_hwm(res0->base + HWM_INDEX_PORT); - break; - case W83627HF_ACPI: - init_acpi(dev); - break; - } -} - -void w83627hf_pnp_set_resources(struct device * dev) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_resources(dev); - pnp_exit_ext_func_mode(dev); -} - -void w83627hf_pnp_enable_resources(struct device * dev) -{ - pnp_enter_ext_func_mode(dev); - pnp_enable_resources(dev); - switch(dev->path.pnp.device) { - case W83627HF_HWM: - printk(BIOS_DEBUG, "w83627hf hwm smbus enabled\n"); - enable_hwm_smbus(dev); - break; - } - pnp_exit_ext_func_mode(dev); -} - -void w83627hf_pnp_enable(struct device * dev) -{ - if (!dev->enabled) { - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_exit_ext_func_mode(dev); - } -} -static void phase2_setup_scan_bus(struct device *dev); -struct device_operations w83627hf_ops = { - .phase2_setup_scan_bus = phase2_setup_scan_bus, - .phase4_read_resources = pnp_read_resources, - .phase4_set_resources = w83627hf_pnp_set_resources, - .phase4_enable_disable = w83627hf_pnp_enable_resources, - .phase5_enable_resources = w83627hf_pnp_enable, - .phase6_init = w83627hf_init, -}; - -static struct pnp_info pnp_dev_info[] = { - { &w83627hf_ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &w83627hf_ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &w83627hf_ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &w83627hf_ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - // No 4 { 0,}, - { &w83627hf_ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &w83627hf_ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, }, - { &w83627hf_ops, W83627HF_GPIO2, }, - { &w83627hf_ops, W83627HF_GPIO3, }, - { &w83627hf_ops, W83627HF_ACPI, }, - { &w83627hf_ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, -}; - -static void phase2_setup_scan_bus(struct device *dev) -{ - pnp_enable_devices(dev, &w83627hf_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -}

1 0

r1029 - coreboot-v3/mainboard/via/epia-cn
by svn＠coreboot.org 15 Nov '08

15 Nov '08

Author: uwe Date: 2008-11-15 17:13:12 +0100 (Sat, 15 Nov 2008) New Revision: 1029 Modified: coreboot-v3/mainboard/via/epia-cn/stage1.c Log: Fix EPIA-CN build in v3 by dropping duplicated stop_ap() definition (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: coreboot-v3/mainboard/via/epia-cn/stage1.c =================================================================== --- coreboot-v3/mainboard/via/epia-cn/stage1.c 2008-11-14 23:03:54 UTC (rev 1028) +++ coreboot-v3/mainboard/via/epia-cn/stage1.c 2008-11-15 16:13:12 UTC (rev 1029) @@ -29,11 +29,6 @@ #include <superio/fintek/f71805f/f71805f.h> #include <northbridge/via/cn700/cn700.h> -/* Someday, we're all going multicore. */ -void stop_ap(void) -{ -} - void hardware_stage1(void) { void early_mtrr_init(void);

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Trac reminder: list of new ticket(s)
by coreboot tracker 15 Nov '08

15 Nov '08

1 0

SuperIO cleanup
by Myles Watson 15 Nov '08

15 Nov '08

This patch makes it so there's not so much extra information in pnp_info. IRQs and DRQs just need values. It also moves enable to the end so it doesn't look like it needs to be set in superio.c. It just needs to be set in the dts. I decided that it makes sense to create a serial port and keyboard by default. It also makes a return value explicitly 1 or 0 instead of using !!. It needs to be done for the other SuperIOs as well, but I'd like to get the w83627hf to a good place before I update the others. I'm fine with not committing until we can agree on how to do this right. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Related note: Could someone who understands how SuperIOs work comment on the duplicated functions in superio.c? (Uwe, you've added SuperIO support for several chips) pnp_read_index and friends look like they should go somewhere shared so we don't have to update so much code every time we port a new SuperIO. Are they standard but were static for romcc? Are they specific to SuperIO vendors? Thanks, Myles

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[PATCH] flashrom: Implement probe support for Atmel chips
by Carl-Daniel Hailfinger 15 Nov '08

15 Nov '08

The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs. The AT45 series SPI chips are DataFlash EEPROMs which means they have odd (non-power-of-two) sector sizes, but some of the DataFlash chips can be configured or ordered with power-of-two sector sizes. Add probe support for the following Atmel SPI chips: AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF041 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 AT45CS1282 AT45DB011D AT45DB021D AT45DB041D AT45DB081D AT45DB161D AT45DB321C AT45DB321D AT45DB642D Add an explanation why the following chips can't be probed: AT45BR3214B AT45D011 AT45D021A AT45D041A AT45D081A AT45D161 AT45DB011 AT45DB011B AT45DB021A AT45DB021B AT45DB041A AT45DB081A AT45DB161 AT45DB161B AT45DB321 AT45DB321B AT45DB642 Add the ID, but no probing function for this chip: AT25F512A This is needed for some Intel boards. Patch attached for Gmail users. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-atmel/flash.h =================================================================== --- flashrom-atmel/flash.h (Revision 3751) +++ flashrom-atmel/flash.h (Arbeitskopie) @@ -139,13 +139,45 @@ #define AT_25DF321 0x4700 /* also 26DF321 */ #define AT_25DF321A 0x4701 #define AT_25DF641 0x4800 +#define AT_25F512A 0x65 /* Needs special RDID. AT25F512A_RDID 15 1d */ +#define AT_25F512B 0x6500 +#define AT_25FS010 0x6601 +#define AT_25FS040 0x6604 #define AT_26DF041 0x4400 #define AT_26DF081 0x4500 /* guessed, no datasheet available */ #define AT_26DF081A 0x4501 #define AT_26DF161 0x4600 #define AT_26DF161A 0x4601 +#define AT_26DF321 0x4700 /* also 25DF321 */ +#define AT_26F004 0x0400 #define AT_29C040A 0xA4 #define AT_29C020 0xDA +#define AT_45BR3214B /* No ID available */ +#define AT_45CS1282 0x2920 +#define AT_45D011 /* No ID available */ +#define AT_45D021A /* No ID available */ +#define AT_45D041A /* No ID available */ +#define AT_45D081A /* No ID available */ +#define AT_45D161 /* No ID available */ +#define AT_45DB011 /* No ID available */ +#define AT_45DB011B /* No ID available */ +#define AT_45DB011D 0x2200 +#define AT_45DB021A /* No ID available */ +#define AT_45DB021B /* No ID available */ +#define AT_45DB021D 0x2300 +#define AT_45DB041A /* No ID available */ +#define AT_45DB041D 0x2400 +#define AT_45DB081A /* No ID available */ +#define AT_45DB081D 0x2500 +#define AT_45DB161 /* No ID available */ +#define AT_45DB161B /* No ID available */ +#define AT_45DB161D 0x2600 +#define AT_45DB321 /* No ID available */ +#define AT_45DB321B /* No ID available */ +#define AT_45DB321C 0x2700 +#define AT_45DB321D 0x2701 /* Buggy data sheet */ +#define AT_45DB642 /* No ID available */ +#define AT_45DB642D 0x2800 #define AT_49F002N 0x07 /* for AT49F002(N) */ #define AT_49F002NT 0x08 /* for AT49F002(N)T */ Index: flashrom-atmel/flashchips.c =================================================================== --- flashrom-atmel/flashchips.c (Revision 3751) +++ flashrom-atmel/flashchips.c (Arbeitskopie) @@ -38,11 +38,36 @@ {"AMD", "Am29F040B", AMD_ID, AM_29F040B, 512, 64 * 1024, TEST_OK_PREW, probe_29f040b, erase_29f040b, write_29f040b}, {"AMD", "Am29LV040B", AMD_ID, AM_29LV040B, 512, 64 * 1024, TEST_UNTESTED, probe_29f040b, erase_29f040b, write_29f040b}, {"ASD", "AE49F2008", ASD_ID, ASD_AE49F2008, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, + {"Atmel", "AT25DF021", ATMEL_ID, AT_25DF021, 256, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF041A", ATMEL_ID, AT_25DF041A, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF081", ATMEL_ID, AT_25DF081, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF161", ATMEL_ID, AT_25DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Atmel", "AT25DF321A", ATMEL_ID, AT_25DF321A, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF641", ATMEL_ID, AT_25DF641, 8192, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25F512B", ATMEL_ID, AT_25F512B, 64, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25FS010", ATMEL_ID, AT_25FS010, 128, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25FS040", ATMEL_ID, AT_25FS040, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT26DF041", ATMEL_ID, AT_26DF041, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL}, + {"Atmel", "AT26DF081A", ATMEL_ID, AT_26DF081A, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT26DF161", ATMEL_ID, AT_26DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT26DF161A", ATMEL_ID, AT_26DF161A, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + /*The AT26DF321 has the same ID as the AT25DF321. */ + /*{"Atmel", "AT26DF321", ATMEL_ID, AT_26DF321, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL},*/ + {"Atmel", "AT26F004", ATMEL_ID, AT_26F004, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL}, {"Atmel", "AT29C020", ATMEL_ID, AT_29C020, 256, 256, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT29C040A", ATMEL_ID, AT_29C040A, 512, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, + {"Atmel", "AT45CS1282", ATMEL_ID, AT_45CS1282, 16896/*!*/,1056/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL /* Incompatible read */}, /* No power of two sizes */ + {"Atmel", "AT45DB011D", ATMEL_ID, AT_45DB011D, 128/*!*/,256/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB021D", ATMEL_ID, AT_45DB021D, 256/*!*/,256/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB041D", ATMEL_ID, AT_45DB041D, 512/*!*/,256/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB081D", ATMEL_ID, AT_45DB081D, 1024/*!*/,256/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB161D", ATMEL_ID, AT_45DB161D, 2048/*!*/,512/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB321C", ATMEL_ID, AT_45DB321C, 4224/*!*/,528/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL /* Incompatible read */}, /* No power of two sizes */ + {"Atmel", "AT45DB321D", ATMEL_ID, AT_45DB321D, 4096/*!*/,512/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB642D", ATMEL_ID, AT_45DB642D, 8192/*!*/,1024/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ {"Atmel", "AT49F002(N)", ATMEL_ID, AT_49F002N, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, {"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT, 256, 256, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_49f002}, - {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"AMIC", "A25L40P", AMIC_ID, AMIC_A25L40P, 512, 256, TEST_OK_PREW, probe_spi_rdid4, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"AMIC", "A29002B", AMIC_ID_NOPREFIX, AMIC_A29002B, 256, 64 * 1024, TEST_UNTESTED, probe_29f002, erase_29f002, write_29f002}, {"AMIC", "A29002T", AMIC_ID_NOPREFIX, AMIC_A29002T, 256, 64 * 1024, TEST_OK_PREW, probe_29f002, erase_29f002, write_29f002}, @@ -157,6 +182,7 @@ {"Winbond", "W39V080FA", WINBOND_ID, W_39V080FA, 1024, 64*1024, TEST_OK_PREW, probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub}, {"Winbond", "W39V080FA (dual mode)",WINBOND_ID, W_39V080FA_DM, 512, 64*1024, TEST_UNTESTED, probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub}, + {"Atmel", "unknown Atmel SPI chip",ATMEL_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, {"EON", "unknown EON SPI chip", EON_ID_NOPREFIX,GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, {"Macronix", "unknown Macronix SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, {"PMC", "unknown PMC SPI chip", PMC_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, Index: flashrom-atmel/spi.h =================================================================== --- flashrom-atmel/spi.h (Revision 3751) +++ flashrom-atmel/spi.h (Arbeitskopie) @@ -29,6 +29,16 @@ #define JEDEC_RDID_OUTSIZE 0x01 #define JEDEC_RDID_INSIZE 0x03 +/* AT25F512A has bit 3 as don't care bit in commands */ +#define AT25F512A_RDID 0x15 +#define AT25F512A_RDID_OUTSIZE 0x01 +#define AT25F512A_RDID_INSIZE 0x02 + +/* Read Electronic Manufacturer Signature */ +#define JEDEC_REMS 0x +#define JEDEC_REMS_OUTSIZE 0x +#define JEDEC_REMS_INSIZE 0x + /* Read Electronic Signature */ #define JEDEC_RES 0xab #define JEDEC_RES_OUTSIZE 0x04 @@ -54,7 +64,7 @@ #define JEDEC_CE_C7_OUTSIZE 0x01 #define JEDEC_CE_C7_INSIZE 0x00 -/* Block Erase 0x52 is supported by SST chips. */ +/* Block Erase 0x52 is supported by SST and old Atmel chips. */ #define JEDEC_BE_52 0x52 #define JEDEC_BE_52_OUTSIZE 0x04 #define JEDEC_BE_52_INSIZE 0x00 -- http://www.hailfinger.org/ Index: flashrom-atmel/flash.h =================================================================== --- flashrom-atmel/flash.h (Revision 3751) +++ flashrom-atmel/flash.h (Arbeitskopie) @@ -139,13 +139,45 @@ #define AT_25DF321 0x4700 /* also 26DF321 */ #define AT_25DF321A 0x4701 #define AT_25DF641 0x4800 +#define AT_25F512A 0x65 /* Needs special RDID. AT25F512A_RDID 15 1d */ +#define AT_25F512B 0x6500 +#define AT_25FS010 0x6601 +#define AT_25FS040 0x6604 #define AT_26DF041 0x4400 #define AT_26DF081 0x4500 /* guessed, no datasheet available */ #define AT_26DF081A 0x4501 #define AT_26DF161 0x4600 #define AT_26DF161A 0x4601 +#define AT_26DF321 0x4700 /* also 25DF321 */ +#define AT_26F004 0x0400 #define AT_29C040A 0xA4 #define AT_29C020 0xDA +#define AT_45BR3214B /* No ID available */ +#define AT_45CS1282 0x2920 +#define AT_45D011 /* No ID available */ +#define AT_45D021A /* No ID available */ +#define AT_45D041A /* No ID available */ +#define AT_45D081A /* No ID available */ +#define AT_45D161 /* No ID available */ +#define AT_45DB011 /* No ID available */ +#define AT_45DB011B /* No ID available */ +#define AT_45DB011D 0x2200 +#define AT_45DB021A /* No ID available */ +#define AT_45DB021B /* No ID available */ +#define AT_45DB021D 0x2300 +#define AT_45DB041A /* No ID available */ +#define AT_45DB041D 0x2400 +#define AT_45DB081A /* No ID available */ +#define AT_45DB081D 0x2500 +#define AT_45DB161 /* No ID available */ +#define AT_45DB161B /* No ID available */ +#define AT_45DB161D 0x2600 +#define AT_45DB321 /* No ID available */ +#define AT_45DB321B /* No ID available */ +#define AT_45DB321C 0x2700 +#define AT_45DB321D 0x2701 /* Buggy data sheet */ +#define AT_45DB642 /* No ID available */ +#define AT_45DB642D 0x2800 #define AT_49F002N 0x07 /* for AT49F002(N) */ #define AT_49F002NT 0x08 /* for AT49F002(N)T */ Index: flashrom-atmel/flashchips.c =================================================================== --- flashrom-atmel/flashchips.c (Revision 3751) +++ flashrom-atmel/flashchips.c (Arbeitskopie) @@ -38,11 +38,36 @@ {"AMD", "Am29F040B", AMD_ID, AM_29F040B, 512, 64 * 1024, TEST_OK_PREW, probe_29f040b, erase_29f040b, write_29f040b}, {"AMD", "Am29LV040B", AMD_ID, AM_29LV040B, 512, 64 * 1024, TEST_UNTESTED, probe_29f040b, erase_29f040b, write_29f040b}, {"ASD", "AE49F2008", ASD_ID, ASD_AE49F2008, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, + {"Atmel", "AT25DF021", ATMEL_ID, AT_25DF021, 256, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF041A", ATMEL_ID, AT_25DF041A, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF081", ATMEL_ID, AT_25DF081, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF161", ATMEL_ID, AT_25DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Atmel", "AT25DF321A", ATMEL_ID, AT_25DF321A, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF641", ATMEL_ID, AT_25DF641, 8192, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25F512B", ATMEL_ID, AT_25F512B, 64, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25FS010", ATMEL_ID, AT_25FS010, 128, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25FS040", ATMEL_ID, AT_25FS040, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT26DF041", ATMEL_ID, AT_26DF041, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL}, + {"Atmel", "AT26DF081A", ATMEL_ID, AT_26DF081A, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT26DF161", ATMEL_ID, AT_26DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT26DF161A", ATMEL_ID, AT_26DF161A, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + /*The AT26DF321 has the same ID as the AT25DF321. */ + /*{"Atmel", "AT26DF321", ATMEL_ID, AT_26DF321, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL},*/ + {"Atmel", "AT26F004", ATMEL_ID, AT_26F004, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL}, {"Atmel", "AT29C020", ATMEL_ID, AT_29C020, 256, 256, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT29C040A", ATMEL_ID, AT_29C040A, 512, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, + {"Atmel", "AT45CS1282", ATMEL_ID, AT_45CS1282, 16896/*!*/,1056/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL /* Incompatible read */}, /* No power of two sizes */ + {"Atmel", "AT45DB011D", ATMEL_ID, AT_45DB011D, 128/*!*/,256/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB021D", ATMEL_ID, AT_45DB021D, 256/*!*/,256/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB041D", ATMEL_ID, AT_45DB041D, 512/*!*/,256/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB081D", ATMEL_ID, AT_45DB081D, 1024/*!*/,256/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB161D", ATMEL_ID, AT_45DB161D, 2048/*!*/,512/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB321C", ATMEL_ID, AT_45DB321C, 4224/*!*/,528/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL /* Incompatible read */}, /* No power of two sizes */ + {"Atmel", "AT45DB321D", ATMEL_ID, AT_45DB321D, 4096/*!*/,512/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB642D", ATMEL_ID, AT_45DB642D, 8192/*!*/,1024/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ {"Atmel", "AT49F002(N)", ATMEL_ID, AT_49F002N, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, {"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT, 256, 256, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_49f002}, - {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"AMIC", "A25L40P", AMIC_ID, AMIC_A25L40P, 512, 256, TEST_OK_PREW, probe_spi_rdid4, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"AMIC", "A29002B", AMIC_ID_NOPREFIX, AMIC_A29002B, 256, 64 * 1024, TEST_UNTESTED, probe_29f002, erase_29f002, write_29f002}, {"AMIC", "A29002T", AMIC_ID_NOPREFIX, AMIC_A29002T, 256, 64 * 1024, TEST_OK_PREW, probe_29f002, erase_29f002, write_29f002}, @@ -157,6 +182,7 @@ {"Winbond", "W39V080FA", WINBOND_ID, W_39V080FA, 1024, 64*1024, TEST_OK_PREW, probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub}, {"Winbond", "W39V080FA (dual mode)",WINBOND_ID, W_39V080FA_DM, 512, 64*1024, TEST_UNTESTED, probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub}, + {"Atmel", "unknown Atmel SPI chip",ATMEL_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, {"EON", "unknown EON SPI chip", EON_ID_NOPREFIX,GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, {"Macronix", "unknown Macronix SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, {"PMC", "unknown PMC SPI chip", PMC_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, Index: flashrom-atmel/spi.h =================================================================== --- flashrom-atmel/spi.h (Revision 3751) +++ flashrom-atmel/spi.h (Arbeitskopie) @@ -29,6 +29,16 @@ #define JEDEC_RDID_OUTSIZE 0x01 #define JEDEC_RDID_INSIZE 0x03 +/* AT25F512A has bit 3 as don't care bit in commands */ +#define AT25F512A_RDID 0x15 +#define AT25F512A_RDID_OUTSIZE 0x01 +#define AT25F512A_RDID_INSIZE 0x02 + +/* Read Electronic Manufacturer Signature */ +#define JEDEC_REMS 0x +#define JEDEC_REMS_OUTSIZE 0x +#define JEDEC_REMS_INSIZE 0x + /* Read Electronic Signature */ #define JEDEC_RES 0xab #define JEDEC_RES_OUTSIZE 0x04 @@ -54,7 +64,7 @@ #define JEDEC_CE_C7_OUTSIZE 0x01 #define JEDEC_CE_C7_INSIZE 0x00 -/* Block Erase 0x52 is supported by SST chips. */ +/* Block Erase 0x52 is supported by SST and old Atmel chips. */ #define JEDEC_BE_52 0x52 #define JEDEC_BE_52_OUTSIZE 0x04 #define JEDEC_BE_52_INSIZE 0x00

2 3

r3754 - trunk/util/flashrom
by svn＠coreboot.org 15 Nov '08

15 Nov '08

Author: hailfinger Date: 2008-11-15 14:55:43 +0100 (Sat, 15 Nov 2008) New Revision: 3754 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c trunk/util/flashrom/spi.h Log: The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs. The AT45 series SPI chips are DataFlash EEPROMs which means they have odd (non-power-of-two) sector sizes, but some of the DataFlash chips can be configured or ordered with power-of-two sector sizes. Add probe support for the following Atmel SPI chips: AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF041 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 AT45CS1282 AT45DB011D AT45DB021D AT45DB041D AT45DB081D AT45DB161D AT45DB321C AT45DB321D AT45DB642D Add an explanation why the following chips can't be probed: AT45BR3214B AT45D011 AT45D021A AT45D041A AT45D081A AT45D161 AT45DB011 AT45DB011B AT45DB021A AT45DB021B AT45DB041A AT45DB081A AT45DB161 AT45DB161B AT45DB321 AT45DB321B AT45DB642 Add the ID, but no probing function for this chip: AT25F512A Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested-by: Jesse Brandeburg <jesse.brandeburg(a)intel.com> Tested-by: Andriy Gapon <avg(a)icyb.net.ua> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-11-14 19:25:37 UTC (rev 3753) +++ trunk/util/flashrom/flash.h 2008-11-15 13:55:43 UTC (rev 3754) @@ -139,13 +139,45 @@ #define AT_25DF321 0x4700 /* also 26DF321 */ #define AT_25DF321A 0x4701 #define AT_25DF641 0x4800 +#define AT_25F512A 0x65 /* Needs special RDID. AT25F512A_RDID 15 1d */ +#define AT_25F512B 0x6500 +#define AT_25FS010 0x6601 +#define AT_25FS040 0x6604 #define AT_26DF041 0x4400 #define AT_26DF081 0x4500 /* guessed, no datasheet available */ #define AT_26DF081A 0x4501 #define AT_26DF161 0x4600 #define AT_26DF161A 0x4601 +#define AT_26DF321 0x4700 /* also 25DF321 */ +#define AT_26F004 0x0400 #define AT_29C040A 0xA4 #define AT_29C020 0xDA +#define AT_45BR3214B /* No ID available */ +#define AT_45CS1282 0x2920 +#define AT_45D011 /* No ID available */ +#define AT_45D021A /* No ID available */ +#define AT_45D041A /* No ID available */ +#define AT_45D081A /* No ID available */ +#define AT_45D161 /* No ID available */ +#define AT_45DB011 /* No ID available */ +#define AT_45DB011B /* No ID available */ +#define AT_45DB011D 0x2200 +#define AT_45DB021A /* No ID available */ +#define AT_45DB021B /* No ID available */ +#define AT_45DB021D 0x2300 +#define AT_45DB041A /* No ID available */ +#define AT_45DB041D 0x2400 +#define AT_45DB081A /* No ID available */ +#define AT_45DB081D 0x2500 +#define AT_45DB161 /* No ID available */ +#define AT_45DB161B /* No ID available */ +#define AT_45DB161D 0x2600 +#define AT_45DB321 /* No ID available */ +#define AT_45DB321B /* No ID available */ +#define AT_45DB321C 0x2700 +#define AT_45DB321D 0x2701 /* Buggy data sheet */ +#define AT_45DB642 /* No ID available */ +#define AT_45DB642D 0x2800 #define AT_49F002N 0x07 /* for AT49F002(N) */ #define AT_49F002NT 0x08 /* for AT49F002(N)T */ Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-11-14 19:25:37 UTC (rev 3753) +++ trunk/util/flashrom/flashchips.c 2008-11-15 13:55:43 UTC (rev 3754) @@ -38,11 +38,36 @@ {"AMD", "Am29F040B", AMD_ID, AM_29F040B, 512, 64 * 1024, TEST_OK_PREW, probe_29f040b, erase_29f040b, write_29f040b}, {"AMD", "Am29LV040B", AMD_ID, AM_29LV040B, 512, 64 * 1024, TEST_UNTESTED, probe_29f040b, erase_29f040b, write_29f040b}, {"ASD", "AE49F2008", ASD_ID, ASD_AE49F2008, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, + {"Atmel", "AT25DF021", ATMEL_ID, AT_25DF021, 256, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF041A", ATMEL_ID, AT_25DF041A, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF081", ATMEL_ID, AT_25DF081, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF161", ATMEL_ID, AT_25DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Atmel", "AT25DF321A", ATMEL_ID, AT_25DF321A, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF641", ATMEL_ID, AT_25DF641, 8192, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25F512B", ATMEL_ID, AT_25F512B, 64, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25FS010", ATMEL_ID, AT_25FS010, 128, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25FS040", ATMEL_ID, AT_25FS040, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT26DF041", ATMEL_ID, AT_26DF041, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL}, + {"Atmel", "AT26DF081A", ATMEL_ID, AT_26DF081A, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT26DF161", ATMEL_ID, AT_26DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT26DF161A", ATMEL_ID, AT_26DF161A, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + /*The AT26DF321 has the same ID as the AT25DF321. */ + /*{"Atmel", "AT26DF321", ATMEL_ID, AT_26DF321, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL},*/ + {"Atmel", "AT26F004", ATMEL_ID, AT_26F004, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL}, {"Atmel", "AT29C020", ATMEL_ID, AT_29C020, 256, 256, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT29C040A", ATMEL_ID, AT_29C040A, 512, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, + {"Atmel", "AT45CS1282", ATMEL_ID, AT_45CS1282, 16896/*!*/,1056/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL /* Incompatible read */}, /* No power of two sizes */ + {"Atmel", "AT45DB011D", ATMEL_ID, AT_45DB011D, 128/*!*/,256/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB021D", ATMEL_ID, AT_45DB021D, 256/*!*/,256/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB041D", ATMEL_ID, AT_45DB041D, 512/*!*/,256/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB081D", ATMEL_ID, AT_45DB081D, 1024/*!*/,256/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB161D", ATMEL_ID, AT_45DB161D, 2048/*!*/,512/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB321C", ATMEL_ID, AT_45DB321C, 4224/*!*/,528/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL /* Incompatible read */}, /* No power of two sizes */ + {"Atmel", "AT45DB321D", ATMEL_ID, AT_45DB321D, 4096/*!*/,512/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ + {"Atmel", "AT45DB642D", ATMEL_ID, AT_45DB642D, 8192/*!*/,1024/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL, NULL}, /* Size can only be determined from status register */ {"Atmel", "AT49F002(N)", ATMEL_ID, AT_49F002N, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, {"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT, 256, 256, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_49f002}, - {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"AMIC", "A25L40P", AMIC_ID, AMIC_A25L40P, 512, 256, TEST_OK_PREW, probe_spi_rdid4, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"AMIC", "A29002B", AMIC_ID_NOPREFIX, AMIC_A29002B, 256, 64 * 1024, TEST_UNTESTED, probe_29f002, erase_29f002, write_29f002}, {"AMIC", "A29002T", AMIC_ID_NOPREFIX, AMIC_A29002T, 256, 64 * 1024, TEST_OK_PREW, probe_29f002, erase_29f002, write_29f002}, @@ -157,6 +182,7 @@ {"Winbond", "W39V080FA", WINBOND_ID, W_39V080FA, 1024, 64*1024, TEST_OK_PREW, probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub}, {"Winbond", "W39V080FA (dual mode)",WINBOND_ID, W_39V080FA_DM, 512, 64*1024, TEST_UNTESTED, probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub}, + {"Atmel", "unknown Atmel SPI chip",ATMEL_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, {"EON", "unknown EON SPI chip", EON_ID_NOPREFIX,GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, {"Macronix", "unknown Macronix SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, {"PMC", "unknown PMC SPI chip", PMC_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, Modified: trunk/util/flashrom/spi.h =================================================================== --- trunk/util/flashrom/spi.h 2008-11-14 19:25:37 UTC (rev 3753) +++ trunk/util/flashrom/spi.h 2008-11-15 13:55:43 UTC (rev 3754) @@ -54,7 +54,7 @@ #define JEDEC_CE_C7_OUTSIZE 0x01 #define JEDEC_CE_C7_INSIZE 0x00 -/* Block Erase 0x52 is supported by SST chips. */ +/* Block Erase 0x52 is supported by SST and old Atmel chips. */ #define JEDEC_BE_52 0x52 #define JEDEC_BE_52_OUTSIZE 0x04 #define JEDEC_BE_52_INSIZE 0x00

1 0

Re: [coreboot] [PATCH] flashrom: Implement probe support for Atmel chips
by Carl-Daniel Hailfinger 15 Nov '08

15 Nov '08

On 14.11.2008 17:33, FENG Yu Ning wrote: > On 11/14/08, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > >> Index: flashrom-atmel/flash.h >> =================================================================== >> --- flashrom-atmel/flash.h (Revision 3751) >> +++ flashrom-atmel/flash.h (Arbeitskopie) >> > > I am not familiar with the directory hierarchy yet. Where is > flashrom-atmel/ ? Can I see it using the ViewVC interface? I can see > the latest revision is 3752 but cannot find this r3751 flashrom-atmel/ > I renamed the directly on my disk to be able to organize my trees better. Simply apply the patch with patch -p1 and it will work for you. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

SuperIO updates
by Myles Watson 15 Nov '08

15 Nov '08

This patch updates the other supported SuperIOs to use the PNP dts changes. It should not break anything that was working, but I didn't try to fix SuperIOs that were not compiling when I started. Compile tested on 1. amd/dbm690t for ite/it8712f 2. amp/tinygx for ite/it8716f I'd already updated fintek/f71805 before I realized jetway doesn't compile. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 2

r1028 - in coreboot-v3/superio: fintek/f71805f ite/it8712f ite/it8716f
by svn＠coreboot.org 15 Nov '08

15 Nov '08

Author: myles Date: 2008-11-15 00:03:54 +0100 (Sat, 15 Nov 2008) New Revision: 1028 Modified: coreboot-v3/superio/fintek/f71805f/dts coreboot-v3/superio/fintek/f71805f/superio.c coreboot-v3/superio/ite/it8712f/dts coreboot-v3/superio/ite/it8712f/superio.c coreboot-v3/superio/ite/it8716f/dts coreboot-v3/superio/ite/it8716f/superio.c Log: This patch updates the other supported SuperIOs to use the PNP dts changes. It shouldn't break anything that was working, but I didn't try to fix SuperIOs that weren't compiling when I started. Compile tested on 1. amd/dbm690t for ite/it8712f 2. amp/tinygx for ite/it8716f I'd already updated fintek/f71805 before I realized jetway doesn't compile. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/superio/fintek/f71805f/dts =================================================================== --- coreboot-v3/superio/fintek/f71805f/dts 2008-11-14 21:45:10 UTC (rev 1027) +++ coreboot-v3/superio/fintek/f71805f/dts 2008-11-14 23:03:54 UTC (rev 1028) @@ -22,42 +22,35 @@ device_operations = "f71805f_ops"; /* Floppy */ - floppydev = "0"; floppyenable = "0"; floppyio = "0x3f0"; floppyirq = "6"; floppydrq = "2"; /* COM1 */ - com1dev = "1"; com1enable = "0"; com1io = "0x3f8"; com1irq = "4"; /* COM2 */ - com2dev = "2"; com2enable = "0"; com2io = "0x2f8"; com2irq = "3"; /* Parallel port */ - ppdev = "3"; ppenable = "0"; ppio = "0x378"; ppirq = "7"; /* Hardware Monitor */ - hwmdev = "4"; hwmenable = "0"; hwmio = "0x295"; hwmirq = "0"; /* TODO? */ /* GPIO */ - gpiodev = "6"; gpioenable = "0"; gpioirq = "0"; /* TODO? */ /* PME */ - pmedev = "10"; pmeenable = "0"; }; Modified: coreboot-v3/superio/fintek/f71805f/superio.c =================================================================== --- coreboot-v3/superio/fintek/f71805f/superio.c 2008-11-14 21:45:10 UTC (rev 1027) +++ coreboot-v3/superio/fintek/f71805f/superio.c 2008-11-14 23:03:54 UTC (rev 1028) @@ -38,25 +38,25 @@ static void pnp_enter_conf_state(struct device *dev); static void pnp_exit_conf_state(struct device *dev); -static void pnp_enter_conf_state(struct device *dev) +static void pnp_enter_conf_state(struct device *dev) { outb(0x87, dev->path.pnp.port); } -static void pnp_exit_conf_state(struct device *dev) +static void pnp_exit_conf_state(struct device *dev) { outb(0xaa, dev->path.pnp.port); } void f71805f_pnp_set_resources(struct device *dev) { - pnp_enter_conf_state(dev); + pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); -} + pnp_exit_conf_state(dev); +} void f71805f_pnp_enable_resources(struct device *dev) -{ +{ pnp_enter_conf_state(dev); pnp_enable_resources(dev); pnp_exit_conf_state(dev); @@ -64,10 +64,10 @@ void f71805f_pnp_enable(struct device *dev) { - pnp_enter_conf_state(dev); + pnp_enter_conf_state(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, dev->enabled); - pnp_exit_conf_state(dev); + pnp_exit_conf_state(dev); } static void f71805f_init(struct device *dev) @@ -77,19 +77,19 @@ if (!dev->enabled) return; - + switch (dev->path.pnp.device) { - case F71805F_COM1: + case F71805F_COM1: res0 = find_resource(dev, PNP_IDX_IO0); /* TODO: Fix these */ //uart8250_init(res0->base, &conf->sp1); break; - + case F71805F_COM2: res1 = find_resource(dev, PNP_IDX_IO0); //uart8250_init(res0->base, &conf->sp2); break; - + /* No KBC on F71805f */ } } @@ -113,5 +113,27 @@ static void phase2_setup_scan_bus(struct device *dev) { + /* Get dts values and populate pnp_dev_info. */ + const struct superio_fintek_f71805f_dts_config * const conf = dev->device_configuration; + + /* COM1 */ + pnp_dev_info[F71805F_COM1].enable = conf->com1enable; + pnp_dev_info[F71805F_COM1].io0.val = conf->com1io; + pnp_dev_info[F71805F_COM1].irq0.val = conf->com1irq; + + /* COM2 */ + pnp_dev_info[F71805F_COM2].enable = conf->com2enable; + pnp_dev_info[F71805F_COM2].io0.val = conf->com2io; + pnp_dev_info[F71805F_COM2].irq0.val = conf->com2irq; + + /* Initialize SuperIO for PNP children. */ + if (!dev->links) { + dev->links = 1; + dev->link[0].dev = dev; + dev->link[0].children = NULL; + dev->link[0].link = 0; + } + + /* Call init with updated tables to create children. */ pnp_enable_devices(dev, &f71805f_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } Modified: coreboot-v3/superio/ite/it8712f/dts =================================================================== --- coreboot-v3/superio/ite/it8712f/dts 2008-11-14 21:45:10 UTC (rev 1027) +++ coreboot-v3/superio/ite/it8712f/dts 2008-11-14 23:03:54 UTC (rev 1028) @@ -22,65 +22,54 @@ device_operations = "it8712f_ops"; /* Floppy */ - floppydev = "0"; floppyenable = "0"; floppyio = "0x3f0"; floppyirq = "6"; floppydrq = "2"; /* COM1 */ - com1dev = "1"; com1enable = "0"; com1io = "0x3f8"; com1irq = "4"; /* COM2 */ - com2dev = "2"; com2enable = "0"; com2io = "0x2f8"; com2irq = "3"; /* Parallel port */ - ppdev = "3"; ppenable = "0"; ppio = "0x378"; ppirq = "7"; /* Environment controller */ - ecdev = "4"; ecenable = "0"; ecio = "0x290"; ecirq = "9"; /* PS/2 keyboard */ - kbdev = "5"; kbenable = "0"; kbio = "0x60"; kbio2 = "0x64"; kbirq = "1"; /* PS/2 mouse */ - mousedev = "6"; mouseenable = "0"; mouseirq = "12"; /* GPIO */ - gpiodev = "7"; gpioenable = "0"; /* MIDI port */ - mididev = "8"; midienable = "0"; midiio = "0x300"; midiirq = "10"; /* Game port */ - gamedev = "9"; gameenable = "0"; gameio = "0x201"; /* Consumer IR */ - cirdev = "10"; cirenable = "0"; cirio = "0x310"; cirirq = "11"; Modified: coreboot-v3/superio/ite/it8712f/superio.c =================================================================== --- coreboot-v3/superio/ite/it8712f/superio.c 2008-11-14 21:45:10 UTC (rev 1027) +++ coreboot-v3/superio/ite/it8712f/superio.c 2008-11-14 23:03:54 UTC (rev 1028) @@ -102,11 +102,12 @@ pnp_set_enable(dev, dev->enabled); pnp_exit_ext_func_mode(dev); } + static void it8712f_setup_scan_bus(struct device *dev); struct device_operations it8712f_ops = { .phase3_chip_setup_dev = it8712f_setup_scan_bus, - .phase3_enable = it8712f_pnp_enable_resources, + .phase3_enable = it8712f_pnp_enable_resources, .phase4_read_resources = pnp_read_resources, .phase4_set_resources = it8712f_pnp_set_resources, .phase5_enable_resources = it8712f_pnp_enable, @@ -114,22 +115,86 @@ }; static struct pnp_info pnp_dev_info[] = { - {&it8712f_ops, IT8712F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xff8, 0},}, - {&it8712f_ops, IT8712F_SP1, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, - {&it8712f_ops, IT8712F_SP2, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, - {&it8712f_ops, IT8712F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xffc, 0},}, - {&it8712f_ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xff8, 0}, {0xff8, 4},}, - {&it8712f_ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfff, 0}, {0xfff, 4},}, - {&it8712f_ops, IT8712F_KBCM, PNP_IRQ0,}, - {&it8712f_ops, IT8712F_GPIO,}, - {&it8712f_ops, IT8712F_MIDI, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, - {&it8712f_ops, IT8712F_GAME, PNP_IO0, {0xfff, 0},}, - {&it8712f_ops, IT8712F_IR, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, + /* Enable, All resources need by dev, io_info_structs */ + {&it8712f_ops, IT8712F_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xff8, 0},}, + {&it8712f_ops, IT8712F_SP1, 0, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, + {&it8712f_ops, IT8712F_SP2, 0, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, + {&it8712f_ops, IT8712F_PP, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xffc, 0},}, + {&it8712f_ops, IT8712F_EC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xff8, 0}, {0xff8, 4},}, + {&it8712f_ops, IT8712F_KBCK, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfff, 0}, {0xfff, 4},}, + {&it8712f_ops, IT8712F_KBCM, 0, PNP_IRQ0,}, + {&it8712f_ops, IT8712F_GPIO, 0, }, + {&it8712f_ops, IT8712F_MIDI, 0, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, + {&it8712f_ops, IT8712F_GAME, 0, PNP_IO0, {0xfff, 0},}, + {&it8712f_ops, IT8712F_IR, 0, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, }; static void it8712f_setup_scan_bus(struct device *dev) { + const struct superio_ite_it8712f_dts_config * const conf = dev->device_configuration; + + /* Floppy */ + pnp_dev_info[IT8712F_FDC].enable = conf->floppyenable; + pnp_dev_info[IT8712F_FDC].io0.val = conf->floppyio; + pnp_dev_info[IT8712F_FDC].irq0.val = conf->floppyirq; + pnp_dev_info[IT8712F_FDC].drq0.val = conf->floppydrq; + + /* COM1 */ + pnp_dev_info[IT8712F_SP1].enable = conf->com1enable; + pnp_dev_info[IT8712F_SP1].io0.val = conf->com1io; + pnp_dev_info[IT8712F_SP1].irq0.val = conf->com1irq; + + /* COM2 */ + pnp_dev_info[IT8712F_SP2].enable = conf->com2enable; + pnp_dev_info[IT8712F_SP2].io0.val = conf->com2io; + pnp_dev_info[IT8712F_SP2].irq0.val = conf->com2irq; + + /* Parallel port */ + pnp_dev_info[IT8712F_PP].enable = conf->ppenable; + pnp_dev_info[IT8712F_PP].io0.val = conf->ppio; + pnp_dev_info[IT8712F_PP].irq0.val = conf->ppirq; + + /* Environment controller */ + pnp_dev_info[IT8712F_EC].enable = conf->ecenable; + pnp_dev_info[IT8712F_EC].io0.val = conf->ecio; + pnp_dev_info[IT8712F_EC].irq0.val = conf->ecirq; + + /* Keyboard */ + pnp_dev_info[IT8712F_KBCK].enable = conf->kbenable; + pnp_dev_info[IT8712F_KBCK].io0.val = conf->kbio; + pnp_dev_info[IT8712F_KBCK].io1.val = conf->kbio2; + pnp_dev_info[IT8712F_KBCK].irq0.val = conf->kbirq; + + /* PS/2 mouse */ + pnp_dev_info[IT8712F_KBCM].enable = conf->mouseenable; + pnp_dev_info[IT8712F_KBCM].irq0.val = conf->mouseirq; + + /* GPIO */ + pnp_dev_info[IT8712F_GPIO].enable = conf->gpioenable; + + /* MIDI port */ + pnp_dev_info[IT8712F_MIDI].enable = conf->midienable; + pnp_dev_info[IT8712F_MIDI].io0.val = conf->midiio; + pnp_dev_info[IT8712F_MIDI].irq0.val = conf->midiirq; + + /* Game port */ + pnp_dev_info[IT8712F_GAME].enable = conf->gameenable; + pnp_dev_info[IT8712F_GAME].io0.val = conf->gameio; + + /* Consumer IR */ + pnp_dev_info[IT8712F_IR].enable = conf->cirenable; + pnp_dev_info[IT8712F_IR].io0.val = conf->cirio; + pnp_dev_info[IT8712F_IR].irq0.val = conf->cirirq; + + /* Initialize SuperIO for PNP children. */ + if (!dev->links) { + dev->links = 1; + dev->link[0].dev = dev; + dev->link[0].children = NULL; + dev->link[0].link = 0; + } + + /* Call init with updated tables to create children. */ pnp_enable_devices(dev, &it8712f_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } - Modified: coreboot-v3/superio/ite/it8716f/dts =================================================================== --- coreboot-v3/superio/ite/it8716f/dts 2008-11-14 21:45:10 UTC (rev 1027) +++ coreboot-v3/superio/ite/it8716f/dts 2008-11-14 23:03:54 UTC (rev 1028) @@ -22,65 +22,54 @@ device_operations = "it8716f_ops"; /* Floppy */ - floppydev = "0"; floppyenable = "0"; floppyio = "0x3f0"; floppyirq = "6"; floppydrq = "2"; /* COM1 */ - com1dev = "1"; com1enable = "0"; com1io = "0x3f8"; com1irq = "4"; /* COM2 */ - com2dev = "2"; com2enable = "0"; com2io = "0x2f8"; com2irq = "3"; /* Parallel port */ - ppdev = "3"; ppenable = "0"; ppio = "0x378"; ppirq = "7"; /* Environment controller */ - ecdev = "4"; ecenable = "0"; ecio = "0x290"; ecirq = "9"; /* PS/2 keyboard */ - kbdev = "5"; kbenable = "0"; kbio = "0x60"; kbio2 = "0x64"; kbirq = "1"; /* PS/2 mouse */ - mousedev = "6"; mouseenable = "0"; mouseirq = "12"; /* GPIO */ - gpiodev = "7"; gpioenable = "0"; /* MIDI port */ - mididev = "8"; midienable = "0"; midiio = "0x300"; midiirq = "10"; /* Game port */ - gamedev = "9"; gameenable = "0"; gameio = "0x201"; /* Consumer IR */ - cirdev = "10"; cirenable = "0"; cirio = "0x310"; cirirq = "11"; Modified: coreboot-v3/superio/ite/it8716f/superio.c =================================================================== --- coreboot-v3/superio/ite/it8716f/superio.c 2008-11-14 21:45:10 UTC (rev 1027) +++ coreboot-v3/superio/ite/it8716f/superio.c 2008-11-14 23:03:54 UTC (rev 1028) @@ -144,32 +144,99 @@ } static void it8716f_setup_scan_bus(struct device *dev); + struct device_operations it8716f_ops = { - .phase2_setup_scan_bus = it8716f_setup_scan_bus, + .phase3_chip_setup_dev = it8716f_setup_scan_bus, + .phase3_enable = it8716f_pnp_enable_disable, .phase4_read_resources = pnp_read_resources, .phase4_set_resources = it8716f_pnp_set_resources, - .phase4_enable_disable = it8716f_pnp_enable_disable, .phase5_enable_resources = it8716f_pnp_enable_resources, .phase6_init = it8716f_init, }; static struct pnp_info pnp_dev_info[] = { - {&it8716f_ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, - {&it8716f_ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, - {&it8716f_ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, - {&it8716f_ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, - {&it8716f_ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, + /* Enable, All resources need by dev, io_info_structs */ + {&it8716f_ops, IT8716F_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, + {&it8716f_ops, IT8716F_SP1, 0, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, + {&it8716f_ops, IT8716F_SP2, 0, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, + {&it8716f_ops, IT8716F_PP, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, + {&it8716f_ops, IT8716F_EC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, {0x7f8, 0x4},}, - {&it8716f_ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0}, + {&it8716f_ops, IT8716F_KBCK, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0}, {0x7ff, 0x4},}, - {&it8716f_ops, IT8716F_KBCM, PNP_IRQ0,}, - {&it8716f_ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},}, - {&it8716f_ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},}, - {&it8716f_ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},}, - {&it8716f_ops, IT8716F_IR,}, + {&it8716f_ops, IT8716F_KBCM, 0, PNP_IRQ0,}, + {&it8716f_ops, IT8716F_GPIO, 0, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},}, + {&it8716f_ops, IT8716F_MIDI, 0, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},}, + {&it8716f_ops, IT8716F_GAME, 0, PNP_IO0, {0x7ff, 0},}, + {&it8716f_ops, IT8716F_IR, 0,}, }; static void it8716f_setup_scan_bus(struct device *dev) { - pnp_enable_devices(dev, &it8716f_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); + const struct superio_ite_it8716f_dts_config * const conf = dev->device_configuration; + + /* Floppy */ + pnp_dev_info[IT8716F_FDC].enable = conf->floppyenable; + pnp_dev_info[IT8716F_FDC].io0.val = conf->floppyio; + pnp_dev_info[IT8716F_FDC].irq0.val = conf->floppyirq; + pnp_dev_info[IT8716F_FDC].drq0.val = conf->floppydrq; + + /* COM1 */ + pnp_dev_info[IT8716F_SP1].enable = conf->com1enable; + pnp_dev_info[IT8716F_SP1].io0.val = conf->com1io; + pnp_dev_info[IT8716F_SP1].irq0.val = conf->com1irq; + + /* COM2 */ + pnp_dev_info[IT8716F_SP2].enable = conf->com2enable; + pnp_dev_info[IT8716F_SP2].io0.val = conf->com2io; + pnp_dev_info[IT8716F_SP2].irq0.val = conf->com2irq; + + /* Parallel port */ + pnp_dev_info[IT8716F_PP].enable = conf->ppenable; + pnp_dev_info[IT8716F_PP].io0.val = conf->ppio; + pnp_dev_info[IT8716F_PP].irq0.val = conf->ppirq; + + /* Environment controller */ + pnp_dev_info[IT8716F_EC].enable = conf->ecenable; + pnp_dev_info[IT8716F_EC].io0.val = conf->ecio; + pnp_dev_info[IT8716F_EC].irq0.val = conf->ecirq; + + /* Keyboard */ + pnp_dev_info[IT8716F_KBCK].enable = conf->kbenable; + pnp_dev_info[IT8716F_KBCK].io0.val = conf->kbio; + pnp_dev_info[IT8716F_KBCK].io1.val = conf->kbio2; + pnp_dev_info[IT8716F_KBCK].irq0.val = conf->kbirq; + + /* PS/2 mouse */ + pnp_dev_info[IT8716F_KBCM].enable = conf->mouseenable; + pnp_dev_info[IT8716F_KBCM].irq0.val = conf->mouseirq; + + /* GPIO */ + pnp_dev_info[IT8716F_GPIO].enable = conf->gpioenable; + + /* MIDI port */ + pnp_dev_info[IT8716F_MIDI].enable = conf->midienable; + pnp_dev_info[IT8716F_MIDI].io0.val = conf->midiio; + pnp_dev_info[IT8716F_MIDI].irq0.val = conf->midiirq; + + /* Game port */ + pnp_dev_info[IT8716F_GAME].enable = conf->gameenable; + pnp_dev_info[IT8716F_GAME].io0.val = conf->gameio; + + /* Consumer IR */ + pnp_dev_info[IT8716F_IR].enable = conf->cirenable; + pnp_dev_info[IT8716F_IR].io0.val = conf->cirio; + pnp_dev_info[IT8716F_IR].irq0.val = conf->cirirq; + + /* Initialize SuperIO for PNP children. */ + if (!dev->links) { + dev->links = 1; + dev->link[0].dev = dev; + dev->link[0].children = NULL; + dev->link[0].link = 0; + } + + /* Call init with updated tables to create children. */ + pnp_enable_devices(dev, &it8716f_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); }

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coreboot November 2008