coreboot November 2008

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490 discussions

Re: [coreboot] r1040 - coreboot-v3/superio/winbond/w83627thg
by Peter Stuge 18 Nov '08

18 Nov '08

svn(a)coreboot.org wrote: > Fix/finish the Winbond W83627THF/THG dts. .. > +++ coreboot-v3/superio/winbond/w83627thg/dts 2008-11-17 20:40:39 UTC (rev 1040) > @@ -20,8 +20,23 @@ > > { > device_operations = "w83627thg_ops"; > + > /* To override any of these, put the over-ride in mainboard dts. */ > > + /* Floppy */ > + floppydev = "0"; > + floppyenable = "0"; > + floppyio = "0x3f0"; > + floppyirq = "6"; > + floppydrq = "2"; I would like to veto this style - it's not the dts way, it's the v2 way. Sorry if there is already consensus on this issue, but I would really like something more dtsy than that for the pnps. //Peter

4 4

Device init
by Myles Watson 18 Nov '08

18 Nov '08

It doesn't make sense to me to initialize the devices in the list. The tree seems more appropriate. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

1 0

[PATCH] v3: Fix/finish the Winbond W83627THF/THG dts
by Uwe Hermann 18 Nov '08

18 Nov '08

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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r1040 - coreboot-v3/superio/winbond/w83627thg
by svn＠coreboot.org 18 Nov '08

18 Nov '08

Author: uwe Date: 2008-11-17 21:40:39 +0100 (Mon, 17 Nov 2008) New Revision: 1040 Modified: coreboot-v3/superio/winbond/w83627thg/dts Log: Fix/finish the Winbond W83627THF/THG dts. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: coreboot-v3/superio/winbond/w83627thg/dts =================================================================== --- coreboot-v3/superio/winbond/w83627thg/dts 2008-11-17 19:18:36 UTC (rev 1039) +++ coreboot-v3/superio/winbond/w83627thg/dts 2008-11-17 20:40:39 UTC (rev 1040) @@ -20,8 +20,23 @@ { device_operations = "w83627thg_ops"; + /* To override any of these, put the over-ride in mainboard dts. */ + /* Floppy */ + floppydev = "0"; + floppyenable = "0"; + floppyio = "0x3f0"; + floppyirq = "6"; + floppydrq = "2"; + + /* Parallel port */ + ppdev = "1"; + ppenable = "0"; + ppio = "0x378"; + ppirq = "7"; + ppdrq = "4"; + /* COM1 */ com1dev = "2"; com1enable = "0"; @@ -34,11 +49,36 @@ com2io = "0x2f8"; com2irq = "3"; - /* Keyboard */ + /* PS/2 keyboard + PS/2 mouse */ kbdev = "5"; kbenable = "0"; kbio = "0x60"; - kbio2 = "0x62"; + kbio2 = "0x64"; kbirq = "1"; kbirq2 = "12"; + + /* Game port, MIDI port, GPIO1, GPIO5 */ + gamedev = "7"; + gameenable = "0"; + gameio = "0x201"; + gameio2 = "0x330"; + gameirq = "9"; + + /* GPIO2 */ + gpio2dev = "8"; + gpio2enable = "0"; + + /* GPIO3, GPIO4 */ + gpio34dev = "9"; + gpio34enable = "0"; + + /* ACPI */ + acpidev = "10"; + acpienable = "0"; + + /* Hardware Monitor */ + hwmdev = "11"; + hwmenable = "0"; + hwmio = "0x290"; + hwmirq = "5"; };

1 0

r1039 - in coreboot-v3: device northbridge/amd/k8
by svn＠coreboot.org 18 Nov '08

18 Nov '08

Author: myles Date: 2008-11-17 20:18:36 +0100 (Mon, 17 Nov 2008) New Revision: 1039 Modified: coreboot-v3/device/device.c coreboot-v3/northbridge/amd/k8/util.c Log: This patch clarifies/fixes some debug output. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: coreboot-v3/device/device.c =================================================================== --- coreboot-v3/device/device.c 2008-11-17 17:53:14 UTC (rev 1038) +++ coreboot-v3/device/device.c 2008-11-17 19:18:36 UTC (rev 1039) @@ -1095,11 +1095,9 @@ for (i = 0; i < depth; i++) depth_str[i] = ' '; depth_str[i] = '\0'; - printk(debug_level, "%s%s(%s): enabled %d have_resources %d devfn %x\n", + printk(debug_level, "%s%s(%s): enabled %d, %d resources\n", depth_str, dev->dtsname, dev_path(dev), dev->enabled, - dev->have_resources, - dev->path.type == DEVICE_PATH_PCI ? dev->path.pci.devfn : - dev->path.type == DEVICE_PATH_PNP ? dev->path.pnp.device : 0xff); + dev->resources); for (i = 0; i < dev->links; i++) { for (sibling = dev->link[i].children; sibling; sibling = sibling->sibling) Modified: coreboot-v3/northbridge/amd/k8/util.c =================================================================== --- coreboot-v3/northbridge/amd/k8/util.c 2008-11-17 17:53:14 UTC (rev 1038) +++ coreboot-v3/northbridge/amd/k8/util.c 2008-11-17 19:18:36 UTC (rev 1039) @@ -127,10 +127,11 @@ void showconfig(int level, u8 which, u32 reg) { /* Don't use node() and link() here. */ - printk(level, "CONFIG(%02x)%02x-%02x ->(%d,%d),%s %s CE %d\n", - which, BITS(reg, 24, 0xff), BITS(reg, 16, 0xff), + printk(level, "CONFIG(%02x)%02x-%02x ->(%d,%d),%s %s (%s numbers)\n", + which, BITS(reg, 16, 0xff), BITS(reg, 24, 0xff), BITS(reg, 4, 0x7), BITS(reg, 8, 0x3), - re(reg), we(reg), BITS(reg, 2, 0x1)); + re(reg), we(reg), + BITS(reg, 2, 0x1)?"dev":"bus"); } /**

1 0

HT chains fixup
by Myles Watson 18 Nov '08

18 Nov '08

This patch fixes ht chain handling. include/device/path.h: Add a ht_path type to hold chain number and UnitID. include/device/hypertransport.h: Remove offset_unitid from prototype. mainboard/amd/serengeti/dts: Update to use ht@chain,unitid. Add 8132 devices. Add pci_X for devices that would otherwise collide. Since setting the UnitID for an HT device affects the devfn of all the PCI devices on the chip, they all start at 0,0 and go from there. If you look in a data sheet it will say Dev A, function 2 and Dev B, function 3 etc. These become pci@0,2 and pci@ 1,3. device/hypertransport.c: Remove many #if statements and rely on the dts. The idea here is that we change HT devices to PCI at enumeration. That makes it so that they can be scanned on the normal PCI bus. The code is set up so that it can also scan without being given ht UnitIDs ht@chain, and then it assigns them in the order it finds them. device/pci_device.c: Add an error if there's a broken BAR. Remove an overly verbose statement Not setting VID... Add the path to a debug statement about leftover devices. device/device_util.c: Add HT support in dev_path(). device/pci_ops.c Make the debug statement more clear when there's a loop. northbridge/amd/k8/pci.c: Remove offset_unitid util/dtc/flattree.c: Add support for ht@chain,unitid. Remove broken link code. This code generated a new link when there was a sibling of a bridge that was also a bridge. This breaks Serengeti because it has two siblings that are bridges, but they are not on separate links. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Here's the resulting device tree: Notice that the only dynamic (discovered) devices are the plug-in cards. Show all devs in tree form...After phase 3. root(Root Device): enabled 1 have_resources 0 cpus(CPU: 00): enabled 1 have_resources 0 apic_0(APIC: 00): enabled 1 have_resources 0 domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 domain_0_pci_18_0(PCI: 00:18.0): enabled 1 have_resources 0 domain_0_pci_18_0_ht_0_6(PCI: 00:06.0): enabled 1 have_resources 0 domain_0_pci_18_0_ht_0_6_pci_0_0(PCI: 01:00.0): enabled 1 have_resources 0 domain_0_pci_18_0_ht_0_6_pci_0_1(PCI: 01:00.1): enabled 1 have_resources 0 domain_0_pci_18_0_ht_0_6_pci_0_2(PCI: 01:00.2): enabled 0 have_resources 0 domain_0_pci_18_0_ht_0_6_pci_1_0(PCI: 01:01.0): enabled 0 have_resources 0 dynamic PCI: 01:04.0(PCI: 01:04.0): enabled 1 have_resources 0 dynamic PCI: 01:05.0(PCI: 01:05.0): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_0(PCI: 00:07.0): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e(IOPORT: 2e): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_0(PNP: 002e.0): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_1(PNP: 002e.1): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_2(PNP: 002e.2): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_3(PNP: 002e.3): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_5(PNP: 002e.5): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_6(PNP: 002e.6): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_7(PNP: 002e.7): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_8(PNP: 002e.8): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_9(PNP: 002e.9): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_10(PNP: 002e.a): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_11(PNP: 002e.b): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_1(PCI: 00:07.1): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_2(PCI: 00:07.2): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_3(PCI: 00:07.3): enabled 1 have_resources 0 domain_0_pci_18_0_pci_6_1_5(PCI: 00:07.5): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_6(PCI: 00:07.6): enabled 0 have_resources 0 domain_0_pci_18_0_pci_6_1_7(PCI: 00:07.7): enabled 1 have_resources 0 domain_0_pci_18_0_ht_0_a(PCI: 00:0a.0): enabled 1 have_resources 0 domain_0_pci_18_0_pci_a_0_1(PCI: 00:0a.1): enabled 1 have_resources 0 domain_0_pci_18_0_pci_a_1_0(PCI: 00:0b.0): enabled 1 have_resources 0 domain_0_pci_18_0_pci_a_1_1(PCI: 00:0b.1): enabled 1 have_resources 0 domain_0_pci_18_1(PCI: 00:18.1): enabled 1 have_resources 0 domain_0_pci_18_2(PCI: 00:18.2): enabled 1 have_resources 0 domain_0_pci_18_3(PCI: 00:18.3): enabled 1 have_resources 0 I'm hoping that this gets us to the point where we can work on getting video working. Here are some of the next steps: - Get video working. - Remove #ifs from k8 chain code. - Add the rest of the devices to the dts (other processors and AGP bridge.) - Unify SIO code. - Remove links structure? - K8 doesn't need them, does anyone? Thanks, Myles

1 0

r1038 - coreboot-v3/southbridge/amd/amd8111
by svn＠coreboot.org 18 Nov '08

18 Nov '08

Author: myles Date: 2008-11-17 18:53:14 +0100 (Mon, 17 Nov 2008) New Revision: 1038 Modified: coreboot-v3/southbridge/amd/amd8111/ide.c Log: This patch fixes debug printing. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles Modified: coreboot-v3/southbridge/amd/amd8111/ide.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ide.c 2008-11-17 10:31:40 UTC (rev 1037) +++ coreboot-v3/southbridge/amd/amd8111/ide.c 2008-11-17 17:53:14 UTC (rev 1038) @@ -42,12 +42,12 @@ if (conf->ide1_enable) { /* Enable secondary ide interface */ word |= (1<<0); - printk(BIOS_DEBUG, "IDE1 "); + printk(BIOS_DEBUG, "%s: IDE1 \n", __func__); } if (conf->ide0_enable) { /* Enable primary ide interface */ word |= (1<<1); - printk(BIOS_DEBUG, "IDE0 "); + printk(BIOS_DEBUG, "%s: IDE0 \n", __func__); } word |= (1<<12);

1 0

r3755 - trunk/util/flashrom
by svn＠coreboot.org 18 Nov '08

18 Nov '08

Author: mraudsepp Date: 2008-11-17 16:31:56 +0100 (Mon, 17 Nov 2008) New Revision: 3755 Modified: trunk/util/flashrom/flashchips.c Log: flashrom: SST39VF020 TEST_OK_ PROBE READ ERASE WRITE Tested fully on a ThinCan DBE61A Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-11-15 13:55:43 UTC (rev 3754) +++ trunk/util/flashrom/flashchips.c 2008-11-17 15:31:56 UTC (rev 3755) @@ -119,7 +119,7 @@ {"SST", "SST39SF040", SST_ID, SST_39SF040, 512, 4096, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39VF512", SST_ID, SST_39VF512, 64, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39VF010", SST_ID, SST_39VF010, 128, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, - {"SST", "SST39VF020", SST_ID, SST_39VF020, 256, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, + {"SST", "SST39VF020", SST_ID, SST_39VF020, 256, 4096, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39VF040", SST_ID, SST_39VF040, 512, 4096, TEST_OK_PROBE, probe_jedec, erase_chip_jedec, write_39sf020}, // assume similar to 004B, ignoring data sheet {"SST", "SST49LF002A/B", SST_ID, SST_49LF002A, 256, 16 * 1024, TEST_OK_PREW, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub},

1 0

[PATCH] Fix v3 build dependencies on build.h
by Carl-Daniel Hailfinger 18 Nov '08

18 Nov '08

Not a single file is being rebuilt in v3 if build.h changes. That means the console banner and the option table will never be updated with more recent build.h strings. The fix is not yet ready for committing because the x86emu changes could be avoided if someone fixed two or three lines in x86emu. Hint: x86emu doesn't care about the contents of build.h, it just uses build.h to check whether it is compiled in conjunction with coreboot. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-build_h_dependencies/lib/console.c =================================================================== --- corebootv3-build_h_dependencies/lib/console.c (Revision 984) +++ corebootv3-build_h_dependencies/lib/console.c (Arbeitskopie) @@ -6,6 +6,7 @@ #include <stdarg.h> #include <string.h> #include <globalvars.h> +#include <build.h> int vtxprintf(void (*)(unsigned char, void *arg), void *arg, const char *, va_list); Index: corebootv3-build_h_dependencies/lib/Makefile =================================================================== --- corebootv3-build_h_dependencies/lib/Makefile (Revision 984) +++ corebootv3-build_h_dependencies/lib/Makefile (Arbeitskopie) @@ -44,6 +44,11 @@ nrv2b: endif +$(obj)/lib/console.o: $(src)/lib/console.c $(obj)/build.h + $(Q)mkdir -p $(dir $@) + $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ + $(obj)/lib/%.o: $(src)/lib/%.c $(Q)mkdir -p $(dir $@) $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" Index: corebootv3-build_h_dependencies/Makefile =================================================================== --- corebootv3-build_h_dependencies/Makefile (Revision 984) +++ corebootv3-build_h_dependencies/Makefile (Arbeitskopie) @@ -88,8 +88,7 @@ -I$(src)/include \ -I$(src)/include/arch/$(ARCH)/ \ -I$(src)/mainboard/$(MAINBOARDDIR)/ \ - -include $(obj)/config.h \ - -include $(obj)/build.h + -include $(obj)/config.h CC := $(CC_$(ARCH)) AS := $(AS_$(ARCH)) Index: corebootv3-build_h_dependencies/util/x86emu/include/x86emu/x86emu.h =================================================================== --- corebootv3-build_h_dependencies/util/x86emu/include/x86emu/x86emu.h (Revision 984) +++ corebootv3-build_h_dependencies/util/x86emu/include/x86emu/x86emu.h (Arbeitskopie) @@ -43,6 +43,7 @@ #define __X86EMU_X86EMU_H /* FIXME: undefine printk for the moment */ +#include <build.h> #ifdef COREBOOT_VERSION #include <console.h> #define printk(x...) printk(BIOS_DEBUG, x) Index: corebootv3-build_h_dependencies/util/x86emu/Makefile =================================================================== --- corebootv3-build_h_dependencies/util/x86emu/Makefile (Revision 984) +++ corebootv3-build_h_dependencies/util/x86emu/Makefile (Arbeitskopie) @@ -44,7 +44,7 @@ # This rule is also valid for all subdirectories # -$(obj)/util/x86emu/%.o: $(src)/util/x86emu/%.c +$(obj)/util/x86emu/%.o: $(src)/util/x86emu/%.c $(obj)/build.h $(Q)mkdir -p $(dir $@) $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) $(INITCFLAGS) -I$(src)/util/x86emu/include -c $< -o $@ Index: corebootv3-build_h_dependencies/arch/x86/coreboot_table.c =================================================================== --- corebootv3-build_h_dependencies/arch/x86/coreboot_table.c (Revision 984) +++ corebootv3-build_h_dependencies/arch/x86/coreboot_table.c (Arbeitskopie) @@ -31,6 +31,7 @@ //#include <pirq_routing.h> //#include <smp/mpspec.h> //#include <acpi.h> +#include <build.h> struct lb_header *lb_table_init(unsigned long addr) { Index: corebootv3-build_h_dependencies/arch/x86/Makefile =================================================================== --- corebootv3-build_h_dependencies/arch/x86/Makefile (Revision 984) +++ corebootv3-build_h_dependencies/arch/x86/Makefile (Arbeitskopie) @@ -243,6 +243,11 @@ # Build rules. # +$(obj)/arch/x86/coreboot_table.o: $(src)/arch/x86/coreboot_table.c $(obj)/build.h + $(Q)mkdir -p $(dir $@) + $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ + $(obj)/arch/x86/%.o: $(src)/arch/x86/%.c $(Q)mkdir -p $(dir $@) $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" -- http://www.hailfinger.org/

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Re: [coreboot] r1034 - coreboot-v3/superio/winbond/w83627hf
by Peter Stuge 18 Nov '08

18 Nov '08

svn(a)coreboot.org wrote: > Fix some incorrect entries in superio/winbond/w83627hf/dts. > > The hardware monitor defaults as per datasheet are 0x0000 / 0, but on > hardware that uses this functionality it seems to be 0x290 / 5 often, > thus use those values in the dts. The hwmon wasn't changed in this patch? //Peter

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coreboot November 2008