coreboot November 2008

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490 discussions

Re: [coreboot] [patch] i82810 WIP for fixing VGA and 512MB
by z4ziggy＠gmail.com 18 Nov '08

18 Nov '08

On Nov 18, 2008 7:26am, Corey Osgood <corey.osgood(a)gmail.com> wrote: > On Mon, Nov 17, 2008 at 11:45 PM, Elia Yehuda z4ziggy(a)gmail.com> wrote: > > well, i managed to make it work as you initially suggested (adding .ops_pci to northbridge_operations), > but... i had to change the .device to 0x7124 (which is what lspci shows me) - are you all sure 82810 > > > device_id is 7120? i use 82810e but according to datasheet it should be the same. > > Nope, here's from my i810 datasheet: > > DIDDevice Identification Register (Device 0) > Address Offset: 02–03h > > Default Value: 82810 = 7120h > 82810-DC100 = 7122h > Attribute: Read Only > Size: 16 bits > > So, go ahead and do this: > > static const struct pci_driver i810_northbridge_driver __pci_driver = { > > > .ops = &northbridge_operations, > > .vendor = PCI_VENDOR_ID_INTEL, > > .device = 0x7120, > > }; > > static const struct pci_driver i810e_northbridge_driver __pci_driver = { > > .ops = &northbridge_operations, > > .vendor = PCI_VENDOR_ID_INTEL, > > .device = 0x7124, > > }; exactly what i just did! only different naming :-) thanks for all your info. > > Please do not be tempted to add i810-dc100 in there as well, unless you want to read through the i810 datasheet and fix any other differences ;) :) > > -Corey > > > > > > Elia. > > On Tue, Nov 18, 2008 at 6:04 AM, Corey Osgood corey.osgood(a)gmail.com> wrote: > > > > > > On Mon, Nov 17, 2008 at 10:10 PM, Elia Yehuda z4ziggy(a)gmail.com> wrote: > > > > > > > > > On Tue, Nov 18, 2008 at 3:44 AM, Joseph Smith joe(a)settoplinux.org> wrote: > > > > > > > > > On Tue, 18 Nov 2008 00:59:07 +0200, "Elia Yehuda" z4ziggy(a)gmail.com> > > wrote: > > > just noticed ive put it in cpu_bus_ops... have a laugh... > > > > > > No worries, this is how we learn :-) > > > > > > but i dont have "static struct device_operations mc_ops" - where should i > > > add > > > the .ops_pci ? > > > > > > Little confused about what your trying to do here. This doesn't work?? > > > > static const struct pci_driver northbridge_driver __pci_driver = { > > .ops = &northbridge_operations, > > .vendor = PCI_VENDOR_ID_INTEL, > > .device = 0x7120, > > }; > > > > this works just fine. i simply don't know where to add ".ops_pci" since i dont have > "static struct device_operations mc_ops" in northbridge.c > > > > > > > > > You should be able to add it to pci_domain_ops, but be sure to check that it actually runs. Otherwise, you'll need to create that mc_ops driver with just the .ops_pci and everything else set to NULL, and use this: > > > > > static void enable_dev(struct device *dev) > { > struct device_path path; //unused? > > /* Set the operations if it is a special bus type */ > if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { > dev->ops = &pci_domain_ops; > > > > pci_set_method(dev); > } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { > dev->ops = &cpu_bus_ops; > } else if (dev->path.type == DEVICE_PATH_PCI) { > dev->ops = &mc_ops; > > > > } > > > } > > I hope you can understand what I'm trying to say, I'ma bit tired right now. > > -Corey > > > > > > > > > > Elia.

1 0

[patch] i82810 WIP for fixing VGA and 512MB
by Elia Yehuda 18 Nov '08

18 Nov '08

Those 2 patches are one step towards having a working Onboard-VGA and 512MB (the max for i810). The raminit.c patch fixes some misconfigurations and probes the DIMMs correctly (all dual-sided are now recognized properly), and also set buffer_strength to handle 2 DIMMs although atm this doesn't work. The i82810/northbridge.c patch takes care of allocating Onboard-VGA memory. Signed-off-by: Elia Yehuda <z4ziggy(a)gmail.com>

5 18

[PATCH] flashrom: Make ICH SPI flash chip read more resilient
by Carl-Daniel Hailfinger 18 Nov '08

18 Nov '08

Currently flashrom assumes every vendor BIOS shares our view about which SPI opcodes should be placed in which location. Move to a less optimistic implementation and actually use the generic SPI read functions. They're useful for abstracting exactly this stuff and that makes them the preferred choice. This patch depends on the patch with improved SPI error checking. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich_spi_generalize/ichspi.c =================================================================== --- flashrom-ich_spi_generalize/ichspi.c (Revision 3754) +++ flashrom-ich_spi_generalize/ichspi.c (Arbeitskopie) @@ -300,7 +300,7 @@ if (op.atomic != 0) { /* Select atomic command */ temp16 |= SPIC_ACS; - /* Selct prefix opcode */ + /* Select prefix opcode */ if ((op.atomic - 1) == 1) { /*Select prefix opcode 2 */ temp16 |= SPIC_SPOP; @@ -491,19 +491,15 @@ for (a = 0; a < page_size; a += maxdata) { if (remaining < maxdata) { - if (run_opcode - (curopcodes->opcode[1], - offset + (page_size - remaining), remaining, - &buf[page_size - remaining]) != 0) { + if (spi_nbyte_read(offset + (page_size - remaining), + &buf[page_size - remaining], remaining)) { printf_debug("Error reading"); return 1; } remaining = 0; } else { - if (run_opcode - (curopcodes->opcode[1], - offset + (page_size - remaining), maxdata, - &buf[page_size - remaining]) != 0) { + if (spi_nbyte_read(offset + (page_size - remaining), + &buf[page_size - remaining], maxdata)) { printf_debug("Error reading"); return 1; } -- http://www.hailfinger.org/ Index: flashrom-ich_spi_generalize/ichspi.c =================================================================== --- flashrom-ich_spi_generalize/ichspi.c (Revision 3754) +++ flashrom-ich_spi_generalize/ichspi.c (Arbeitskopie) @@ -300,7 +300,7 @@ if (op.atomic != 0) { /* Select atomic command */ temp16 |= SPIC_ACS; - /* Selct prefix opcode */ + /* Select prefix opcode */ if ((op.atomic - 1) == 1) { /*Select prefix opcode 2 */ temp16 |= SPIC_SPOP; @@ -491,19 +491,15 @@ for (a = 0; a < page_size; a += maxdata) { if (remaining < maxdata) { - if (run_opcode - (curopcodes->opcode[1], - offset + (page_size - remaining), remaining, - &buf[page_size - remaining]) != 0) { + if (spi_nbyte_read(offset + (page_size - remaining), + &buf[page_size - remaining], remaining)) { printf_debug("Error reading"); return 1; } remaining = 0; } else { - if (run_opcode - (curopcodes->opcode[1], - offset + (page_size - remaining), maxdata, - &buf[page_size - remaining]) != 0) { + if (spi_nbyte_read(offset + (page_size - remaining), + &buf[page_size - remaining], maxdata)) { printf_debug("Error reading"); return 1; }

2 2

r3758 - trunk/util/flashrom
by svn＠coreboot.org 18 Nov '08

18 Nov '08

Author: hailfinger Date: 2008-11-18 01:43:14 +0100 (Tue, 18 Nov 2008) New Revision: 3758 Modified: trunk/util/flashrom/ichspi.c Log: Currently flashrom assumes every vendor BIOS shares our view about which SPI opcodes should be placed in which location. Move to a less optimistic implementation and actually use the generic SPI read functions. They're useful for abstracting exactly this stuff and that makes them the preferred choice. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/ichspi.c =================================================================== --- trunk/util/flashrom/ichspi.c 2008-11-18 00:41:02 UTC (rev 3757) +++ trunk/util/flashrom/ichspi.c 2008-11-18 00:43:14 UTC (rev 3758) @@ -300,7 +300,7 @@ if (op.atomic != 0) { /* Select atomic command */ temp16 |= SPIC_ACS; - /* Selct prefix opcode */ + /* Select prefix opcode */ if ((op.atomic - 1) == 1) { /*Select prefix opcode 2 */ temp16 |= SPIC_SPOP; @@ -491,19 +491,15 @@ for (a = 0; a < page_size; a += maxdata) { if (remaining < maxdata) { - if (run_opcode - (curopcodes->opcode[1], - offset + (page_size - remaining), remaining, - &buf[page_size - remaining]) != 0) { + if (spi_nbyte_read(offset + (page_size - remaining), + &buf[page_size - remaining], remaining)) { printf_debug("Error reading"); return 1; } remaining = 0; } else { - if (run_opcode - (curopcodes->opcode[1], - offset + (page_size - remaining), maxdata, - &buf[page_size - remaining]) != 0) { + if (spi_nbyte_read(offset + (page_size - remaining), + &buf[page_size - remaining], maxdata)) { printf_debug("Error reading"); return 1; }

1 0

[PATCH] flashrom: Check for failed SPI command execution
by Carl-Daniel Hailfinger 18 Nov '08

18 Nov '08

Check for failed SPI command execution in flashrom. Although SPI itself does not have a mechanism to signal command failure, the SPI host may be unable to send a given command over the wire due to security or hardware limitations. The current code ignores these mechanisms completely and simply assumes almost every command succeeds. Complain if SPI command execution fails. Since locked down Intel chipsets (like the one we had problems with earlier) only allow a small subset of commands, find the common subset of commands between the chipset and the ROM in the chip erase case. That is accomplished by the new spi_chip_erase_60_c7() which can be used for chips supporting both 0x60 and 0xc7 chip erase commands. Both parts of the patch address problems seen in the real world. The increased verbosity for the error case will help us diagnose and address problems better. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_error_checking/flash.h =================================================================== --- flashrom-spi_error_checking/flash.h (Revision 3754) +++ flashrom-spi_error_checking/flash.h (Arbeitskopie) @@ -452,19 +452,20 @@ int probe_spi_res(struct flashchip *flash); int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -void spi_write_enable(); -void spi_write_disable(); +int spi_write_enable(); +int spi_write_disable(); int spi_chip_erase_60(struct flashchip *flash); int spi_chip_erase_c7(struct flashchip *flash); +int spi_chip_erase_60_c7(struct flashchip *flash); int spi_chip_erase_d8(struct flashchip *flash); int spi_block_erase_52(const struct flashchip *flash, unsigned long addr); int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr); int spi_chip_write(struct flashchip *flash, uint8_t *buf); int spi_chip_read(struct flashchip *flash, uint8_t *buf); uint8_t spi_read_status_register(); -void spi_disable_blockprotect(void); +int spi_disable_blockprotect(void); void spi_byte_program(int address, uint8_t byte); -void spi_nbyte_read(int address, uint8_t *bytes, int len); +int spi_nbyte_read(int address, uint8_t *bytes, int len); /* 82802ab.c */ int probe_82802ab(struct flashchip *flash); Index: flashrom-spi_error_checking/spi.c =================================================================== --- flashrom-spi_error_checking/spi.c (Revision 3754) +++ flashrom-spi_error_checking/spi.c (Arbeitskopie) @@ -71,20 +71,20 @@ return 0; } -void spi_write_enable() +int spi_write_enable() { const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN }; /* Send WREN (Write Enable) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_command(sizeof(cmd), 0, cmd, NULL); } -void spi_write_disable() +int spi_write_disable() { const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; /* Send WRDI (Write Disable) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_command(sizeof(cmd), 0, cmd, NULL); } static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) @@ -274,14 +274,28 @@ int spi_chip_erase_60(struct flashchip *flash) { const unsigned char cmd[JEDEC_CE_60_OUTSIZE] = {JEDEC_CE_60}; + int result; - spi_disable_blockprotect(); - spi_write_enable(); + result = spi_disable_blockprotect(); + if (result) { + printf_debug("spi_disable_blockprotect failed\n"); + return result; + } + result = spi_write_enable(); + if (result) { + printf_debug("spi_write_enable failed\n"); + return result; + } /* Send CE (Chip Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_command(sizeof(cmd), 0, cmd, NULL); + if (result) { + printf_debug("spi_chip_erase_60 failed sending erase\n"); + return result; + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-85 s, so wait in 1 s steps. */ + /* FIXME: We assume spi_read_status_register will never fail. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) sleep(1); return 0; @@ -290,19 +304,44 @@ int spi_chip_erase_c7(struct flashchip *flash) { const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = { JEDEC_CE_C7 }; + int result; - spi_disable_blockprotect(); - spi_write_enable(); + result = spi_disable_blockprotect(); + if (result) { + printf_debug("spi_disable_blockprotect failed\n"); + return result; + } + result = spi_write_enable(); + if (result) { + printf_debug("spi_write_enable failed\n"); + return result; + } /* Send CE (Chip Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_command(sizeof(cmd), 0, cmd, NULL); + if (result) { + printf_debug("spi_chip_erase_60 failed sending erase\n"); + return result; + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-85 s, so wait in 1 s steps. */ + /* FIXME: We assume spi_read_status_register will never fail. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) sleep(1); return 0; } +int spi_chip_erase_60_c7(struct flashchip *flash) +{ + int result; + result = spi_chip_erase_60(flash); + if (result) { + printf_debug("spi_chip_erase_60 failed, trying c7\n"); + result = spi_chip_erase_c7(flash); + } + return result; +} + int spi_block_erase_52(const struct flashchip *flash, unsigned long addr) { unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52}; @@ -390,13 +429,13 @@ * This is according the SST25VF016 datasheet, who knows it is more * generic that this... */ -void spi_write_status_register(int status) +int spi_write_status_register(int status) { const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = { JEDEC_WRSR, (unsigned char)status }; /* Send WRSR (Write Status Register) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_command(sizeof(cmd), 0, cmd, NULL); } void spi_byte_program(int address, uint8_t byte) @@ -413,20 +452,30 @@ spi_command(sizeof(cmd), 0, cmd, NULL); } -void spi_disable_blockprotect(void) +int spi_disable_blockprotect(void) { uint8_t status; + int result; status = spi_read_status_register(); /* If there is block protection in effect, unprotect it first. */ if ((status & 0x3c) != 0) { printf_debug("Some block protection in effect, disabling\n"); - spi_write_enable(); - spi_write_status_register(status & ~0x3c); + result = spi_write_enable(); + if (result) { + printf_debug("spi_write_enable failed\n"); + return result; + } + result = spi_write_status_register(status & ~0x3c); + if (result) { + printf_debug("spi_write_status_register failed\n"); + return result; + } } + return 0; } -void spi_nbyte_read(int address, uint8_t *bytes, int len) +int spi_nbyte_read(int address, uint8_t *bytes, int len) { const unsigned char cmd[JEDEC_READ_OUTSIZE] = { JEDEC_READ, @@ -436,7 +485,7 @@ }; /* Send Read */ - spi_command(sizeof(cmd), len, cmd, bytes); + return spi_command(sizeof(cmd), len, cmd, bytes); } int spi_chip_read(struct flashchip *flash, uint8_t *buf) -- http://www.hailfinger.org/ Index: flashrom-spi_error_checking/flash.h =================================================================== --- flashrom-spi_error_checking/flash.h (Revision 3754) +++ flashrom-spi_error_checking/flash.h (Arbeitskopie) @@ -452,19 +452,20 @@ int probe_spi_res(struct flashchip *flash); int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -void spi_write_enable(); -void spi_write_disable(); +int spi_write_enable(); +int spi_write_disable(); int spi_chip_erase_60(struct flashchip *flash); int spi_chip_erase_c7(struct flashchip *flash); +int spi_chip_erase_60_c7(struct flashchip *flash); int spi_chip_erase_d8(struct flashchip *flash); int spi_block_erase_52(const struct flashchip *flash, unsigned long addr); int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr); int spi_chip_write(struct flashchip *flash, uint8_t *buf); int spi_chip_read(struct flashchip *flash, uint8_t *buf); uint8_t spi_read_status_register(); -void spi_disable_blockprotect(void); +int spi_disable_blockprotect(void); void spi_byte_program(int address, uint8_t byte); -void spi_nbyte_read(int address, uint8_t *bytes, int len); +int spi_nbyte_read(int address, uint8_t *bytes, int len); /* 82802ab.c */ int probe_82802ab(struct flashchip *flash); Index: flashrom-spi_error_checking/spi.c =================================================================== --- flashrom-spi_error_checking/spi.c (Revision 3754) +++ flashrom-spi_error_checking/spi.c (Arbeitskopie) @@ -71,20 +71,20 @@ return 0; } -void spi_write_enable() +int spi_write_enable() { const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN }; /* Send WREN (Write Enable) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_command(sizeof(cmd), 0, cmd, NULL); } -void spi_write_disable() +int spi_write_disable() { const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; /* Send WRDI (Write Disable) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_command(sizeof(cmd), 0, cmd, NULL); } static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) @@ -274,14 +274,28 @@ int spi_chip_erase_60(struct flashchip *flash) { const unsigned char cmd[JEDEC_CE_60_OUTSIZE] = {JEDEC_CE_60}; + int result; - spi_disable_blockprotect(); - spi_write_enable(); + result = spi_disable_blockprotect(); + if (result) { + printf_debug("spi_disable_blockprotect failed\n"); + return result; + } + result = spi_write_enable(); + if (result) { + printf_debug("spi_write_enable failed\n"); + return result; + } /* Send CE (Chip Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_command(sizeof(cmd), 0, cmd, NULL); + if (result) { + printf_debug("spi_chip_erase_60 failed sending erase\n"); + return result; + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-85 s, so wait in 1 s steps. */ + /* FIXME: We assume spi_read_status_register will never fail. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) sleep(1); return 0; @@ -290,19 +304,44 @@ int spi_chip_erase_c7(struct flashchip *flash) { const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = { JEDEC_CE_C7 }; + int result; - spi_disable_blockprotect(); - spi_write_enable(); + result = spi_disable_blockprotect(); + if (result) { + printf_debug("spi_disable_blockprotect failed\n"); + return result; + } + result = spi_write_enable(); + if (result) { + printf_debug("spi_write_enable failed\n"); + return result; + } /* Send CE (Chip Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_command(sizeof(cmd), 0, cmd, NULL); + if (result) { + printf_debug("spi_chip_erase_60 failed sending erase\n"); + return result; + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-85 s, so wait in 1 s steps. */ + /* FIXME: We assume spi_read_status_register will never fail. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) sleep(1); return 0; } +int spi_chip_erase_60_c7(struct flashchip *flash) +{ + int result; + result = spi_chip_erase_60(flash); + if (result) { + printf_debug("spi_chip_erase_60 failed, trying c7\n"); + result = spi_chip_erase_c7(flash); + } + return result; +} + int spi_block_erase_52(const struct flashchip *flash, unsigned long addr) { unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52}; @@ -390,13 +429,13 @@ * This is according the SST25VF016 datasheet, who knows it is more * generic that this... */ -void spi_write_status_register(int status) +int spi_write_status_register(int status) { const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = { JEDEC_WRSR, (unsigned char)status }; /* Send WRSR (Write Status Register) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_command(sizeof(cmd), 0, cmd, NULL); } void spi_byte_program(int address, uint8_t byte) @@ -413,20 +452,30 @@ spi_command(sizeof(cmd), 0, cmd, NULL); } -void spi_disable_blockprotect(void) +int spi_disable_blockprotect(void) { uint8_t status; + int result; status = spi_read_status_register(); /* If there is block protection in effect, unprotect it first. */ if ((status & 0x3c) != 0) { printf_debug("Some block protection in effect, disabling\n"); - spi_write_enable(); - spi_write_status_register(status & ~0x3c); + result = spi_write_enable(); + if (result) { + printf_debug("spi_write_enable failed\n"); + return result; + } + result = spi_write_status_register(status & ~0x3c); + if (result) { + printf_debug("spi_write_status_register failed\n"); + return result; + } } + return 0; } -void spi_nbyte_read(int address, uint8_t *bytes, int len) +int spi_nbyte_read(int address, uint8_t *bytes, int len) { const unsigned char cmd[JEDEC_READ_OUTSIZE] = { JEDEC_READ, @@ -436,7 +485,7 @@ }; /* Send Read */ - spi_command(sizeof(cmd), len, cmd, bytes); + return spi_command(sizeof(cmd), len, cmd, bytes); } int spi_chip_read(struct flashchip *flash, uint8_t *buf)

3 6

r3757 - trunk/util/flashrom
by svn＠coreboot.org 18 Nov '08

18 Nov '08

Author: hailfinger Date: 2008-11-18 01:41:02 +0100 (Tue, 18 Nov 2008) New Revision: 3757 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/spi.c Log: Check for failed SPI command execution in flashrom. Although SPI itself does not have a mechanism to signal command failure, the SPI host may be unable to send a given command over the wire due to security or hardware limitations. The current code ignores these mechanisms completely and simply assumes almost every command succeeds. Complain if SPI command execution fails. Since locked down Intel chipsets (like the one we had problems with earlier) only allow a small subset of commands, find the common subset of commands between the chipset and the ROM in the chip erase case. That is accomplished by the new spi_chip_erase_60_c7() which can be used for chips supporting both 0x60 and 0xc7 chip erase commands. Both parts of the patch address problems seen in the real world. The increased verbosity for the error case will help us diagnose and address problems better. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Otherwise: Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-11-18 00:36:26 UTC (rev 3756) +++ trunk/util/flashrom/flash.h 2008-11-18 00:41:02 UTC (rev 3757) @@ -452,19 +452,20 @@ int probe_spi_res(struct flashchip *flash); int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -void spi_write_enable(); -void spi_write_disable(); +int spi_write_enable(); +int spi_write_disable(); int spi_chip_erase_60(struct flashchip *flash); int spi_chip_erase_c7(struct flashchip *flash); +int spi_chip_erase_60_c7(struct flashchip *flash); int spi_chip_erase_d8(struct flashchip *flash); int spi_block_erase_52(const struct flashchip *flash, unsigned long addr); int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr); int spi_chip_write(struct flashchip *flash, uint8_t *buf); int spi_chip_read(struct flashchip *flash, uint8_t *buf); uint8_t spi_read_status_register(); -void spi_disable_blockprotect(void); +int spi_disable_blockprotect(void); void spi_byte_program(int address, uint8_t byte); -void spi_nbyte_read(int address, uint8_t *bytes, int len); +int spi_nbyte_read(int address, uint8_t *bytes, int len); /* 82802ab.c */ int probe_82802ab(struct flashchip *flash); Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2008-11-18 00:36:26 UTC (rev 3756) +++ trunk/util/flashrom/spi.c 2008-11-18 00:41:02 UTC (rev 3757) @@ -71,20 +71,20 @@ return 0; } -void spi_write_enable() +int spi_write_enable() { const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN }; /* Send WREN (Write Enable) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_command(sizeof(cmd), 0, cmd, NULL); } -void spi_write_disable() +int spi_write_disable() { const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; /* Send WRDI (Write Disable) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_command(sizeof(cmd), 0, cmd, NULL); } static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) @@ -274,14 +274,28 @@ int spi_chip_erase_60(struct flashchip *flash) { const unsigned char cmd[JEDEC_CE_60_OUTSIZE] = {JEDEC_CE_60}; + int result; - spi_disable_blockprotect(); - spi_write_enable(); + result = spi_disable_blockprotect(); + if (result) { + printf_debug("spi_disable_blockprotect failed\n"); + return result; + } + result = spi_write_enable(); + if (result) { + printf_debug("spi_write_enable failed\n"); + return result; + } /* Send CE (Chip Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_command(sizeof(cmd), 0, cmd, NULL); + if (result) { + printf_debug("spi_chip_erase_60 failed sending erase\n"); + return result; + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-85 s, so wait in 1 s steps. */ + /* FIXME: We assume spi_read_status_register will never fail. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) sleep(1); return 0; @@ -290,19 +304,44 @@ int spi_chip_erase_c7(struct flashchip *flash) { const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = { JEDEC_CE_C7 }; + int result; - spi_disable_blockprotect(); - spi_write_enable(); + result = spi_disable_blockprotect(); + if (result) { + printf_debug("spi_disable_blockprotect failed\n"); + return result; + } + result = spi_write_enable(); + if (result) { + printf_debug("spi_write_enable failed\n"); + return result; + } /* Send CE (Chip Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_command(sizeof(cmd), 0, cmd, NULL); + if (result) { + printf_debug("spi_chip_erase_60 failed sending erase\n"); + return result; + } /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-85 s, so wait in 1 s steps. */ + /* FIXME: We assume spi_read_status_register will never fail. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) sleep(1); return 0; } +int spi_chip_erase_60_c7(struct flashchip *flash) +{ + int result; + result = spi_chip_erase_60(flash); + if (result) { + printf_debug("spi_chip_erase_60 failed, trying c7\n"); + result = spi_chip_erase_c7(flash); + } + return result; +} + int spi_block_erase_52(const struct flashchip *flash, unsigned long addr) { unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52}; @@ -390,13 +429,13 @@ * This is according the SST25VF016 datasheet, who knows it is more * generic that this... */ -void spi_write_status_register(int status) +int spi_write_status_register(int status) { const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = { JEDEC_WRSR, (unsigned char)status }; /* Send WRSR (Write Status Register) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_command(sizeof(cmd), 0, cmd, NULL); } void spi_byte_program(int address, uint8_t byte) @@ -413,20 +452,30 @@ spi_command(sizeof(cmd), 0, cmd, NULL); } -void spi_disable_blockprotect(void) +int spi_disable_blockprotect(void) { uint8_t status; + int result; status = spi_read_status_register(); /* If there is block protection in effect, unprotect it first. */ if ((status & 0x3c) != 0) { printf_debug("Some block protection in effect, disabling\n"); - spi_write_enable(); - spi_write_status_register(status & ~0x3c); + result = spi_write_enable(); + if (result) { + printf_debug("spi_write_enable failed\n"); + return result; + } + result = spi_write_status_register(status & ~0x3c); + if (result) { + printf_debug("spi_write_status_register failed\n"); + return result; + } } + return 0; } -void spi_nbyte_read(int address, uint8_t *bytes, int len) +int spi_nbyte_read(int address, uint8_t *bytes, int len) { const unsigned char cmd[JEDEC_READ_OUTSIZE] = { JEDEC_READ, @@ -436,7 +485,7 @@ }; /* Send Read */ - spi_command(sizeof(cmd), len, cmd, bytes); + return spi_command(sizeof(cmd), len, cmd, bytes); } int spi_chip_read(struct flashchip *flash, uint8_t *buf)

1 0

Implement read support for Atmel SPI chips
by Carl-Daniel Hailfinger 18 Nov '08

18 Nov '08

Implement read support for the following Atmel chips: AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF041 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 I double-checked the data sheets and am confident this will work. Attached for gmail users. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-atmel_read/flashchips.c =================================================================== --- flashrom-atmel_read/flashchips.c (Revision 3754) +++ flashrom-atmel_read/flashchips.c (Arbeitskopie) @@ -38,23 +38,23 @@ {"AMD", "Am29F040B", AMD_ID, AM_29F040B, 512, 64 * 1024, TEST_OK_PREW, probe_29f040b, erase_29f040b, write_29f040b}, {"AMD", "Am29LV040B", AMD_ID, AM_29LV040B, 512, 64 * 1024, TEST_UNTESTED, probe_29f040b, erase_29f040b, write_29f040b}, {"ASD", "AE49F2008", ASD_ID, ASD_AE49F2008, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, - {"Atmel", "AT25DF021", ATMEL_ID, AT_25DF021, 256, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25DF041A", ATMEL_ID, AT_25DF041A, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25DF081", ATMEL_ID, AT_25DF081, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25DF161", ATMEL_ID, AT_25DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF021", ATMEL_ID, AT_25DF021, 256, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25DF041A", ATMEL_ID, AT_25DF041A, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25DF081", ATMEL_ID, AT_25DF081, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25DF161", ATMEL_ID, AT_25DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"Atmel", "AT25DF321A", ATMEL_ID, AT_25DF321A, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25DF641", ATMEL_ID, AT_25DF641, 8192, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25F512B", ATMEL_ID, AT_25F512B, 64, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25FS010", ATMEL_ID, AT_25FS010, 128, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25FS040", ATMEL_ID, AT_25FS040, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT26DF041", ATMEL_ID, AT_26DF041, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL}, - {"Atmel", "AT26DF081A", ATMEL_ID, AT_26DF081A, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT26DF161", ATMEL_ID, AT_26DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT26DF161A", ATMEL_ID, AT_26DF161A, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF321A", ATMEL_ID, AT_25DF321A, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25DF641", ATMEL_ID, AT_25DF641, 8192, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25F512B", ATMEL_ID, AT_25F512B, 64, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25FS010", ATMEL_ID, AT_25FS010, 128, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25FS040", ATMEL_ID, AT_25FS040, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT26DF041", ATMEL_ID, AT_26DF041, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */,spi_chip_read}, + {"Atmel", "AT26DF081A", ATMEL_ID, AT_26DF081A, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT26DF161", ATMEL_ID, AT_26DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT26DF161A", ATMEL_ID, AT_26DF161A, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, /*The AT26DF321 has the same ID as the AT25DF321. */ - /*{"Atmel", "AT26DF321", ATMEL_ID, AT_26DF321, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL},*/ - {"Atmel", "AT26F004", ATMEL_ID, AT_26F004, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL}, + /*{"Atmel", "AT26DF321", ATMEL_ID, AT_26DF321, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read},*/ + {"Atmel", "AT26F004", ATMEL_ID, AT_26F004, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */,spi_chip_read}, {"Atmel", "AT29C020", ATMEL_ID, AT_29C020, 256, 256, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT29C040A", ATMEL_ID, AT_29C040A, 512, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT45CS1282", ATMEL_ID, AT_45CS1282, 16896/*!*/,1056/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL /* Incompatible read */}, /* No power of two sizes */ -- http://www.hailfinger.org/ Index: flashrom-atmel_read/flashchips.c =================================================================== --- flashrom-atmel_read/flashchips.c (Revision 3754) +++ flashrom-atmel_read/flashchips.c (Arbeitskopie) @@ -38,23 +38,23 @@ {"AMD", "Am29F040B", AMD_ID, AM_29F040B, 512, 64 * 1024, TEST_OK_PREW, probe_29f040b, erase_29f040b, write_29f040b}, {"AMD", "Am29LV040B", AMD_ID, AM_29LV040B, 512, 64 * 1024, TEST_UNTESTED, probe_29f040b, erase_29f040b, write_29f040b}, {"ASD", "AE49F2008", ASD_ID, ASD_AE49F2008, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, - {"Atmel", "AT25DF021", ATMEL_ID, AT_25DF021, 256, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25DF041A", ATMEL_ID, AT_25DF041A, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25DF081", ATMEL_ID, AT_25DF081, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25DF161", ATMEL_ID, AT_25DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF021", ATMEL_ID, AT_25DF021, 256, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25DF041A", ATMEL_ID, AT_25DF041A, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25DF081", ATMEL_ID, AT_25DF081, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25DF161", ATMEL_ID, AT_25DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"Atmel", "AT25DF321A", ATMEL_ID, AT_25DF321A, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25DF641", ATMEL_ID, AT_25DF641, 8192, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25F512B", ATMEL_ID, AT_25F512B, 64, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25FS010", ATMEL_ID, AT_25FS010, 128, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25FS040", ATMEL_ID, AT_25FS040, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT26DF041", ATMEL_ID, AT_26DF041, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL}, - {"Atmel", "AT26DF081A", ATMEL_ID, AT_26DF081A, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT26DF161", ATMEL_ID, AT_26DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT26DF161A", ATMEL_ID, AT_26DF161A, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF321A", ATMEL_ID, AT_25DF321A, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25DF641", ATMEL_ID, AT_25DF641, 8192, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25F512B", ATMEL_ID, AT_25F512B, 64, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25FS010", ATMEL_ID, AT_25FS010, 128, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25FS040", ATMEL_ID, AT_25FS040, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT26DF041", ATMEL_ID, AT_26DF041, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */,spi_chip_read}, + {"Atmel", "AT26DF081A", ATMEL_ID, AT_26DF081A, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT26DF161", ATMEL_ID, AT_26DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT26DF161A", ATMEL_ID, AT_26DF161A, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, /*The AT26DF321 has the same ID as the AT25DF321. */ - /*{"Atmel", "AT26DF321", ATMEL_ID, AT_26DF321, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL},*/ - {"Atmel", "AT26F004", ATMEL_ID, AT_26F004, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL}, + /*{"Atmel", "AT26DF321", ATMEL_ID, AT_26DF321, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read},*/ + {"Atmel", "AT26F004", ATMEL_ID, AT_26F004, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */,spi_chip_read}, {"Atmel", "AT29C020", ATMEL_ID, AT_29C020, 256, 256, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT29C040A", ATMEL_ID, AT_29C040A, 512, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT45CS1282", ATMEL_ID, AT_45CS1282, 16896/*!*/,1056/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL /* Incompatible read */}, /* No power of two sizes */

2 2

r3756 - trunk/util/flashrom
by svn＠coreboot.org 18 Nov '08

18 Nov '08

Author: hailfinger Date: 2008-11-18 01:36:26 +0100 (Tue, 18 Nov 2008) New Revision: 3756 Modified: trunk/util/flashrom/flashchips.c Log: Implement read support for the following Atmel chips: AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF041 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 I double-checked the data sheets and am confident this will work. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-11-17 15:31:56 UTC (rev 3755) +++ trunk/util/flashrom/flashchips.c 2008-11-18 00:36:26 UTC (rev 3756) @@ -38,23 +38,23 @@ {"AMD", "Am29F040B", AMD_ID, AM_29F040B, 512, 64 * 1024, TEST_OK_PREW, probe_29f040b, erase_29f040b, write_29f040b}, {"AMD", "Am29LV040B", AMD_ID, AM_29LV040B, 512, 64 * 1024, TEST_UNTESTED, probe_29f040b, erase_29f040b, write_29f040b}, {"ASD", "AE49F2008", ASD_ID, ASD_AE49F2008, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, - {"Atmel", "AT25DF021", ATMEL_ID, AT_25DF021, 256, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25DF041A", ATMEL_ID, AT_25DF041A, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25DF081", ATMEL_ID, AT_25DF081, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25DF161", ATMEL_ID, AT_25DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF021", ATMEL_ID, AT_25DF021, 256, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25DF041A", ATMEL_ID, AT_25DF041A, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25DF081", ATMEL_ID, AT_25DF081, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25DF161", ATMEL_ID, AT_25DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"Atmel", "AT25DF321A", ATMEL_ID, AT_25DF321A, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25DF641", ATMEL_ID, AT_25DF641, 8192, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25F512B", ATMEL_ID, AT_25F512B, 64, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25FS010", ATMEL_ID, AT_25FS010, 128, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT25FS040", ATMEL_ID, AT_25FS040, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT26DF041", ATMEL_ID, AT_26DF041, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL}, - {"Atmel", "AT26DF081A", ATMEL_ID, AT_26DF081A, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT26DF161", ATMEL_ID, AT_26DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, - {"Atmel", "AT26DF161A", ATMEL_ID, AT_26DF161A, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL}, + {"Atmel", "AT25DF321A", ATMEL_ID, AT_25DF321A, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25DF641", ATMEL_ID, AT_25DF641, 8192, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25F512B", ATMEL_ID, AT_25F512B, 64, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25FS010", ATMEL_ID, AT_25FS010, 128, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT25FS040", ATMEL_ID, AT_25FS040, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT26DF041", ATMEL_ID, AT_26DF041, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */,spi_chip_read}, + {"Atmel", "AT26DF081A", ATMEL_ID, AT_26DF081A, 1024, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT26DF161", ATMEL_ID, AT_26DF161, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, + {"Atmel", "AT26DF161A", ATMEL_ID, AT_26DF161A, 2048, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read}, /*The AT26DF321 has the same ID as the AT25DF321. */ - /*{"Atmel", "AT26DF321", ATMEL_ID, AT_26DF321, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, NULL},*/ - {"Atmel", "AT26F004", ATMEL_ID, AT_26F004, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL}, + /*{"Atmel", "AT26DF321", ATMEL_ID, AT_26DF321, 4096, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL, spi_chip_read},*/ + {"Atmel", "AT26F004", ATMEL_ID, AT_26F004, 512, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL /* Incompatible Page write */,spi_chip_read}, {"Atmel", "AT29C020", ATMEL_ID, AT_29C020, 256, 256, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT29C040A", ATMEL_ID, AT_29C040A, 512, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT45CS1282", ATMEL_ID, AT_45CS1282, 16896/*!*/,1056/*!*/, TEST_BAD_READ, probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL /* Incompatible read */}, /* No power of two sizes */

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v3 amd8111 wrong ops
by Myles Watson 18 Nov '08

18 Nov '08

This didn't fix everything, but it helps. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 2

r1041 - coreboot-v3/southbridge/amd/amd8111
by svn＠coreboot.org 18 Nov '08

18 Nov '08

Author: myles Date: 2008-11-17 23:24:11 +0100 (Mon, 17 Nov 2008) New Revision: 1041 Modified: coreboot-v3/southbridge/amd/amd8111/ac97audio.dts coreboot-v3/southbridge/amd/amd8111/acpi.dts Log: Correct ops pointers in amd8111 dts. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/southbridge/amd/amd8111/ac97audio.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ac97audio.dts 2008-11-17 20:40:39 UTC (rev 1040) +++ coreboot-v3/southbridge/amd/amd8111/ac97audio.dts 2008-11-17 22:24:11 UTC (rev 1041) @@ -18,6 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ { - device_operations = "ac97modem"; + device_operations = "ac97audio"; /* configuration variables go here */ }; Modified: coreboot-v3/southbridge/amd/amd8111/acpi.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8111/acpi.dts 2008-11-17 20:40:39 UTC (rev 1040) +++ coreboot-v3/southbridge/amd/amd8111/acpi.dts 2008-11-17 22:24:11 UTC (rev 1041) @@ -19,6 +19,6 @@ */ { - device_operations = "ac97modem"; + device_operations = "acpi"; /* configuration variables go here */ };

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coreboot November 2008